JP3067408B2 - Diagnosis method of memory access control device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a diagnostic method for a memory access control device connected to a main memory.

[0002]

2. Description of the Related Art Conventionally, diagnosis of a memory access control device is performed by a control from a diagnostic processing device after a start-up process, and a hardware area unique to each device such as a port portion is actually connected to another device. Or using a specific diagnostic program.

[0003]

In the above-described conventional diagnostic method of the memory access control device, before connecting the arithmetic processing unit and the input / output processing unit, a hardware area specific to each device such as a port unit is previously determined. There is a problem that the diagnosis cannot be executed by the memory access control device itself at a high speed as in the state where each device is connected.

[0004]

According to the present invention, there is provided a diagnostic method for a memory access control device which performs a main memory access process from a plurality of access request sources, wherein a request source device number, a request code, a request address, A control memory having write data and a field for controlling the inside of the memory access control device; a steady detection device for detecting that there is no valid request in the memory access control device;
When "1", the diagnosis start flag means is set to "1" when an instruction is received from the processing device, and when the diagnosis start flag means is "1", the execution start address for diagnosis in the control memory is set. Is set, furthermore, an address register whose address is updated, a diagnosis start flag means when the last address of the diagnosis execution is detected, a comparison means for resetting the address register, and a register means for storing an output of the control memory, Request holding means for generating and outputting a request hold signal to the request source device indicated by the register means and suppressing the reception of the request; reply suppression means for suppressing transmission of the reply signal to the request source device indicated by the register means 7; The original request code, address data, and the request A reception buffer for selectively inputting a request, a request code, and data by an output of the register unit; a selection unit for performing a busy check of a plurality of requests from the reception buffer, further determining a priority, and outputting one request; A request processing unit for processing a request to the selecting unit is provided, and the diagnosis of the memory access control device can be performed not only at the time of startup but also at a high speed after the startup.

[0005]

Next, the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention.

The memory access control device according to the present embodiment is connected to a request request source such as an arithmetic processing unit (EPU0, EPU2) or an input processing unit (IOP0, IOP2) and a main storage device 140. In this embodiment, EPU0, EPU2, IO are used as request request sources.
It has four devices, P0 and IOPP2. This memory access control device is roughly composed of a request reception port unit and a request processing unit.

In the figure, reference numeral 210 denotes an AND of a diagnosis start signal from the diagnosis processing device and an output 360 of the steady detection circuit 300.
This is a diagnosis start F / F set by D. Diagnosis start F /
F210 is reset when the CS address register 100 indicates a constant value and the diagnostic program ends.

Reference numeral 300 denotes a steady detection circuit for detecting that there is no valid request in the memory access control device, and outputs "1" for one clock only in a steady state pulse. The input is a steady signal 310 indicating that there is no valid request in the reception buffer 110 and the buffer read register 114 for EPU0, and the EPU2
Signal 320 for IOP0, steady signal 330 for IOP2, and steady signal 3 for IOP2
40, a request processing unit steady signal 35 indicating that there is no request being processed by the request processing unit 120.
0. The output 360 of the steady detection circuit is input to the AND gater 400.

The output of the diagnosis start F / F 210 gives a set instruction to the address register 100, and the CS address is updated to +1 at every clock to execute the diagnosis program. 220 is the CS address register 100
Is a comparator for detecting that the output of the second comparator has reached a constant value.
Reference numeral 100 denotes a CS address register that holds a read / write address of CS (CONTROL CLOCK), and operates as an 11 counter while the set signal from the diagnosis start F / F 210 is being output.

Reference numeral 101 denotes a CS to the CS 103 at the time of initial setting.
At the time of startup in the write data register, the diagnostic processing device sets the write address and the write signal. 1
Reference numeral 02 denotes a CS write signal register for receiving a write signal to the CS from the diagnostic processing device. Reference numeral 103 denotes a CS, in which control fields (details will be described later) inside the memory access control device, device designation, request code, request address, and data Having.

FIG. 2A shows the contents of the field at address 0 of the CS 103. The contents are ALL0 and do nothing as an operation. As shown in FIG. 2 (2), the contents of the internal fields include setting and release of a request hold for each device, setting and release of a reply suppression mode, and a hit indicating the validity of the request code, request address and data in the CS 103 Consists of All of these commands are valid for the device specified in the device specification field.

The contents of the device designation field are shown in FIG.
As shown in the figure, EPU0 and EP consist of 4 bits from the left.
U2, IOP0, and IOP2. Simultaneous designation is also possible. Commands in the internal control field are valid for the device specified. Therefore, the request hold setting and reply suppression mode of the internal control
EPU0, EPU2, IPO if the bit is 1 "and the device designation field is all bits" 1 "
0, the request hold F / F and reply suppression F / F of IOP2 are set to "1".

The request code field has a format similar to that of the interface with each device, and has a read /
A request address / data field having a bit indicating an operation such as writing and a mask bit corresponding to a byte at the time of partial writing also has the same format as the interface with each device.

Reference numeral 104 denotes a CS read register for receiving the output of the CS 103, and reference numeral 105 denotes an AND date to generate and output a control signal to each unit from the output of the CS read register 104.

Here, a rough processing flow at the time of executing a diagnosis will be described. In the diagnosis corresponding to each device, a request is output from the content of the CS 103 inside the memory access control device and output to each port, so that the request conflicts with a request from the request source. Therefore, the request hold F / F 160, 161,
162, 163. Further, since the diagnostic command is generated and executed in the memory access control device, a reply to this request must not be sent to each device. Therefore, reply suppression F / Fs 170 and 17 corresponding to each device are provided.
1,172,173.

The diagnostic processing device performs a request hold F / F 160 to 163 and a reply suppression F / F
170 to 173 are set, and a command to be executed next is specified (specifically, a CS address in which a request to be processed is stored is given). When the diagnosis is completed, the request hold F / F 160 to 163 and the reply suppression F / F
F170 to 173 are released, and the state is ended in which the request from the request source can be accepted.

The command for realizing such an operation is C
It is held as a microinstruction inside S103,
The diagnostic processing device executes by giving a track signal and an address.

The AND date 105 generates an AND condition in the internal control field and the device designation field, and generates a request hole setting / release signal and a reply F / F setting / release signal, respectively. Further, the reception buffer 110
1 to 113 are instructed to take in the request code, request address, and request data in the CS read register 104.

Reference numeral 110 denotes a reception buffer for receiving a request from the EPU0. Normally, a request from the EPU0 is input. However, the request code / address valid bit in the CS read register 104 is "1" and the
If the device designation in the read register 104 is EPU0, the request code, address, and data output from the CS read register 104 are input. 111, 11
Reference numerals 2 and 113 denote reception buffers for EPU2, IOP0 and IOP2, respectively. 114 is the reception buffer 110
A buffer read register that receives an output and outputs it to the request processing unit 120. 115, 116 and 117 are buffer read registers for EPU2, IOP0 and IOP2, respectively.

Reference numeral 118 denotes a buffer read register 11
4, 115, 116, 117, the request stored in the request processor 1
And a request processing unit 120 for receiving and processing the request output from the selection circuit 118.
The data is read from the main storage device 140, a write request is output, and a reply data is received. Reference numeral 130 denotes a reply destination determining circuit which determines the request source of the request and outputs each reply signal and reply data. A main storage unit 140 receives a requester from the request processing unit 120 and returns reply data. 151, 152, 15
3, 154 are EPU0, EPU2, IOP0,
This is a reply data register for IOP2.

Reference numeral 160 denotes a request hold F / F for outputting a signal for suppressing the transmission of a request to the EPU0.
It is set and released by the output of the reading register 104. The setting is made before the diagnosis of EPU0 is performed, and the setting is canceled after the diagnosis of EPU0 is completed. 161,1
62, 163 are EPU2, IOP0, IOP2, respectively.
Is a request hold F / F.

Reference numeral 170 denotes a reply suppression F / F for suppressing a reply signal to EPU0, and a request hold F / F
As in the case of F160, it is set and released by the output of the CS read register 104. When this F / F is "1", the reply signal to EPU0 is completely suppressed.
This is because inconsistency arises when a reply is sent to a request that has not been issued by the EPU0 at the time of diagnosis execution.
/ F160 and reply suppression F / F170 are set to "1", and are released at the same time when the diagnosis is completed. 171, 17
Reference numerals 2173 denote reply inhibition F / Fs for EPU2, IOP0, and IOP2, respectively.

Reference numeral 180 denotes a reply signal of EPU0 from the reply destination determination circuit 130 and a request suppression F / F 17
This is a reply valid register for ANDing the output of 0 and inputting it. Only when this output is "1", the contents of the reply data register 151 are significant. 181,182,1
83, 184 are EPU2, IOP0, IOP, respectively.
2 is a reply valid register.

Further, a bus for reporting a failure of the memory access control unit to the diagnostic processing unit is provided. Therefore, after the diagnosis is completed, the diagnosis processing device can recognize the failure of the memory access control device based on the presence or absence of the failure report.

In this embodiment, all hardware areas including each port are automatically set during or after system startup by the memory access control unit without connecting to each arithmetic processing unit and input / output processing unit. Diagnosis can be executed at high speed. Furthermore, since (port) diagnosis can be performed on a plurality of devices at the same time, the processing can be performed at a very high speed.

FIG. 3 shows another embodiment of the present invention. This embodiment is provided with an OR gate 500, and is capable of freely stopping at an arbitrary timing even during diagnosis by performing a logical sum of a forced stop instruction from the diagnostic processing device and an output of the comparator. This is different from the first embodiment.

[0028]

As described in the present embodiment, according to the present invention, before connecting the arithmetic processing unit and the input / output processing unit, the diagnosis of all hardware areas including the interface part is performed in memorial. There is an effect that the access control device can execute the program at high speed.

[Brief description of the drawings]

FIG. 1 is a block diagram of one embodiment of the present invention.

FIG. 2 is a diagram showing detailed information of a CS field according to the present invention.

FIG. 3 is a block diagram of another embodiment of the present invention.

[Explanation of symbols]

 REFERENCE SIGNS LIST 100 CS address register 101 CS write data register 102 CS write signal register 103 CS (CONTROL STRAGE) 104 CS read register 105 AND gate 110 reception buffer 111 reception buffer 112 reception buffer 113 reception buffer 114 buffer read register 115 buffer read register 116 Buffer read register 117 Buffer read register 118 Selection circuit 120 Request processing unit 130 Reply destination determination circuit 140 Main storage device 151 Reply data register 152 Reply data register 153 Reply data register 154 Reply data register 160 Request hold F / F 161 Request hold F / F 162 Request Ho F / F 163 Request hold F / F 170 Reply suppression F / F 171 Reply suppression F / F 172 Reply suppression F / F 173 Reply suppression F / F 180 Reply valid register 181 Reply valid register 182 Reply valid register 183 Reply valid register 210 Diagnosis start F / F 220 Comparator 300 Steady detection circuit 310 Steady signal 320 Steady signal 330 Steady signal 340 Steady signal 350 Request processing part steady signal 360 Steady detect circuit output 400 AND circuit 500 OR circuit

Continuation of the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) G06F 11/22 G06F 12/16

Claims (2)

(57) [Claims] 1. A method of diagnosing a memory access control device for performing a main memory access process from a plurality of access request sources, comprising: a request source device number, a request code, a request address, write data, and a memory access control device. A control memory having a field for control; a steady detection means for detecting that there is no valid request in the memory access control device; and an instruction from the processing device when the steady detection means output is "1" A diagnosis start flag means which is set to "1" at the time, an execution start address for the diagnosis to the control memory when the diagnosis start flag means is "1", and an address register for updating the address. When the end address of the diagnosis is detected, the diagnosis start flag means and the address register are detected. Comparing means for resetting a register, register means for storing the output of the control memory, request holding means for generating and outputting a request hold signal to a request source device indicated by the register means, and suppressing reception of a request; A reply inhibiting means for suppressing transmission of a reply signal to the request source device indicated by 7; a request code, address data from the request source and a request address, a request code, and data output from the register means by an output of the register means; A reception buffer for selecting and inputting, a selection unit for performing a busy check of a plurality of requests from the reception buffer, determining a priority, and outputting one request, and a request processing unit for processing a request to the selection unit. Memory access A diagnostic method for a memory access control device, characterized in that diagnosis of a memory access control device can be performed not only at the time of startup but also at the time of startup. 2. The diagnosis method for a memory access control device according to claim 1, further comprising a forced diagnosis stop means, wherein start and stop of the execution of the diagnosis can be freely set by a diagnosis processing device.