JP2710219B2 - DMA controller - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a DMA controller,
In particular, the present invention relates to a DMA control device having a bit string transfer function and used for controlling data transfer between memory devices in an information processing system.

[0002]

2. Description of the Related Art A conventional DMA controller of this type includes a bit string processing register group (general purpose register) corresponding to an external bus 106 and internal buses 107 and 108, as shown in FIG. 2 including a CPU 2 including an arithmetic processing circuit 3 and a transfer source address register 1
2, destination address register 13, count register 1
Control circuit 11 including mode register 4 and mode register 15
And a bus interface / bus arbiter 16.

[0003] In FIG 6, the transfer source address, transfer destination A <br/> drain scan and transfer byte number (count) in advance, the transfer source address register 12, respectively included in the DMA control circuit 11, the transfer destination address register 13 and the corresponding registers of the count register 14, and are set in response to a DMA request signal 101 from an external device.
The transfer source memory data 70 in the data format shown in FIG.
1 and the transfer destination memory data 702, data transfer between the memory devices is performed. On the other hand, in the data transfer between memory devices, as shown in FIG.
03 is transferred by designating the bit offset 704 from the first bit of the specific address, the CPU unit 1 includes the case where the logical operation is not executed by the transfer destination memory data 705 and the transfer source memory data 703. The date transfer is executed by necessarily using the bitstone ring transfer function that depends on the processing action of the software provided in the data transfer.

[0004]

SUMMARY OF THE INVENTION The above-described conventional DMA
In the control device, there is no other way to execute the bit string transfer between the memory devices except depending on the processing operation by the software in the CPU unit, and therefore, the asynchronous operation is performed by the DMA request signal input from the external device. The request cannot respond to the bit string transfer. Therefore, in the data transfer operation, in order to support the bit string transfer,
There is an operational disadvantage that it is necessary to always manage the data transfer operation on the program of the CPU unit.

The present invention solves the above-mentioned drawbacks, and can execute a bit string transfer function without requiring program operation management even for an asynchronous data transfer request by an external DMA request signal. And to provide a DMA controller.

[0006]

A DMA controller according to the present invention receives a DMA request signal from the outside and arbitrates the right to use a bus with another bus master including another DMA channel and another CPU unit. A bus interface / arbiter to be performed, a DMA control unit that inputs a DMA request signal output from the bus interface / arbiter, and performs a DMA transfer according to a specified predetermined method; and a calculation instruction output from the DMA control unit via the transfer, the data of an arbitrary bit length, the data transfer instruction of the CPU unit
It is characterized by comprising at least a CPU unit having a bit string function of performing data transfer between a source memory and a destination memory.

When a DMA request signal output from the bus interface / bus arbiter is input into the DMA control unit to perform a DMA transfer, the DMA transfer data length of the corresponding channel is not a byte / word unit but a fraction. When the bit is generated, the data is temporarily stored in the DMA.
A bit string control circuit for executing a normal DMA transfer process after capturing the data in the control device and performing the transfer of the fractional bits may be additionally provided.
When a DMA request signal output from the bus interface / bus arbiter is input into the MA control unit to perform a DMA transfer, if the DMA transfer data length of the corresponding channel is not a byte / word unit but a fraction bit, data temporarily taken into the DMA control unit and after performing the transfer of the fraction bits, together comprise together bit string control circuit performs normal DMA transfer process, to the bit string control circuit, the rolling < the br /><br/> logic operation according to the bit string functions performed between the data in Okumoto memory and data of the transfer destination memory, the arithmetic processing circuit that executes on behalf of the CPU unit At least it may be provided.

[0008]

Next, the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing a first embodiment of the present invention. As shown in FIG. 1, this embodiment corresponds to the external bus 106, the internal buses 107 and 108,
Bit string processing registers (general purpose registers) 2
And a CPU section 1 including an arithmetic processing circuit 3, a bit string control circuit 5, a processing selection register 10 and a DM
A DMA control unit 4 including an A control circuit 11 and a bus interface / bus arbiter 16 are provided.
Note and the bit string control circuit 5 includes an operational selection register 6, the bit length setting register 7, is formed by the source bit offset register 8 and the destination bit offset register 9, before Symbol DMA control circuit 11, the transfer source address register 12. Transfer destination address register 1
3, a count register 14 and a mode register 15. FIG. 2 is a flowchart illustrating a processing procedure when a DMA request signal is input from the outside in the present embodiment. Hereinafter, the operation of the present embodiment will be described with reference to FIGS.

Referring to FIG. 1, when a DMA request signal 101 is input from an external device and a DMA transfer request occurs (step 201), arbitration with another DMA channel is performed by the bus interface / bus arbiter 16 in the microprocessor. It is determined whether the channel is the highest priority channel (step 2).
02) If the channel is determined to be the highest priority channel, the bus interface / bus arbiter 16
A hold request signal 103 is output to the CPU unit 1, and in response to the input of the hold request signal 103, C
An acknowledgment signal 104 is output from the PU unit 1,
This is returned to the bus interface / bus arbiter 16.
When the acknowledge signal 104 is returned to the bus interface / bus arbiter 16, a predetermined control signal 105 is output from the bus interface / bus arbiter 16 and is input to the DMA control circuit 11. Then, the DMA control unit 4 is controlled by the control signal 105.
Is started (step 203). If the channel is not the highest priority in step 202, the process returns to step 202 again.
The determination process is continuously performed.

After the step 203, in the mode register 15 included in the DMA control circuit 11, the data transfer target is specified to be between the memory devices or between the memory device and the I / O device. Is determined (step 204). In this case, if the data transfer between the memories is specified in advance, the presence or absence of the arithmetic processing is determined as the corresponding processing step (step 205). If it is determined in step 205 that the arithmetic processing is not required, it is determined whether or not the data transfer is a data transfer with a bit offset (step 2).
08) If it is set that the data transfer has no bit offset (no operation), the process is immediately returned to the DMA control circuit 11 to determine whether or not the DMA data transfer has the highest priority. is determined (step 212), then,
Normal DMA data transfer is executed by the data transfer command of the CPU unit 1 (step 213). Also, there bit offset in step 208 (calculating Ah
The If set as a data transfer Ri), by referring to the contents of the source bit offset register 8, C
The data transfer instruction of the PU unit 1, transfer processing of bits deducting offset of one byte in the leading data is performed (step 209), after which the processing DMA
Returning to the control circuit 11, the DMA processing circuit 11 DMA-transfers data of the number of bytes / words excluding the offset from the predetermined data length set in the bit length setting register 7 (step 210). ). At this time, in the last 1-byte / word transfer, unnecessary bits are discarded as in the case of the start of transfer (step 211).

If it is determined in step 205 that an operation is required, the processing contents held in the processing selection register 10 are further referred to. As shown in FIGS. 3A and 3B, the configuration of the processing selection register 10 is such that
Each channel (in this embodiment, four channels are assumed) is formed by the bit structure 302,
Each of the three types of processing contents can be selected. When the execution of the predetermined arithmetic processing is designated in the processing selection register 10, the contents of the arithmetic selection register 6 are referred to in addition to the bit string transfer processing (step 206). Is instructed to execute a logical operation to the arithmetic processing circuit 3 included in the CPU unit 1. In response, the arithmetic processing circuit 3 included in the CPU 1
Bit string processing is executed (step 20).
7). Note that an example of the configuration of the operation selection register 10 is shown in FIG.
This is shown as a register configuration 303 in FIG.

Next, a second embodiment of the present invention will be described. FIG. 4 is a block diagram showing the second embodiment. As shown in FIG. 4, the present embodiment employs an external bus 10
6. CPU unit 1 including bit string processing register group (general purpose register) 2 and arithmetic processing circuit 3 corresponding to internal buses 107 and 108, bit string control circuit 5, processing selection register 10, and DMA control circuit 11 and a bus interface /
A bus arbiter 16, and the bit string control circuit 5 includes an operation selection register 6,
The DMA control circuit 11 is formed by a bit length setting register 7, a transfer source bit offset register 8, a transfer destination bit offset register 9, and an arithmetic processing circuit 17.
As in the case of the first embodiment, a transfer source address register 12, a transfer destination address register 13, a count register 14, and a mode register 15 are formed.
FIG. 5 is a flowchart showing a processing procedure when a DMA request signal is input from the outside in this embodiment.

As is clear from the comparison between FIG. 4 and FIG. 1, the difference between the first embodiment and the first embodiment is that the bit string control circuit 5 included in the DMA control unit 4 in the present embodiment. And that an arithmetic processing circuit 17 is newly added. By the addition of the arithmetic processing circuit 17, in the first embodiment described above, the processing control operations such as the arithmetic processing and the bit string processing performed in the arithmetic processing circuit 3 included in the CPU unit 1 are reduced. This is performed only in the circuit 17. As a result, FIG.
5 is different from the flowchart in the first embodiment shown in FIG.
In step 507, step 506
, A bit string process is executed in the arithmetic processing circuit 17 included in the DMA control unit 4. The processing procedure other than step 507 is the same as the flowchart of the first embodiment in FIG. The second embodiment has an advantage that the bit string function can be realized regardless of whether the bit string function is supported inside the CPU 1.

[0015]

As described above, the present invention is applied to a DMA controller for controlling data transfer between memory devices in an information processing system, and provides a bit string transfer function conventionally realized by software. This can be realized by the control unit itself included in the DMA control device instead of the software, and thereby, in various image processing systems and data processing systems, it is possible to realize asynchronous processing by hardware, There is an effect that the data transfer performance can be improved by reducing the CPU intervention time.

Further, in the second embodiment, C
There is an effect that the bit string function can be realized regardless of whether the bit string function in the PU is supported.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a first embodiment of the present invention.

FIG. 2 is a diagram illustrating a flowchart of a processing procedure in the first embodiment.

FIG. 3 is a diagram showing a configuration of a process selection register and an operation selection register included in the embodiment.

FIG. 4 is a block diagram showing a second embodiment of the present invention.

FIG. 5 is a diagram illustrating a flowchart of a processing procedure in the second embodiment.

FIG. 6 is a block diagram showing a conventional example.

FIG. 7 is a diagram showing a transfer data format.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 CPU part 2 Bit string processing register group (general purpose register) 3, 17 Operation processing circuit 4 DMA control part 5 Bit string control circuit 6 Operation selection register 7 Bit length setting register 8 Source bit offset register 9 Destination bit offset register 10 Processing Selection Register 11 DMA Control Circuit 12 Source Address Register 13 Destination Address Register 14 Count Register 15 Mode Register 16 Bus Interface / Arbiter 101 DMA Request Signal 102 DMA Permit Signal 103 Hold Request Signal 104 Hold Permit Signal 105 DMA Permit Signal 106 External bus 107, 108 Internal bus 201-213, 501-513 Step 301, 303 Register configuration 302 Bit configuration 701, 703, 707 Source memory data 702, 705, 709 Destination memory data 704, 708 Source bit offset 706, 710 Destination bit offset

Claims (3)

(57) [Claims] A bus interface / arbiter for inputting a DMA request signal from outside and arbitrating a right to use a bus with another bus master including another DMA channel and another CPU unit; and the bus interface / bus arbiter A DMA control unit that receives a DMA request signal output from the controller and performs a DMA transfer according to a specified predetermined method. Through a calculation instruction output from the DMA control unit, data of an arbitrary bit length is transmitted. A CPU unit having a bit string function of performing data transfer between a transfer source memory and a transfer destination memory in accordance with a data transfer instruction of the CPU unit.
Control device. 2. When the DMA control unit performs a DMA transfer by inputting a DMA request signal output from the bus interface / bus arbiter, the DMA transfer data length of the corresponding channel is not a byte / word unit but a fraction bit. In the case where the error occurs, a bit string control circuit for executing a normal DMA transfer process after temporarily taking the data into the DMA control device and performing the transfer of the fraction bits is further provided. 2. The DMA control device according to 1. 3. When the DMA controller inputs a DMA request signal output from the bus interface / arbiter and performs a DMA transfer, the DMA transfer data length of the corresponding channel is not a byte / word unit but a fraction bit. Is generated, the data is once taken into the DMA controller, the fractional bits are transferred, and then a bit string control circuit for executing a normal DMA transfer process is additionally provided. within, the transfer source memory
The logical operation according to a bit string functions performed between the data of the internal data of the transfer destination memory, characterized in that it comprises at least an arithmetic processing circuit that executes on behalf of the CPU unit according to claim 1 DM described
A control device.