JPH11212900A - System controller - Google Patents

Abstract

PROBLEM TO BE SOLVED: To simplify the control of response sequence of command packets in the same group, to attain the simultaneous processing of the command packets and to fetch the commands as much as possible without increasing the hardware in order to attain the high performance of a system controller by securing the response to be returned from an internal controller by means of a queue identification number. SOLUTION: A received command packet is held in a command queue 10a-1, and the next command packet is held in a command queue 10a-2. Then a group (n) internal processing request signal generation circuit 11 starts to supply a group (n) internal processing request signal to an internal controller 2. At the same time, a group n QID generation part 10b outputs a QID to the controller 2 as a QID signal 11b. The controller 2 supplies a group internal processing reception signal 2a to the circuit 11 and also to a group n QID updating part 10c against the received request. Thus, the QID is updated.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a system controller for performing overall control of a computer system for performing memory access, register access, IO access, and the like by a command packet issued from a processor (or channel).

2. Description of the Related Art In recent years, with the increase in speed and size of computers, improvements in CPU performance, multiprocessors, and the like have been demanded. However, a system control device that processes commands issued from CPUs and channels has many commands. High-speed processing is desired.

[0003]

2. Description of the Related Art FIG. 22 is an explanatory view of a conventional example. In the figure,
Reference numeral 80 denotes a CPU. In this example, two CPUs (CPU 0, CP
81, a system controller, 82, a command queue for temporarily storing commands from each CPU, 83, a bus, 84, an internal controller, 8
5 is a memory and 86 is a channel control device. It should be noted that another IO device (not shown) and the like are connected to the channel control device 86 via another bus.

Conventionally, when the CPU 80 accesses the memory 85, the channel controller 86, and the like, each CP
Command (or command packet) from U80
Is issued, it is set in the command queue 82 provided corresponding to the CPU in the system controller 81. The contents of the command queue 82 were sequentially processed by the internal controller 84. In this conventional example, the CPU
Only the configuration when the command is issued from is shown,
In fact, a command is also issued from the channel controller,
A command queue for that purpose is provided, but is not shown.

[0005]

In the above-mentioned conventional system control device, the CP has been increased with the recent increase in the size of computers.
If the number of U and channel control devices increases and the number of command packets issued from them increases, to process all command packets at once, a circuit configuration for processing command packets in the system control device is required. Although it is necessary to provide a plurality of devices and drive them simultaneously, there is a problem that the amount of hardware increases drastically.

According to the present invention, when a processor or a channel accesses another device such as a memory, a command packet is sent to a bus connected to the system controller, and a response is received from the system controller via the bus. It is an object of the present invention to provide a system control device which can access the memory as fast as possible by taking in as many commands as possible without increasing hardware and realizing high performance.

[0007]

FIG. 1 is a diagram showing a first principle configuration of the present invention, in which 1 is a system controller,
Reference numeral 10 denotes a command queue corresponding to a command group that needs to maintain the order in accordance with the type of command (a group of commands of the same type that need to be processed in order, for example, a command that performs a memory read is the same group). . In this example, a group n command queue unit for group n is shown. 10a represents an individual command queue;
a-1 and 10a-2 are a plurality of command queues.
10b is a group n queue identification number (QID) generator,
10c is a group n QID update unit, 11 is a group n
The internal request signal generation circuit 2 is an internal controller.

In the first principle configuration, a plurality of command groups are provided in the system control device 1 according to the types of commands. For example, a memory cache access command for accessing a memory and a command for a non-memory cache are grouped separately. The command packet corresponding to this group sent from the CPU (processor) or channel via the bus is held in the first command queue 10a-1, and the next command packet is held in the command queue 10a-2. When the command queue is held, the group n internal request signal generation circuit 11
Is activated, a group n internal processing request signal is supplied to the internal controller 2, and at the same time, the group nQ
A QID (initially “0”) is generated from the ID generation unit 10b and output to the internal controller 2 as a QID signal 11b.

The internal controller 2 responds to a request from the command queue by receiving a group internal processing acceptance signal (ACK).
Signal) 2a to the group n internal request signal generation circuit 11, and at the same time, this signal is
c is also supplied to the group queue identification number generator 10b.
Is updated (QID becomes "1"). This updated QID is prepared for the next group n command packet. Thus, upon receiving the next command packet, it supplies the same to the internal controller 2 and sends the updated QID in the same manner as the previous command. CPU
The command packet issued from the (processor) is Q
Since the order of ID = 0 to QID = 1, the internal controller 2 may generate the group n response signal 2b to the processor in consideration of the order of the QID. Thus, by receiving and processing each command packet, the command packets can be processed substantially simultaneously.

FIG. 2 shows a second principle configuration of the present invention. In FIG. 2, reference numerals 1 and 2 denote a system controller and an internal controller, respectively, as in FIG. Reference numeral 10 in the system control device 1 denotes a group n command queue unit in which a command queue corresponding to the command group of group n is stored. 10a-1 and 10a-2 are two command queues of group n, and 10d-1 and 10d-2 are command queue valid flags which are means for displaying the validity of each group n command queue 10a-1 and 10a-2. is there. Reference numeral 11 denotes a group n internal request signal generation circuit.
When the command packet is held in the command queue 10a-1, the group n internal request signal generation circuit 11 generates a group n internal processing request signal (request) 11a,
The internal controller 2 starts processing the command packet. When the internal controller 2 returns a response (reply) to the command packet issuing source by the group n internal processing acceptance signal 2a, the internal controller 2
A group n response completion (END) signal 2d is sent. In response to the response completion (END) signal 2d, the command queue invalidates the command packet held up to that time and can receive a new command packet. This enables the next command to be input to the processor as soon as possible.

However, when the command reads data from the memory element, for example, the internal controller 2 sets the same memory as the end of the memory element for several ns after sending out the read data by using the next command queue for a fixed time. Group n internal request signal suppression instruction signal (FL signal)
2c is sent to the group n command queue 10. If the next access is another address or memory element, it is not inhibited. By such control, a response can be returned earlier to the command packet issuing source.

FIG. 3 shows a third principle configuration of the present invention, in which 1, 2, 10, 10a-1 and 10-2 correspond to those shown in FIG.
Similarly to 2, 1 is a system control device, 2 is an internal controller, 10a is a group n command queue unit, and 10a-
1, 10a-2 are command queues of group n.
Reference numeral 12 denotes a command conversion unit (denoted by DEC).

In the third principle configuration, when the system controller 1 receives a command packet from a channel,
The command converter 12 decodes the command packet and decodes the address portion of the command packet to check whether the access is valid. Specifically, when a non-cache command (a command for accessing the register space) that is not a cache command (such as a read command from a memory to a cache) specifying a memory area is identified, the address of the command is determined. Detects that the command specifies an address in the memory area, an error response is generated from the group n command queue unit 10 because the command is obviously an error.

At this time, the command is converted into a non-cache block read which is not issued from the channel and stored in the group n command queue 10. In the group n command queue 10, it is suppressed that a processing request is not issued to the internal controller 2 in the case of a command that cannot be actually performed. Thus, hardware can be reduced by eliminating unnecessary processing in the internal controller 2 in advance.

FIG. 4 shows a fourth principle configuration of the present invention, in which 1, 2, 10, 10a-1 and 10a-2 are the same as those in FIG.
3 to 3 and the description is omitted. 11 is a group n internal request signal generation circuit, and 13 is a mask (MSK) circuit.

In the fourth principle configuration, the number of commands that can be processed simultaneously by the internal controller 2 (corresponding to the number of hardware that performs processing of the internal controller 2)
When the number is p, the processing request signal 11a to the internal controller 2 generated from the group n command queue signal generation circuit 11 from the group n command queue unit 10 is transmitted from the internal controller 2 to the group. When the internal controller 2 receives an n internal processing reception signal 2a and receives two commands in order, the group n internal request signal generation circuit 11 sends an MSK set instruction signal to the mask circuit 13 when p groups are received. Is generated, and the mask circuit 13 is set.

The set output of the mask circuit 13 is supplied to the group n internal request signal generation circuit 11 as an internal processing request suppression signal 13a. Thereafter, when the processing of one command is completed in the internal controller 2, a mask (MSK) release instruction signal 2e is generated and a group n response completion signal (END) 2d is generated. The mask (MSK) circuit 13 is thereby reset, stops the internal processing request suppression signal 13a, and generates a group n internal processing request 11a corresponding to the next command queue.

FIG. 5 shows a fifth principle configuration of the present invention. In FIG. 5, 1, 2, 10, 10a-1 and 10-2 are the same as those in FIGS. 10-m represents a group m command queue section, and 10a-1m, 10a
-2m represents each queue in the group m command queue unit 10-m. 11-m is a group m internal request signal generation circuit, 14 is a switching control circuit, 15 is a switching internal request signal generation circuit, and 16 is a logical sum circuit.

The internal controller 2 has a processing circuit corresponding to each command group, but among the commands set as the group n, those which perform the same operation as the group m are included. Since it is useless to provide a circuit similar to the group m in the n processing circuits, when such a command is detected in the group n, the command is switched to the group m and supplied to the internal controller 2. To control.

As a result of the identification of the group n command queue unit 10, when it is detected that the command queue is a command for switching to the group m, a switching command detection signal 10 f is output to the switching control circuit 14. The switching control circuit 14 thereby obtains the group n
A suppression signal is generated to the internal request signal generation circuit to suppress the generation of a request signal corresponding to a command from the group n command queue unit. Further, the switching control circuit 14 generates a signal for controlling the switching internal request signal generating circuit 15, and generates a switching internal request signal 15a from the group n to the group m. At this time, the switching internal request signal generating circuit 15 generates a signal 15b for suppressing the group m internal request signal generating circuit 11-m. Therefore, the switching internal request signal 15a is supplied to the internal controller 2 through the OR circuit 16. The internal controller 2 outputs a group m internal processing acceptance signal 2a-m in response to the signal and supplies it to the switching internal request signal generation circuit 15.
When the processing of the replacement command is completed, the group m
The processing completion 2dm is supplied to both the group n command queue unit 10 and the group m command queue unit 10-m.

FIG. 6 shows a sixth principle configuration of the present invention, in which 1, 2, 10, 10a-1, 10a-2, 10-
The reference numerals m, 10a-1m, 10a-2m, 11, and 11-m are the same as the reference numerals in FIG.
Reference numeral 17 denotes a resource management mask circuit.

In the sixth principle configuration, when the internal controller 2 uses a limited number of resources common to the command of the command queue of the group m and the command of the command queue of the group n, This suppresses the generation of command queue request signals (internal request signals) for groups m and n so that the number does not exceed a certain amount.

That is, when resources commonly used by the two groups m and n are limited, for example, the group n
May be provided with only two read data buffers when sending read data to the CPU when the group m is non-cacheable read.

In this case, detection signals 10g and 10g-m generated when a command using a common resource is detected from the group n command queue unit 10 and the group m command queue 10-m are transmitted to the resource management mask circuit 17. When input, the resource management mask circuit 17 is set,
Internal request signal generation circuits 11, 11- of each group n, m
m, and outputs the suppression signals 17a and 17b. Thus, the supply of the command queue using the common resource to the internal controller 2 is suppressed. Thereafter, when a response completion (END) 2d indicating the completion of the processing of the command using the common resource is generated from the internal controller 2, the command is supplied to the group n command queue unit 10 and the group m command queue unit 10-m and the resource is It is supplied to the management mask circuit 17. As a result, the resource management mask circuit 17 is reset, and the two inhibition signals 17a and 17b
Is released, and a new command using the common resource can be accepted.

FIG. 7 shows a seventh principle configuration of the present invention. In the figure, 1, 2, 10, 10a-1, 10a-2, 1
0-m, 10a-1m, 10a-2m, 11, 11-m
Are the same as those in FIG. 5 and their description is omitted. Reference numeral 18 denotes a pair control flag for guaranteeing that write back is performed after reading from the cache, and performs control to prohibit the next read without performing write back.

When the processor issues a read access with write-back for cache line replacement (replacement) to the group n and is held in the group n command queue unit 10, the pair control flag 18 A processing request signal 11a is generated from the group n internal request signal generation circuit 11, which is
To generate the group n internal processing reception signal 2a. In response to this signal 2a, the group n internal request signal generation circuit 11 causes the pair control flag set instruction signal 1
1h is generated, whereby the pair control flag 18 is set (= "1"). This signal is supplied to the group m internal request signal generation circuit 11-m as a group m command internal request suppression signal 18a.

When the pair control flag is "0" (reset state), the group m internal request signal generation circuit 11-m
Suppresses internal processing requests for write-back commands,
When the pair control flag is "1", the output of the write-back command internal processing request 11-ma is permitted, and the internal processing request is received and the group m internal processing reception signal 2
When a-m occurs, the group-m internal request signal generation circuit 11-m generates a reset instruction signal 11i for the pair control flag 18. As a result, the pair control flag 18
Is reset, and a read access accompanied by the next write-back can be accepted.

As a result, the order of the read command accompanied by write-back for making an internal processing request and the write-back command is maintained, so that the tag (TA
G), a replacement tag (T) necessary for replacing the dual tag (DTAG) which is a copy of the cache line.
AG) is sufficient, and an increase in hardware can be prevented.

[0029]

FIG. 8 shows the configuration of an embodiment of a system control device. This embodiment shows an example in which two processors are connected to a system controller, and other channel controllers, memory devices, and the like are not shown. In the figure,
3-0 and 3-1 represent processor 0 and processor 1, respectively.
Reference numerals 1, 2, 10, and 11 correspond to the same reference numerals in FIGS. 1 to 7, 1 is a system control device, 2 is an internal controller, 10-0 is a processor 0 command queue unit, 1
Reference numeral 0-1 denotes a processor 1 command queue unit, and 10 provided in each processor command queue unit 10-0 and 10-1.
a-0 to 10a-2 are request signal generation circuits corresponding to the commands of the respective groups 0 of the processors 0 and 1;
Reference numeral a-3 denotes a request signal generation circuit corresponding to the command of the group 1 of each of the processors 0 and 1. 11-0,
11-1 is a request generation circuit of each processor command queue unit (the internal request signal generation circuit 11, FIG.
11-0m), 13-0 and 13-1 are various mask circuits of each processor command queue unit (the mask circuit 13 in FIG. 4 described above, the replacement internal request signal generation circuit 15 in FIG.
(Including a resource management mask circuit 17 in FIG. 6 and a pair control flag 18 in FIG. 7). 19 is a selection circuit. In addition,
In this embodiment, the internal request signal generation circuits (11, 11-m) provided outside the command queue units 10, 10-m in the principle configuration shown in FIGS. 1 to 7 are replaced with the request generation circuits 11-0, 11-m. Although it is provided internally as -1,
It is optional to provide them.

In the internal controller 2, reference numeral 20 denotes a process reception circuit, and reference numeral 21 denotes a copy (DTAG) of a tag (TAG) in a cache memory of a write-back CPU and a tag having an address of a write-back command when rewriting a cache line. Tag copy control unit of secondary cache for performing coherent control
Reference numerals 0 to 22-4 denote a plurality of detailed controllers for processing the received commands, 22-0 and 22-1 process group 0 commands from the processor 0, and 22-2 denote both the processor 0 and the processor 1. 22-3 and 22-4 process the group 0 command of the processor 1.

FIG. 9 shows the format and address space of a command packet in this embodiment. The command packet is A. 32 bits from 0 to 31 bits represent an address, 32 bits represent the presence or absence of replacement (replacement), and 33 bits represent a group (group 0).
Or group 1), and 34 to 37 bits indicate a command type.

The address space is a hexadecimal 8-digit display address from "00000000" to "7FFFFFFFF".
Is the cacheable space (memory space) and "80
The range from “000000” to “FFFFFFFF” is a non-cacheable space (register space).

The command packets can be divided into the following groups 0 and 1. Group 0 command CR: Coherent read (read from memory to cache or cache to cache) NCBR: Non-cacheable block read (read from non-cache area) Group 1 command NCSR: Non-cacheable single Read (read of single data to register space) NCSW: Non-cacheable single write NCBR: Non-cacheable block read WB: Write back (when rewriting cache contents, write cache contents back to memory) Command) The access control device of this embodiment has the following functions (1) to (3) and has a configuration (to be described later) for that.

(1) Control is performed to prohibit cacheable access to the non-cacheable space and non-cacheable access to the cacheable space (memory space).

(2) At the time of access involving a change (replacement) of a line in the cache memory, the replace bit of the read command is set to "1", and a write-back command for replacement is issued following the read command.

(3) The number of commands in group 0 issued from the processor (without waiting for a response) is up to 3 commands, and the number of commands in group 1 is up to 1 command. (4) The maximum number of commands in group 0 issued from a channel (without waiting for a response) is 1 command.
The maximum number of commands is one.

FIGS. 10 to 13 show the configurations (1) to (4) of the respective circuits constituting the processor 0 command queue unit.
It is. FIG. 10A shows a group 0 command queue, and A to C denote three group 0 command queues 10a # 0 of the processor 0 command queue unit 10 # 0 of FIG.
10 to 10a─2. In the example of A, a signal indicating that the pointer of the next command queue of the group 0 (represented by NXTPP0) is “00”,
When the COMV signal issued from the processor and indicating that a command packet is present on the bus and the 33 bits of the command (see A in FIG. 9) are "0" (indicating that the command packet belongs to group 0), the AND (Indicated by AND) generates an enable signal to drive a 38-bit D-type flip-flop circuit (indicated by FF). Thus, 0
Command packet (COMP0.
IN <37: 0>) is a D-type flip-flop circuit (F
F) is set and held. In the case of B and C in (1), the pointer of the next command queue is set to “0”.
In the case of "1" or "10", each command is set.

FIG. 10 (2) shows the bus arbitration of the group 0 command queue. The signal (indicated by ARBP) of the bus arbitration (arbitration) pointer (ARBP) is selected from the three group 0 command queues shown in the above (1). ARBP
One of the corresponding command queues is selected by the selection circuit (indicated by SEL) based on “00”, “01”, or “10”) and output to the request generation circuit 11 # 0.

FIG. 10C shows a group 1 command queue (10 of the processor 0 command queue unit 10 # 0 of FIG. 8).
a─3) is shown. In this case, a COMV signal indicating that a command packet is present on the bus and a command 3
Three bits (see A in FIG. 9) are "1" (group 1).
Is an AND circuit (AND)
, A command packet is set in a 38-bit D-type flip-flop circuit (FF).

Next, (4) of FIG. 11 shows a command queue valid circuit of group 0, and A to C denote the 10d of FIG.
This is a configuration corresponding to {0 to 10d} 2. In the example of A, a COMV signal indicating that there is a command packet on the bus, a signal indicating that 33 bits of the command packet indicating that the command is a group 0 command is "0", a pointer of the next command queue Is "00", "1" is output from the AND circuit (AND1), stored in the D-type flip-flop (FF), and outputs that the command queue 0 of group 0 is valid.
This signal is fed back to the AND circuit (AND2), and the signal (END. POGOQ0) indicating the completion of the response to the command packet
Is reset to “0” when the error occurs. (5) represents a group 1 command queue valid circuit, which is shown in FIG.
This is a configuration corresponding to 0d─3. This circuit also performs the same operation as the above (4).

Processor 1 command queue unit 10 of FIG.
# 1 is also provided with each circuit having the same configuration as in FIGS. 10 and 11, but is not shown. (6) in FIG. 12 is a next command queue pointer (NXTPPO), in which a D-type flip-flop (indicated by FF) is set to “00” for the first command, and a command packet is generated on the bus. When "1" is output from COMV0, the output of the +1 adder (indicated by ADD) that performs +1 on the output of flip-flop circuit FF is selected in the selection unit (indicated by SEL), and is output to flip-flop circuit FF. “01” is set. Similarly, when the next command occurs, “1”
0 ”and“ 00 ”are updated.

FIG. 12 (7) shows an arbitration pointer (represented by ARBPO) having the same configuration as the above-mentioned next command queue pointer. However, in this circuit, +
The selection of the addition output by the 1 adder (ADD) is performed by generating an internal processing request acceptance signal (ACK.POGO) of the group 0 command from the internal controller 2.

FIG. 12 (8) shows a command queue identification number (QID) circuit, which is a configuration for realizing the first principle of the present invention. A in (8) is the QID of group 0
This circuit generates a pointer (QIDP0), and receives an internal processing request acceptance signal (ACK.POGO) for the group 0 command.
Signal, a D-type flip-flop circuit (F
An exclusive OR with the output of F1 is calculated, and if they do not match, "1" is generated, and if they match, "0" is generated. As a result, the queue identification numbers (QIDs) are generated in order. B. Outputs a queue identification number (QID) to the internal controller 2 and then outputs a response completion signal (RPYOK)
Is sent, the flip-flop circuit (F
F2) is updated, and a queue identification number pointer response signal (QIDP0.RPY) is generated as an output.

FIG. 12 (9) is a group 0 command queue request holding circuit, which is incorporated in the request generation circuit 11 # 0 of FIG. A to C in (9) indicate that the command requests (CQRQPOGOQO HOLD2) corresponding to the command queues of the group 0 generated in order are each flip-flop FF in which the condition of the control signal of each AND circuit (AND1, AND2) is satisfied. Is set and held, and the command packet 37 bits to 34 bits (P0G0Q0
<37:34> = NCBRD) is output when "0".

FIG. 13 (10) is a group 0 command queue request selection circuit, which is built in the request generation circuit 11 # 0 of FIG. In this circuit, three AND circuits (AND1 to AND3) output from one of the outputs of the command queue request holding circuits shown in the above (9) designated by the bus arbitration pointer and pass through the OR circuit OR2. AND circuit (AND4)
Supplied to The AND circuit (AND4) outputs “1” from any of various signals input to the OR circuit (OR1).
If does not occur, the selected command queue request is output.

(11) is a group 1 command queue request holding circuit, and the request generation circuit 11 shown in FIG.
Built in $ 0. Since only one command queue is stored in group 1 at most, the configuration is simplified compared to the case of the above (10). A signal indicating that the command is valid (C
OMV0) is “1” and “1” is output from the AND circuit (AND1).
Is generated, "1" is set and held in the D-type flip-flop (FF). This output is a command queue / request signal when the other three mask conditions are all “1” in the AND circuit (AND3).
(CQRQP0G1) is output. The three conditions are that the mask signal (CQRQP0G1.MSK) of the command queue request processor 0 group 1 is not generated and that the processor 0
Non-cacheable read command signal (NCRD.O
K0, P0) or the non-cacheable read command hold signal (NCRDHLD.P0) from processor 0 is not generated, and the group 1 of the command queue request processor 0 is TTB (pair control). Is a valid command. When a reception signal (ACK.P0G0) is returned from the internal controller 2, the flip-flop circuit (FF) operates as an AND circuit (AND1).
Is output from the device and the command queue request is reset by setting this "0".

Each of the circuits (6) to (1) shown in FIGS.
Although 1) is provided in the processor 0 command queue unit 10 # 0, it is also provided in the processor 1 command queue unit 10 # 1 (see FIG. 8).

FIG. 14 shows a configuration of a command signal selection circuit including switching control. Four command signals (38 bits) of (1) to (4) are input to the selection circuit (indicated by SEL), and each of them is selected by the corresponding control signal a to d, and the command signal of group 1 is selected. (P01G1 <37: 0
>) Is output. Processor 0 of (1) or (2)
And the command signal of each group 1 corresponding to the processor 1 is selected when the mask signal indicated by a or b is not generated. Command signals of group 0 corresponding to processors 0 and 1 in (3) and (4) are c and d, respectively.
Non-cache block read command (NCBRD.
EXE.P0 and NCBRD.EXE.P0) are selected, and the command to switch to group 1 (P01
G1 <37: 0>) is output. This switching between command groups is a configuration corresponding to the fifth principle of the present invention shown in FIG.

FIG. 15 shows the configuration of a mask circuit for exclusive control of group 1 of processor 0 and group 1 of processor 1. This circuit is similar to the mask circuit (13 in FIG. 4) for exclusive control between group 0 and group 1 in the same processor.

Two D-type flip-flop circuits (FF)
1, FF2), the mask signal (CQRQP1G) of the group 1 of the command queue request processor 1
1.MSK) and command queue request processor 0
When the group 1 mask signal (CQRQP0G1.MSK) is generated, the request signal of the group 1 of the processor 1 is suppressed, and the request signal of the group 1 of the processor 0 is suppressed. These two mask signals are input to an AND NOT circuit (AND · NOT), and when both detect a state of “1”, they generate “0”, and one of them is “0”.
At the time of "1" is generated. The AND circuit (AND1) detects that 33 bits (group number) of the command are "1" (representing group 1). OR circuit (OR
4), a mask 1 set signal (MASK1.SET) is input, which is a signal generated when the signal of group 0 is switched to group 1. As a result, the flip-flop circuit (FF1) is set, and a mask signal (CQRQP1G1.MSK) for group 1 is generated.
In this case, a command request from the original group 1 is prevented from being input, and a double input with a command input from the group 0 is prevented by switching.

FIGS. 16 to 18 show configurations (part 1) to (part 3) for resource management. FIG. 16A shows “00” and “0” represented by the bus arbiter pointer of the processor 0.
A response (ARBPP0.EQ.RPL0) indicating that the command queue provided for each value of "1" and "10" is invalid (empty) is output, and (2) indicates that the bus arbiter pointer is A response (ARBPP) indicating that the command queue one before the indicated value is invalid (empty).
0.M1.RPL0) is output. (3) and (4) are signals corresponding to (1) and (2) for the processor 1.

(1) and (2) in FIG. 17 are non-cacheable
This is a configuration for controlling whether a single read (NCSR) command can be executed immediately or temporarily held and executed later, and corresponds to the processors 0 and 1. (1)
In the following, the command NC is represented by bits 37 to 34 (command type) of the command (38 bits).
When SR is input and valid (valid), "1" is generated from the AND circuit (AND1), and (1) in FIG.
When both output signals of (2) are "1", the AND circuit (AN
D2) generates "1", and the AND circuit (AND3) generates an output signal (NCRD.OK.SE1 <P0>) for executing this command as it is (without temporarily holding it). In FIG.
If the output signals of (1) and (2) are not both "1", the two flip-flop circuits (F
F1 and FF2) are set to "01" or "10", and signals (NCRDHLD.P0 <0> and P0 <1>) holding this command (NCRD) are generated as 2-bit signals.

FIG. 18 shows a circuit for controlling the execution of the NCRD command held. When the two holding signals NCRDHLD.P0 <0> and P0 <1> generated from (1) in FIG. 17 are "10", "1" is generated from the AND circuit (AND1), and the next AND circuit (AND1) is generated. AND3), and in FIG.
Signal from (1) (Signal indicating that the command queue with the number of the bus arbiter pointer value # 1 has become empty)
Generates "1". Also, the two holding signals NCRDHLD.P0 <0> and P0 <1> generated from (1) in FIG.
In the case of "1", "1" is generated from the AND circuit (AND3), and the next AND circuit (AND4) causes the above (2) in FIG.
(A signal indicating that the command queue having the same number as the bus arbiter pointer is empty) generates "1". When "1" is set in the flip-flop circuit (FF) by satisfying other conditions in the AND circuit (AND5), a non-cacheable read signal (NCRD.OK <P0>) of the processor 0 is generated. From (2), the non-cacheable read signal of processor 1 (NCRD.OK)
<P1>) occurs. Next, FIGS. 19 and 20 are views showing configurations (Part 1) and (Part 2) for performing group switching, and include a configuration for realizing the fifth principle of the present invention. In FIG. 19, two sets of OR circuits (OR1 to OR1)
OR3) receives a signal group a and a signal group b, and outputs three AND circuits (AND4 to AND6).
, Each value of the arbiter pointer (00, 01, 1
0), the type of the command held in each command queue at that time is the non-cacheable block read (NCBRD), and the AND circuit (AND1)
... AND3) (representing that the command of the number preceding the respective command queue is empty) becomes “1”, the OR circuit (OR4) outputs “1”.
Is generated in the AND circuit (AND7) on condition that the non-cache read (NCRD) is "0" (invalid), and the AND circuit (AND8, AND8) shown in FIG.
In 9), when the non-cacheable block read (NCBRD) occurs simultaneously from the processor 0 and the processor 1, which one is given priority is selected. The selected signal is held in one of the flip-flop circuits (FF1, FF2) and is held in a non-cacheable block read (NC
BRD.RQ0.HLD or NCBRD.RQ1.HLD) signal is generated.

The signal group c in FIG. 19 detects a state in which the mask signal of the group 1 of the command queue request processor 0 and the mask signal of the group 1 of the command queue request processor 1 are generated at the same time. A group switching signal (NCBRD.EXE.P01) is generated on the route. Also, a number of logic circuits (combination of AND circuit and OR circuit) to which the signal group d is input determine whether a command of group 1 is being executed and detect a break. When a break in group 1 is detected, a switch from group 0 to group 1 is performed, so that a break detection signal is supplied to FIG. 20 via, and an NCBRDOK signal is generated. Further, the two flip-flop circuits (FF1, F1
Each non-cacheable block read from F2)
Request holding signals (NCBRD.RQ0.HLD and NCBRD.RQ1.HL)
When D) becomes “1”, processor 0 and processor 1
If the mask signal of group 1 of the command queue request of “1” is “1”, the switching judgment signal (NCBRD.EXE.P0
And generate NCBRD.EXE.P1). This signal is used in the selection circuit of FIG.

FIG. 21 shows a circuit for pair control. In the figure, an AND circuit (AND1) indicates that a valid command of the group 0 of the processor 0 is represented by a pair control read (coherent read: CR) shown in the seventh principle configuration of the present invention (see FIG. 7). )) When the type is “1”
Is output. This "1" output is a flip-flop (F
F), and this set output (TTB
<P0>) corresponds to the pair control flag 18 in FIG.
The reset signal of the flip-flop (FF) is generated from the AND circuit (AND3), the command of the group 1 of the processor 0 is write-back (indicated by WB), and the command queue request of the group 1 of the processor 0 is Occurs when not masked.

The AND circuit (AND4) shown in FIG.
When the flip-flop circuit (FF) is set (when TTB <P0> is “1”), when a command of group 1 (new coherent read command) is generated, this is masked ( Suppress) signal (CQ
RQPOG0.MSK.TTB) occurs. Furthermore, an AND circuit (AN
D5) generates a signal (CQRQPOG1.VLD.TTB) that enables a write-back (WR) command to be processed internally when the flip-flop circuit (FF) is set.

[0057]

According to the first principle of the present invention, the response is returned from the internal controller using the queue identification number (QID), thereby simplifying the response order control of command packets in the same group. At the same time.

According to the second principle of the present invention, completion (EN
D) The validity (valid) of the command queue is released by the signal, the next command packet can be received, and a response can be made before the completion of the post-processing, so that the processing can be accelerated comprehensively.

According to the third principle of the present invention, when an undefined command packet indicating a nonexistent address space or the like is detected, an error response is immediately returned without activating the internal controller, thereby performing error processing. Can be simplified.

According to the fourth principle of the present invention, when the number of commands in the same group can be processed, the control of the system controller can be simplified by a mask circuit for suppressing a processing request of a new command queue. .

According to the fifth principle of the present invention, control of switching command packets of one group to another group can be efficiently realized. According to the sixth principle of the present invention, when the number of resources commonly used by a plurality of command groups is limited, it is possible to easily suppress the request of the command queue within the range of the number.

According to the seventh principle of the present invention, the order of a read command and a write-back command can be guaranteed, and a command that is out of the order can be prohibited with a simple configuration.

[Brief description of the drawings]

FIG. 1 is a diagram showing a first principle configuration of the present invention.

FIG. 2 is a diagram showing a second principle configuration of the present invention.

FIG. 3 is a diagram showing a third principle configuration of the present invention.

FIG. 4 is a diagram showing a fourth principle configuration of the present invention.

FIG. 5 is a diagram showing a fifth principle configuration of the present invention.

FIG. 6 is a diagram showing a sixth principle configuration of the present invention.

FIG. 7 is a diagram showing a seventh principle configuration of the present invention.

FIG. 8 is a diagram illustrating a configuration of an embodiment of a system control device.

FIG. 9 is a diagram showing a format and an address space of a command packet in this embodiment.

FIG. 10 is a diagram showing a configuration (part 1) of each circuit constituting a processor 0 command queue unit.

FIG. 11 is a diagram illustrating a configuration (part 2) of each circuit configuring a processor 0 command queue unit.

FIG. 12 is a diagram illustrating a configuration (part 3) of each circuit configuring a processor 0 command queue unit;

FIG. 13 is a diagram illustrating a configuration (part 4) of each circuit configuring the processor 0 command queue unit.

FIG. 14 is a diagram showing a configuration of a command signal selection circuit including switching control.

FIG. 15 is a diagram showing a configuration of a mask circuit for exclusive control of processor 0 group 1 and processor 1 group 1;

FIG. 16 is a diagram showing a configuration (part 1) for resource management.

FIG. 17 is a diagram illustrating a configuration (part 2) for resource management.

FIG. 18 is a diagram illustrating a configuration (part 3) for resource management.

FIG. 19 is a diagram showing a configuration (part 1) for performing group replacement.

FIG. 20 is a diagram illustrating a configuration (part 2) for performing group replacement.

FIG. 21 is a diagram showing a circuit for pair control.

FIG. 22 is an explanatory diagram of a conventional example.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 System controller 10 Group (n) command queue unit 10a Individual command queue 10b Group (n) Queue identification number (QID) generation unit 10c Group n QID update unit 11 Group n internal request signal generation circuit 2 Internal controller

Claims (5)

[Claims] An internal controller is connected to a processor and a channel control device via a bus, receives a command packet input from the device to the bus for accessing another device such as a memory, and performs processing by an internal controller. A command holding unit for holding a received command packet in the system control device, a circuit for generating a processing request signal to an internal controller of the system control device, and a command packet received when making a processing request to the internal controller And a circuit for generating a queue identification number every time and outputting the generated queue identification number to the internal controller and updating the queue identification number in response to a response from the internal controller. When it receives it, it processes it according to the order and responds. A system control device characterized by returning an answer. 2. The command queue unit according to claim 1, further comprising: a validity display unit that indicates that each command packet is valid for each of the held command queues.
The internal controller generates two kinds of signals, a signal indicating that the response to the command packet has been completed, and a signal indicating that there is post-processing for a certain time after the completion of the response.
The command queue unit cancels the validity of the command queue by the response completion signal, makes it possible to receive the next command packet, and the processing request signal generating circuit outputs the signal indicating that the post-processing is performed. A system control device for suppressing a next processing request. 3. The system control device according to claim 1, wherein the system control device decodes a command packet input to a command queue unit corresponding to the group, and when the system control device detects that the address is not adapted to the command packet, the command is transmitted to the command queue unit. A command conversion unit that converts a packet into a non-existent command; the command queue unit suppresses a processing request to an internal controller for a non-existent command and performs an error response to a command source; Characteristic system control device. 4. A mask circuit for performing control for suppressing a processing request to an internal controller is connected to a circuit for generating a processing request signal for an internal controller driven by a command queue section of the system control device. The processing request generation circuit sets the mask circuit when the number of commands that have started processing in response to the processing request to the internal controller reaches a predetermined number, and is reset by a release instruction from the internal controller. A system control device characterized by the above-mentioned. 5. The system control device according to claim 1, wherein the system control device performs coherent control to prevent another command from being issued between a read command for a new line of the cache and a write-back command when the line is changed. A control flag that is set when a processing request is received, and when the control flag is not set, the processing request of the write-back command is suppressed;
A system control device, wherein a request for processing a read command accompanied by a new write-back is suppressed unless the control flag is turned off.