JP2825589B2 - Bus control method - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a bus control method for a multiprocessor in which a plurality of processors and memories are connected by a plurality of buses.

[Conventional technology]

In a multiprocessor configuration in which a plurality of processors share a memory, exclusive control of data shared between the processors is necessary in order to execute processing without contradiction.

The exclusive control is for preventing another processor from using the shared data while a certain processor is using the shared data, and generally includes the following six processes. (See FIG. 2).

processing. Test & Set Instruction (T & S) Shared data has a lock byte that indicates whether the data is being processed by a processor.
If "1" is set in the lock byte of a certain shared data, it indicates that the shared data is being processed by the processor, and if "0", it indicates that the shared data is not being processed.

The test & set instruction is an instruction for checking whether or not the processor can use the shared data. (1) Lock byte read access, (2) determination whether the read lock byte is set, (3) Write access to the memory to set it to “1” when the lock byte is “0” (if it is “1”, another processor has already And (4) setting a condition code to notify the program whether the lock byte is "0" or "1". While the processor is executing the test & set instruction, in order to prevent access to the lock byte from other processors, the lock signal of the bus connecting the processor and the memory is turned on to occupy (lock) the bus. ) And prevent other processors from using the bus (reference: "Computer Architecture 2nd Edition", Yoichi Muraoka, Computer Science University Lecture 11, pp. 137-139, Modern Science).

processing. Judgment of availability of shared data Check condition code. If lock byte is "0", process. If lock byte is "1", process. Proceed to.

processing. Read shared data Reads shared data from memory.

processing. In-processor processing Processing of data read by the processor.

processing. Rewrite of shared data Write access for writing data processed by the processor to the memory (hereinafter referred to as ST1).

processing. Lock byte reset A memory write access (hereinafter referred to as ST2) for resetting (ie, "0") the lock byte of the shared data accessed by the processor.

By executing the processing in the above order, the processing using the shared data is performed without inconsistency among the plurality of processors.

As one method for improving the unit performance of a processor, there is a discrimination control in a write access to a memory.

In the control, when an instruction execution unit (hereinafter referred to as a CPU) executes a write access, a bus control unit stores the write address and data in an internal output buffer and sends the address and data to the CPU. At the point of receiving, the end of the write access is notified, and the execution of the next instruction is prompted, and the writing to the memory is performed in parallel with the execution of the subsequent instruction of the CPU. With this control, CP
U can execute the next instruction without having to wait for the end of writing to the memory every time a write access is performed, so that the processing performance is improved.

[Problems to be solved by the invention]

However, in the case of the conventional multiprocessor coupled by a plurality of buses, there is a problem that the exclusive control described above does not function well if the cutoff control is performed.

 Hereinafter, this problem will be described.

Here, in order to easily explain the above problem, a multiprocessor configuration in which two processors and one memory are connected by two buses having a function (lock signal) for locking the bus is described. Suppose. Each processor is composed of one CPU and two bus controllers corresponding to the buses, and the bus controller has an output buffer for squeeze control. Shared data at address 1 in memory, 0
It is assumed that the lock byte corresponding to the shared data is stored in the address, the value of the shared data is “A”, and the value of the lock byte is “0”. Further, it is assumed that access to the even address of the memory is performed via the bus 0 and access to the odd address is performed via the bus 1. FIG. 3 shows an overall view of a multiprocessor configuration assumed here.

In FIG. 3, 100 is a memory, and # 1 and # 2 are processors. The processor # 1 includes the bus control units 10 and 11 and the CPU 12
Consists of Processor # 2 is a bus control unit 2
0,21 and CPU22. The bus control unit 10 has an output buffer 10A, and the bus control unit 11 has an output buffer 11A. The bus control unit 20 has an output buffer 20A, and the bus control unit 21 has an output buffer 21A.

Next, the operation of each of the processors # 1 and # 2 in the multiprocessor configuration will be described.

The CPU 22 of the processor # 2 turns on the lock signal of the bus 0, executes the test & set instruction via the bus control unit 20 and the bus 0, and sets the lock byte at the address 0 on the memory 100 to “ Set to 1 ". The processor # 2 that has set the lock byte turns off the lock signal of the bus 0 and acquires an access right to the shared data at address 1 (the original data is assumed to be A).

The CPU 22 of the processor # 2 performs read access to the shared data at the address 1 on the memory 100 via the bus control unit 21 and the bus 1, and performs processing in the CPU 22.

Next, the CPU 22 of the processor # 2 writes the processed shared data (new data is assumed to be B) to an address 1 in the memory 100 (ST1), so that the write address and rewrite data (addresser is 1, data is B Is sent to the output buffer 21A of the bus control unit 21.

The bus control unit 21 stores ST1 in the output buffer 21A,
It notifies U22 of the end of the write access.

Subsequently, the CPU 22 of the processor # 2
To reset the lock byte at the address (ST2)
The write address and the data (the address is 0 and the data is 0) are sent to the bus control unit 20.

The bus control unit 20 stores ST2 in the output buffer 20A,
Notify 2 of the end of write access.

Next, the bus control unit 20 of the processor # 2 acquires the bus right of the bus 0, sends out the ST2 stored in the output buffer 20A to the memory 100 via the bus 0, and Resets the lock byte at address from “1” to “0”.
At this time, the bus 1 happens to be used by the processor # 1 or an unillustrated input / output channel, the bus control unit 21 cannot acquire the bus 1, and the ST1 is held in the output buffer of the bus control unit 21. Has been done.

This time, the CPU 12 of the processor # 1 turns on the lock signal of the bus 0, executes the test & set instruction via the bus control unit 10 and the bus 0, and executes the lock byte at the address 0 on the memory. To “1”. The processor # 1 that has set the lock byte turns off the lock signal of the bus 0 and acquires the access right to the sharing data at the address 1.

At this time, it is assumed that ST1 (address is 1 and data is B) in the output buffer of the bus control unit 21 of the processor # 2 is still on hold.

Next, the CPU 12 of the processor # 1 requests the bus control unit 11 for read access to the shared data at the address 1 on the memory 100.

The bus control unit 11 is a read access at address 1, a bus control unit.
Bus 21 is for write access to address 1 (ST1), so bus 1
And it is assumed that the bus control unit 11 is given a bus use right by the bus use right assignment circuit (not shown). The bus control unit 11 reads the old data (A) before ST1 is performed, and provides the old data (A) to the CPU 12 of the processor # 1.

After that, the processor # 1 continues the process using the old data before the rewriting, and a contradiction in the process occurs.

The above contradiction occurs in a multiprocessor including a plurality of buses and a processor that performs squeeze control. Therefore, as a configuration method of the conventional multiprocessor, a method of not providing an output buffer in the bus control unit and not performing the dropout control in the write access, or a method of using one bus has been adopted.

The former method is a method in which a write access (ST1) to a memory is executed on the memory and the next memory access (ST2) is not executed until the write access (ST1) is completed, thereby preventing a process inconsistency. However, as described in the first half of this item, there is a problem that the performance of the processor alone is not improved because the cutoff control is not performed.

In the latter method, the write access ST1 and ST2 to the memory are serialized by the bus by using one bus,
The above-mentioned problem does not occur because ST2 or ST1 is not overwritten in the memory. But with this method,
As the number of processors increases, there is a problem that bus contention increases and the processing performance is thereby saturated.

The present invention has been made to solve the above problems.

SUMMARY OF THE INVENTION An object of the present invention is to provide a bus control method suitable for a multiprocessor having a plurality of buses and including a processor that performs bleeding control.

The above and other objects and novel features of the present invention are as follows.
It will become apparent from the description of the present specification and the accompanying drawings.

[Means for solving the problem]

In order to achieve the above object, a bus control method according to the present invention is characterized in that a plurality of processors having an output buffer effective for a write access to a memory and capable of controlling the size of the memory and the memory are configured to perform memory access from the plurality of processors. In a configuration of a multiprocessor coupled by a plurality of buses having lock signals for performing exclusive control, a CPU of a predetermined processor performs read access with a lock signal turned on via a predetermined bus control unit and a bus. In the case of issuing, all the bus control units connected to other than the predetermined bus of the other processor detect the lock signal, and when there is no write access to the memory in the output buffer, it is notified that the output buffer is empty. On the other hand, when there is a write access to the memory in the output buffer, after performing the write access to the memory, The bus control unit that has issued the read access with the lock signal turned on notifies that the output buffer has been emptied, and the bus control unit receives a signal from all the bus control units connected to other processors than the predetermined bus. The most main feature is that after receiving the notification, the data read from the memory is sent to the CPU.

[Operation] According to the above-described means, when a predetermined CPU issues a read access with a lock signal turned on via a predetermined bus control unit and a bus, all of the other processors connected to other than the predetermined bus are output. The bus control unit detects the lock signal,
When there is no write access to the memory in the output buffer, it indicates that the output buffer is empty.On the other hand, when there is a write access to the memory in the output buffer, after performing the write access to the memory, Notifying the bus control unit that has issued the read access with the lock signal turned on that the output buffer has been emptied, the bus control unit transmits from all the bus control units other than the predetermined bus of the other processor. Since the data read from the memory is sent to the CPU after receiving the notification of the above, it is possible to realize a bus control method suitable for a multiprocessor having a plurality of buses and including a processor that performs control in advance. it can.

That is, the bus control system of the present invention is different from the conventional technology in that all the bus control units connected to buses other than the bus with the lock signal turned on detect a signal line for detecting the lock signal and the output of the bus control unit. The difference is that the buffer has a signal line for notifying the bus control unit that has turned on the lock signal whether or not the buffer has a write access to the memory.

(Example of the invention)

Hereinafter, an embodiment of the present invention will be specifically described with reference to the drawings.

FIG. 1 is a block diagram showing a configuration of a multiprocessor for explaining a bus control method according to an embodiment in which the present invention is applied to a multiprocessor having a plurality of buses and comprising a processor for performing bleeding control. FIG.

In FIG. 1, reference numeral 100 denotes a memory having shared data and a lock byte indicating whether or not the data is accessed;
101 and 103 are buses, 102 and 104 are signal lines for notifying whether or not the output buffer of the bus control unit has write access to the memory, and 105 and 106 are bus control units connected to buses other than the bus with the lock signal turned on. Signal lines for detecting signals; 107, 109, 112, and 114 are bus control units for controlling access to the memory 100; 108, 110, 113, and 115 are output buffers of the bus control unit necessary for performing cut-out control; and 111 and 116 are CPUs for executing instructions ( Instruction execution unit).

When the bus control method of the present invention is applied, in order to easily explain operations performed between a plurality of processors,
Except for the newly added two types of signal lines (102, 104, 105, 106), the entire block configuration is assumed to be exactly the same as the multiprocessor configuration in FIG.

Next, the operation of each processor in the configuration of the multiprocessor will be described.

The CPU 116 of the processor # 2 turns on the lock signal of the bus 0, executes the test & set instruction via the bus control unit 112 and the bus 101, and sets the lock byte at address 0 in the memory to “1”. Set to " The processor # 2 that has set the lock byte turns off the lock signal of the bus 101 and acquires an access right to the shared data at address 1 (the original data is assumed to be A).

The CPU 116 of the processor # 2 includes a bus control unit 114, a bus 103
, A read access is made to the shared data at the address 1 on the memory 100, and the processing is performed in the CPU.

Next, the CPU 116 of the processor # 2 writes the processed shared data (the new data is assumed to be B) to the area of the address 1 in the memory 100 (ST1). B) to the bus control unit 11
Send to 4.

The bus control unit 114 stores ST1 in the output buffer 115,
The PU 116 is notified of the end of the write access.

Subsequently, the CPU 116 of the processor # 2 sends a write address and data (the address is 0 and the data is に) to the bus control unit 112 in order to reset the lock byte at address 0 on the memory 100 (ST2).

The bus control unit 112 stores ST2 in the output buffer 113,
The PU 116 is notified of the end of the write access.

Next, the bus control unit 112 of the processor # 2 acquires the bus right of the bus 0, sends out the ST2 stored in the output buffer to the memory 100 via the bus 101, and stores the lock byte at the address 0. Reset from “1” to “0”. At this time, the bus 103 happens to be used by the processor # 1 or an input / output control channel (not shown), the bus control unit 114 cannot acquire the bus 103, and the ST1 returns to the bus control unit 114.
Is held in the output buffer 115.

FIG. 1 illustrates that the multiprocessor is in the state described above.

Assuming that the multiprocessor is in the state of FIG.
The CPU 111 of the processor # 1 issues a request to read the lock byte at address 0 on the memory 100 to the bus control unit 107 to execute the test & set instruction. The bus control unit 107 is a bus 101
, The lock signal of the bus 101 is turned on, and a read request for the address 0 on the memory 100 is issued.

At this time, the bus control unit 114 of the processor # 2
Signal line 105 indicates that the lock signal is on.
Detect through.

In response to the detection, the bus control unit 114
A write address and data (ST1: address is 1, data is B) for rewriting the shared data held in 15 are sent to the memory 100 via the bus 103, and the address 1 on the memory 100 is sent. Rewrite the shared data in “A” from “A” to “B”.

When the write access of the processor # 2 is completed, the output buffer 115 of the bus control unit 114 is empty, and the bus control unit 114 notifies the bus control unit 10 via the signal line 104 of the fact.
Report to 7.

After reading the lock byte from the memory 100, the bus control unit 107 of the processor # 1 sends the report to the CPU 111. Since the lock byte is 0, the CPU 111 acquires the access right to the shared data and sends a write access to set the lock byte to 1 to the bus control unit 107. Bus control unit 107
Stores the write access in the output buffer 108, and
Notify 111 of the end of the write access.

Next, the CPU 111 moves to reading of the shared data. At this time, the shared data has been rewritten to “B”, and the processing is performed without contradiction.

As mentioned above, although the present invention was explained concretely based on an example, the present invention is not limited to the above-mentioned example.
It goes without saying that various changes can be made without departing from the scope of the invention.

〔The invention's effect〕

As described above, according to the present invention, it is possible to adopt a multiprocessor configuration in which a processor for performing write-once control is connected by a plurality of buses, thereby achieving higher performance of the system.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a multiprocessor for explaining a bus control method according to an embodiment in which the present invention is applied to a multiprocessor having a plurality of buses and comprising a processor for performing bleeding control. FIG. 2 is an operation flowchart of exclusive control of write access to a memory performed by a processor, and FIG. 3 is a diagram for explaining an operation of a conventional multiprocessor having a plurality of buses. In the figure, 100 ... memory, 101,103 ... bus, 102,104 ...
Signal lines, 105, 106 ... signal lines, 107, 109, 112, 114 ... bus control units, 108, 110, 113, 115 ... output buffers, 111, 116 ...
…CPU.

Claims (1)

(57) [Claims] 1. A plurality of processors and a memory are connected by a plurality of buses, and each processor comprises an instruction execution unit and a plurality of bus control units provided for the bus for controlling access to the memory. The memory access from the instruction execution unit is uniquely determined according to a predetermined rule as to which bus control unit is to be accessed by an address, and each bus is a lock for exclusive control of a memory accelerator from a plurality of processors. A memory access request from another processor while the lock signal is on, the bus control unit has an output buffer,
When the address and data are stored in the output buffer for the write access from the instruction execution unit, the end of the write access is notified to the instruction execution unit, and the write address and data are sent to the memory when the bus can be acquired. In the multiprocessor bus control method described above, when a predetermined instruction execution unit issues a read access with a lock signal turned on via a predetermined bus control unit and a bus, the read access is connected to a bus other than the predetermined bus of another processor. All bus control units detect the lock signal and indicate that the output buffer is empty when there is no write access to the memory in the output buffer, and when the bus buffer has write access to the memory in the output buffer. Turned on the lock signal indicating that the output buffer was empty after performing the write access to the memory. The bus control unit that has issued the data access, receives the notification from all the bus control units other than the predetermined bus of the other processor, and then executes the data read from the memory. A bus control method characterized by sending to a section.