JPS6138504B2 - - Google Patents

Description

[Detailed description of the invention]

The present invention relates to a virtual storage device in which a conversion device commonly used by a plurality of processors is provided in a memory controller connected to a main storage device. The present invention relates to a data processing apparatus in which a job processor that performs the following has a cache memory. When multiple processors share an address translation device like this, the amount of hardware can be reduced compared to when each processor has its own address translation device, and information gaps between address translation devices can be reduced. Since this does not occur, control can be simplified. Also, the cache memory is added to each processor. However, in such a configuration, several problems occur because the connection between the cache memory and the address translation device is reversed from the usual case.
One of the problems is cache memory control when a page fault occurs. When rolling out pages using the virtual memory method, the address translation table is updated.
At this time, pages to be rolled out may be stored in the cache memory, but scanning the cache memory and invalidating the relevant blocks for this purpose is fatal in terms of performance. This is not realistic as it would lead to a significant decline. Therefore, even if the referenced data does not exist in the main memory (hereinafter referred to as main memory),
If it exists in cache memory, this data will be used. This does not cause any problems because the cache memory can be thought of as a partial copy of the entire virtual memory including auxiliary memory, rather than simply a partial copy of the main memory. With the above usage,
A cache error occurred when reading (READ),
An object of the present invention is to perform cache memory control when a page fault occurs when accessing main memory, and also control when a page fault occurs when writing (WRITE), without any contradiction. . The cache memory has a validity indicator that indicates whether a block, which is a unit of copying of the main memory, is valid or not. When accessing the main memory due to a cache miss, first set the valid display section to "1" (set) and then access the main memory. The reason for this is that when another processor writes to the same main memory area, the effective display section is set to ``0'' (cleared) so that the block cannot be used thereafter. If the valid display section is set to "1" after the access is completed, even if another processor writes after activation, it will be mistaken as if the correct data is being held. Because of the control described above, if a page fault occurs during READ, it is necessary to clear the relevant valid display area to make the relevant block unusable. Furthermore, if the corresponding block is still in the cache memory at the time of WRITE, it is necessary to receive a page fault signal and clear the valid display area. A feature of the present invention is that the cache memory includes a controller that performs the above control. Hereinafter, one embodiment of the present invention will be described in detail with reference to the drawings. FIG. 1 is a diagram showing an example of the overall configuration of a data processing device to which the present invention is applied. In FIG. 1, a main memory 10 stores programs and data, and is connected to a common bus 50 via a memory bus 11 and a memory controller (MCU) 12. 20 is an external memory for storing programs and data to be stored in the main memory 10; an external memory bus 21; a file processor (FCP);
22 to a common bus 50. 3
0 is an input/output processor (IOP), which controls data transfer with various input/output devices (not shown). A job processor (JOBP) 40, only one of which is shown here, executes programs (instructions). The job processor 40 has an instruction cache 4
1, a data cache 42, an I unit 43 and an E unit;
1 and I unit 43 are connected by bus 45, data cache 42 and E unit 44 are connected by bus 46, and I unit 43 and E unit 44 are connected by bus 47. In this way, the file processor 22, input/output processor 30, and job processor 40 are all connected to the common bus 50, and can access the main memory 10 via the memory controller 12. The job processor 4 performs pipeline processing using an I unit 43 and an E unit 44, and has an instruction cache 41 and a data cache 44 for each unit as described above. Note that the data handled by a program (instruction) is also called an operand, and this data cache is sometimes called an operand cache. When the I unit 43 accesses the instruction word to be executed next, it is first checked to see if the instruction word exists on the instruction cache 41, and if so, the data is sent as the instruction word via the bus 45. and is sent to the I unit 43. If it does not exist, the virtual address of the command is sent to the memory controller 12 via the common bus 50. The memory controller 12 converts the virtual address into a physical address and accesses the main memory 10 via the memory bus 11. The obtained data (commands) are sent to the instruction cache 41 via the common bus 50, and further sent to the I unit 43 via the bus 45, where they are processed and simultaneously sent to the instruction cache 41. Can be stored. The I unit 43 decodes this obtained command and asks the E unit 44 "what to do."
instruct. Based on this command, the E unit 44 collects the necessary data from internal registers or the data cache 42 (if it is not on the data cache 42, from the main memory 10 in the same way as the instruction cache), performs arithmetic processing, The result is stored in an internal register or main memory 10. The latter's main memory 1
When storing the result in 0, if the data at the corresponding location has already been taken into the data cache 42, that data is also updated. Next, a configuration example of the common bus 50 will be explained.
As shown in FIG. 2, the common bus 50 includes a startup bus 55, a data bus 56, a response bus 57, and these buses 55-5, which are used to actually transfer information.
A startup bus occupancy request line 51, a data bus occupancy request line 52, and a data bus occupancy request line 52 necessary for determining which processor or memory controller uses each of
Response bus occupancy request line 53 and interlock signal line 5
4 and is used on a time-sharing basis. The contents of the information on each bus 55 to 57 are as follows. (1) Startup bus 55 (a) Address (b) Type of access (for example, whether it is a read access/write access, how many bytes to access, etc.) (c) Access key (protection performed by the MCU 12) (2) Data bus 56 (a) Write data (b) Read data (3) Response bus 57 (a) End signal (b) Return code (errors and page faults that occurred during access) information) etc. FIG. 3 shows how these buses 55-57 are used. As shown in this figure, three combinations are transferred: (i) read request from a and read response from b, (ii) read request from a and write response from d, (iii) write request from c and write response from d. are possible simultaneously in the same time slot. Next, FIG. 4 shows how the buses 55 to 57 are used. In this figure, JOBP40 is set to time slot 0.
activates the memory read on the MCU 12, and the read data for it is sent to time slots N and N+1.
It has been returned in time slot 1, and in time slot 1
The IOP 30 issues a memory write start to the MCU 12, and a response is returned at time slot N+2. In this manner, the common bus 50 performs so-called split transfer in which activation and response are separated. Further, the main memory 10 is configured to be able to process multiple memory accesses. Before performing the transfer of the buses 55 to 57 described above, it is necessary to perform occupancy control.
This is done by the processor or memory controller that wishes to perform the transfer issuing occupancy requests 51 to 53 for the bus used for the transfer one time slot before the transfer, giving priority to these requests, and allowing the transfer. I'll do it. This prioritization method is
Various methods can be considered, but the details are omitted here. However, a response-based occupation request has a higher priority level than an activation-based occupation request. This is because if a response cannot be returned due to an occupancy request due to activation, the activation processing becomes stuck on the memory controller, resulting in a deadlock state. For example, in the case of this embodiment, if there is a conflict between the data read response b shown in FIG. 3 and the occupancy request caused by data write activation c shown in FIG. 3, the former is given priority. The above occupancy control is shown in a simplified manner in FIG. In time slot 0, JOBP40 and
Each of the IOPs 30 is issuing a startup bus occupancy request 51 in an attempt to start a read. Of these,
Assuming that JOBP 40 has a higher priority level than IOP 30, JOBP 40 uses the activation bus 55 to activate the read in time slot 1, and at the same time stops the occupancy request. On the other hand, since occupancy of IOP 30 was not permitted, the startup bus occupancy request 51 continues to be issued in time slot 1. Since there is no occupancy request from JOBP 40 in slot 1, IOP 30 can start reading in time slot 2. In such a system, when each processor accesses the main memory 10 by excluding access from other processors, that is, by interlocking, the startup bus 55 is prevented from being used by other processors. This is because by occupying the startup bus 55, future startups from other processors are excluded, and in response to memory startups that are already being processed in the main memory 10, the data bus 56 and response bus 57 are This is so that it can be used to return a response. If these responses cannot be returned,
This is because the startup process becomes stuck on the memory controller 12, resulting in a deadlock state. Next, an example of a method for occupying this startup bus 55 will be explained. A processor attempting to interlock and access the memory controller 12 receives a startup bus occupancy request 51 as shown in FIG.
At the time slot for transferring information to the startup bus 55, an interlock signal 54 indicating that the startup bus 55 is occupied is issued. This signal is used to control the activation bus occupancy request 51 from other processors so that it is not accepted. This is, for example, the seventh
This is realized by the circuit shown in the figure. In this figure, the priority determination circuit 61 for each occupancy request 51 to 53 is distributed for each processor, and the interlock signal line 5
4 is an open collector signal line. First, if the interlock signal 54 is not output,
A priority determination circuit 61 checks each of the occupancy requests 51 to 53, and if the activation bus occupancy request 51 issued by itself has the highest priority, an occupancy permission signal 64 for the activation bus 55 is passed through an AND gate 62 and an OR gate 63. coming out. This processor is therefore able to transfer information to the startup bus 55 in the next time slot. At this time, if the interlock request signal 65 is output from the processor, the JK flip-flop 6 is output via the AND gate 68.
6 is set and an interlock signal 54 is output. This interlock signal 54 is output until the interlock release signal 67 is issued, and during this time the processor continues to occupy the startup bus 55. Next, if the interlock signal 54 is being output from another processor, the output of the priority determination circuit 61 is prohibited by the AND gate 62, so the activation bus occupancy permission signal 64 is not output, and the activation bus 55 is It cannot be used and therefore cannot be started from memory. Next, the MCU 12 will be explained. In addition to normal memory access processing, the MCU 12 performs address translation from virtual addresses to physical addresses and protection checks. In addition, since it is commonly used between each processor and requires high throughput, the read processing and write processing are divided into several stages ~ or ~ as shown in Figure 8A and B. As shown in FIG. 8C, multiple accesses can be processed in an overlapping manner. FIG. 9 shows an example of the configuration of the MCU 12, and each processing stage shown in FIGS. 8A and 8B performs the following operations. (A): Operation of the read processing stage Receive read activation from the common bus 50 The virtual address (VA), access type (FUN), and access key (AKEY) on the activation bus 55 are taken into the common bus reception register 71. Address Translation and Protection Check The address translation device 75 converts the page indicated by the virtual address (VA) into the main memory 1.
It is determined whether the address is 0 or not, and if so, it is converted to a physical address (PA). If it does not exist, a so-called page fault occurs. At this time, the protection check circuit 76 determines whether or not the access is permitted. The address translation device 75 and protection check circuit 76 will be described in detail later. The results of these protection checks and page fault information are set in the access register 72 along with other error information as a return code (RC), access type (FUNC), and physical address (PA). Memory read activation If no error or page fault occurs in the access in the access register 72, the memory controller 77 applies memory activation 151 to the main memory 10 using the physical address (PA) on the access register 72, and When main memory 10 receives the activation, it transfers the access type (FUNC) and return code (RC) to temporary storage register 73. In addition, if the access in the access register 72 already indicates the occurrence of an error or page fault, the memory is not activated,
The above information is transferred to temporary storage register 73. Read data reception, data, response bus occupancy request Read data 154 is received from the main memory 10 via the memory bus 11, and the access type (FUNC) and return code (RC) are transferred to the common bus sending register 74. On the other hand, a data bus occupancy request 52 and a response bus occupancy request 53 are output to the common bus 50. When the read data and response bus transfer occupancy requests 52 and 53 are accepted, the read data 154 is transferred to the data bus 56 via the bus 155, and the end signal and return code (RC) are sent as a response via the bus 156. The data is transferred to the bus 57 and returned to the accessing processor. (B): Operation of write processing stage ′ Receive write activation from common bus 50 Virtual address (VA), access type (FUNC), access key (AKEY) on activation bus 55 and write data (WD) on data bus 56 ) into common bus reception register 1. ' The operation is the same as that of the read processing stage (A) except for address conversion and setting protection check write data (WD) in the access register 72. ' Start memory write Write data (WD) 153 to main memory 1
It is the same as the read processing stage (A) except that it is transferred to 0. 'Response bus occupancy request Move the access type (FUNC) and return code (RC) to the common bus transmission register 74. On the other hand, a response bus occupancy request 53 is output to the common bus 50. 'Response bus transfer' When the occupation request 53 of ' is accepted, the end signal and return code (RC) are transferred to the bus 15.
6 to the response bus 57 and returned to the accessing processor. As described above, read and write processing is divided into stages, and stages with different numbers for different access processing can be processed in parallel as shown in FIG. 8c. In this figure, the common bus 50
From (a) 4B ^yte read start, (b) B ^yte write start, (c)
16B ^yte read activations are received and processed in time slots 0, 1, and 2, respectively. Looking at the case of time slot 2, (a) memory read activation, (b) address translation and protection check, and (c) read activation reception from the common bus are performed in parallel. There is. Here, (c)
The 16B ^yte lead is ~ compared to the 4B ^yte lead in (A).
This stage is repeated four times, but this
This is because memory interleaving is performed in units of 4B ^yte . This will be explained below. FIG. 10 is a diagram showing an example of the configuration of the main memory 10, and shows a memory board (MB) 14 (14a to
14d) is configured with a data width of 4B ^yte , and memory boards 14a, 14b, 14c, and 14d are configured with a data width of 4B ^yte.
The lower 2 bits of the address added to the unit are 00, 01,
I have data that is 10, 11. and 16B ^yte
Since the data of 4B ^yte each is on the memory boards 14a, 14b, 14c, and 14d,
In the 16B ^yte read, it is possible to start up the memory boards in succession and read out the read data without causing any contention on the memory board 14, as shown in FIG. 8c. Such 16B ^yte reads are mainly used for block transfers to send data to the cache memory in the event of a cache miss. When the I unit 43 or the E unit 44 accesses the instruction cache 41 or the data cache 42, it is done in units smaller than 16B ^yte (in this example, 4B ^yte ), so when reading this 16B ^yte , the I unit The 4- ^byte data required by the E unit 43 and the E unit 44 is controlled to be delivered earlier than the rest of the data, thereby shortening the access time. To do this, the order of the memory boards 14 to be activated from the MCU 12 may be changed according to the address as shown in FIG. 10B. Next, address translation and protection checking will be explained in detail. FIG. 11 is a block diagram showing the address translation device 75 in FIG. 9 in more detail, and the first
FIG. 2 shows the operational flow of address translation. The virtual address to physical address conversion table 130 is placed in a part of the main memory 10 because its memory capacity is large. However, accessing the main memory 10 to convert a virtual address to a physical address every time a memory access occurs would result in a large overhead, so the TLB 110, which stores recently accessed address conversion information, is It is provided in MCU12. The TLB 110 contains an address translation table 13.
0, the contents of the most recently used page are stored. The contents of each page in the TLB 110 include a valid bit (V) 111, a connect (C) bit 112, and a portion of a virtual address (VPA) 11.
3. It consists of a part of the physical address (PPA) 114, an executed execution bit (EP) 115, and a storage key (SKEY) 116. V
Bit 111 and C bit 112 indicate the current state of the corresponding page, and when V bit 111 is "0", it indicates that the contents of the corresponding page in TLB 110 are not valid data (invalid). V bit 111 and C bit 112 are both “1”
In this case, it indicates that the page in question is currently being transferred between the main memory 10 and the external memory 20, that is, paging is in progress, and the V bit 111 is "1" and the C bit 112 is "1". 0'' indicates that the corresponding page is in the main memory 10 and can be accessed. In this way, the paging state is added to Elyria that is paging.
This is to prevent access other than paging access from the FCP 22. In this system, the MCU 12 performs address translation from a virtual address to a physical address in common to each processor, so the FCP 22 performs paging. Even if it is an access, it will go through the same address translation device 75, and if another processor is allowed to access the area being paged, it will lead to data destruction or loss. Therefore, as mentioned above,
When both the V bit 111 and the C bit 112 indicate "1", the above-mentioned inconvenience is solved by permitting only paging access from the FCP 22. Next, part of the virtual address (VPA) 113 is
When performing address translation in the TLB 110, it is used to check whether the translation pair of the corresponding virtual address (VA) is registered in the TLB 110.
14 is for creating a physical address (PA) when a translation pair is received in the TLB 110. Virtual address (VA) includes segment address (SA) 121, page address (PA) 122,
It consists of an intra-page address (DISP) 123, and the above-mentioned part of the physical address (PPA) 114 is concatenated with the intra-page address (DISP) 123 to form a physical address (PA). Execution protection bit 115 (EP) is
This is to prevent erroneously reading and executing an instruction with respect to data, and if the protection check circuit 76 reads an instruction to an area where this bit is "1", an execution protection error will occur. Therefore, if the instruction cache 41 and data cache 42 are separated in the JOBP 40 as in this configuration example, all accesses to this area from the instruction cache 41 will result in an execution protection error. The storage key (SKEY) 116 is for write protection and is the access key (AKEY) transferred from the requesting processor.
At the same time, the protection check circuit 76
It is checked whether write access is allowed or prohibited; in the latter case, a write protection error occurs. AKEY is SKEY1 like this
In addition to being used to check for write protect errors by comparison with ECP 22, the data contains information on whether or not paging access is from the ECP 22 and information on whether or not it is an instruction read, and is also used for these protection checks. Next, the conversion process will be sequentially explained with reference to the flowchart of FIG. Types of memory access can be broadly divided into the following two types. That is, (1) memory access by a general processor, and (2) memory access during paging by the ECP 22. The distinction between access (1) and (2) is as follows:
It is on the access key AKEY and is transmitted to the address translation controller 125 via the signal line 140. First, address conversion for memory access and determination of access permission in the general case (1) will be explained. A virtual address output from a certain processor (JOBP 40 or IOP 30) is sent to the common bus reception register 7 in the MCU 12 via the common bus 50.
1 in the virtual address register 120. The virtual address set in this virtual address register 120 includes a segment address (SA) 121 and a page address (PA) 122.
First, write TLB using part 120-2 as address.
110. read out by this
The V bit 111 and C bit 112 of the TLB 110 entry are the address translation controller 1
25, and depending on the pattern, the subsequent processing is divided into three parts as shown in ~. This is the step (F0
5). When V bit 111=0 and C bit 112=0. This is shown as "0, 0" in FIG. 12, and as described above, the corresponding page (entry) of the TLB 110 is invalid, and the conversion table 130 on the main memory 10 is read.
(F10) The detailed operation at this time, that is, when a TLB miss occurs, will be described later. When V bit 111=1 and C bit 112=1. In Fig. 12, it is "1, 1", but at this time, part of the virtual address 120-1 and TLB
As a result of comparing the partial virtual address VPA113 of 110 with the comparator 124, it is found that they match,
If the TLB hit signal 141 is output (F205), this indicates that the corresponding page is currently being paged, so the memory access is prohibited and the address translation controller 125
A missing page fault signal 142 is output. (F45) When the TLB bit signal 141 is not output, it is a TLB miss, so the conversion table 130 on the main memory 10 is read out in the same way.
(F10) When V bit 111=1 and C bit 112=0. In FIG. 12, at the time of "1, 0", the TLB bit signal 141 is checked first,
(F30) If no output has occurred, check the protect error signal 143 from the protection check circuit 76, and if no error has occurred, check the in-page address field 123 of the virtual address register 120 and the physical address on the TLB 110. The part 114 is concatenated and the physical address is sent to the access register 7 via the selector 128.
2, sends its physical address to the memory address bus 152, and outputs a memory activation signal 151 from the memory controller 77 in order to access the main memory 10. (F40) Next, memory access during paging by the FCP 22 in (2) will be explained. The virtual address output from the FCP 22 is set in the virtual address register 120 within the MCU 12 via the common bus 50. In this case as well, first access TLB110,
Depending on the pattern of the V bit 111 and C bit 112 of the accessed entry in the TLB 110, the subsequent processing is divided into three parts as before. When the V bit 111=0 and the C bit 112=0, the conversion table 130 in the main memory 10 is read. (F10) When the V bit 111=1 and the C bit 112=1 At this time, the TLB bit signal 141 is checked. (F30) If the TLB bit is indicated, the main memory 10 is accessed using the physical address created on the access register 72. (F
40) If the TLB bit signal is not output,
The conversion table 130 in the main memory 10 is read. (F10) When the V bit = 1 and the C bit 112 = 0, the TLB bit signal 141 is checked.
(F215) When the TLB bit signal 141 is output, it means that a prohibited area is being accessed.
Notify FCP22 of the error. (F220) Next, the process of reading the conversion table 130 on the main memory 10 in the case of a TLB miss will be described. The conversion table 130 consists of a page table 132 having information necessary for address conversion and a segment table 131 holding the start address of the page table 132 in order to reduce the memory capacity required for the table. When TLB misses,
First, an adder 127 adds the contents of the register 126 (STOR) that holds the start address of the segment table and the segment address (SA) 121 of the virtual address register 120 to create a physical address. The contents are read onto the read data bus 155. This data holds the start address of the page table 132, and the adder 127 adds this value to the page address (PA) 122 of the virtual address register 120 to create an address, which is then used for conversion from the page table 132. Read out information. (F10) In addition to the M bit, this page table 132 includes information in the TLB 110 excluding the V bit 111 and a part of the virtual address 113 (VPA), and these M bits and C bits are used as the read data bus. The bit pattern is input to the address conversion controller 125 through a part 155-1 of the bit pattern 155, and the following processing is performed depending on these bit patterns. a○ When M bit = 0 and C bit = 0 This indicates that the corresponding page is not on the main memory 10 but on the external memory 20, and a missing page fault signal is issued in response to an access request for this page. 142 to notify the corresponding processor of the page fault. (F45) b○ When M bit = 0 and C bit = 1 The corresponding bit indicates that paging is currently in progress, so memory access other than FCP22 is prohibited,
A missing page fault signal 142 is issued. (F45) In the case of memory access from the FCP 22, it is registered in the TLB 110 and accessed. (F20) c○ When M bit = 1, C bit = 0 Part of read data 155-2
, part of the virtual address 120-1, and the V bit "1" are registered in the TLB 110, (F20)
Return to the V and C bit check routine. As described above, the address translation device 75
For memory accesses using virtual addresses from each processor, address translation from virtual addresses to physical addresses can be performed in a concentrated manner, simplifying the control of address translation. Furthermore, by changing the control method for access from the FCP 22 and access from other processors, it is possible to prohibit access from other processors to the page being paged, making it possible to preserve data. Next, the operation at the time of a missing page fault will be explained. When the requesting processor receives a page fault signal, it interrupts the task it was currently executing and stores the page containing the requested address in main memory 1.
0, activate FCP22. In response to this activation, the FCP 22 reads the corresponding page, and when this is completed, generates an end interrupt. At this time, since the necessary pages have been rolled into the main memory 10, the interrupted task is resumed. While this task is suspended, the processor performs other tasks. Next, the instruction cache 41 and data cache 4
2 will be explained. FIG. 13 is a diagram showing an example of the structure of the instruction cache 41. The data copied from the main memory 10 is stored in the cache data section 8.
1-I, and the address of the data is on directory 82-I and invalidation directory 83-I.
I, and information indicating whether these are valid or not is in the valid bit register 84-I. The contents of the directory 82-I and the invalidation directory 83-I are the same, and are separated to improve performance. The former is used to check whether the data accessed by the unit 43 is in the cache data section 81-I, and the latter is used to check whether the data written in the main memory 10 by another processor is in the cache data section 81-I.
1-I, the data is already old and must be invalidated (this is called invalidation processing), but this is used to check for that purpose. Next, the operation of this instruction cache 41 will be explained. Note that unlike the data cache 42, the instruction cache 41 does not process write accesses. FIG. 14 shows the flow when a read access cache miss occurs, and FIG. 15 shows the flow of invalidation processing. (1) Read access (see Figure 14) When the activation signal 91-I comes from the I unit 43, part of the virtual address 92-I, here bits 18-27, is used to access the directory 82-I.
The contents of the effective bit register 84-I are read out, and a match is checked between the contents of the directory 82-I and bits 0 to 17 of the virtual address 92-I using the comparator 160-I.
Also, the contents are parity checker 161-
Check with I. and comparator 16
If 0-I indicates a match, no parity error has occurred, and valid bit register 84-I indicates valid, the cache bit signal 1 is output through gate 169-I.
70-I is the instruction cache controller 16
2-I, and the instruction cache controller 162-I issues bit 18 of the virtual address.
-29, the contents of the cache data section 81-I are transferred to the read data bus 94-I.
At the same time, a completion signal 93-I is returned to the I unit 43. In the case of a cache miss, the instruction cache controller 162-I issues an activation bus occupancy request 51. If the occupancy request 51 is approved, the gate 85
-I and transfers the virtual address (VA), access type (FUNC), and access key (AKEY) to the startup bus 55. Note that this access key (AKEY) is appended with the fact that it is for command reading. The set signal 172-I sets bits 0 to 17 of the virtual address to the directory 82-I.
I, writes to the invalidation directory 83-I, and sets the valid bit register 84-I. The reason for performing this process at this point will be described later. From the MCU 12 via the data bus 56,
The read data (RD) is also sent to the response bus 57.
When the end signal and return code (information on errors and page faults that occurred during access) (RC) are sent through register 8.
6-Latch to I. As mentioned in the explanation of the MCU 12, the first data sent is the data accessed by the I unit 43, so the return code (RC) is the following (1).
When the state shown in ~(3) is shown (when the condition (a) shown in FIG. 14B is satisfied), the end signal 93-I, read data 94-I, and return code 95-I are returned to the I unit 43. . (1) NO Error (when no error occurs) (2) Page Fault (when a page fault occurs) (3) Soft Error (when a software error such as a protection error occurs) Also, Hard In the case of an error (an error caused by hardware), it can often be saved by accessing the main memory 10 again.
Perform a retry. Therefore, the above signal is not returned, but if the number of retries exceeds the specified number, that is, in the case of retry over, the above signal is returned in order to report an error. Then, the read data read from the main memory 10 is stored in the cache data section 81.
-Write to I. ,, The remaining read data sent from the MCU 12 is stored in the cache data section 81-.
Write to I. Since the end signal 93-I has already been returned to the I unit 43 at the stage , the I unit 43 can perform other operations during this time. In addition to this, at the stage of
It is checked whether an error or page fault has occurred in the stages of . . . , and if no error or page fault has occurred, the operation of the instruction cache 41 is stopped. If an error or page fault has occurred, the instruction cache controller 162-I outputs a valid bit clear signal 171-I to the valid bit register 84-I set at stage 162-I to clear the valid bit register 84-I and clear the valid bit register 84-I. The corresponding data in the data section 81-I is made unusable. Also, on the stage of
If a Hard Error occurs and the retry is not over (condition (a) shown in FIG. 14B is met), the process jumps to the stage for retrying. The above is the read access processing procedure,
As mentioned earlier, caches (both instruction and data caches) require so-called invalidation processing. The procedure will be explained below. (2) Invalidation processing (see Figure 15) The virtual address (VA) and access type (FUNC) being transferred to the startup bus 55 are loaded into the register 87 each time. Bits 18-27 of the above virtual address are used to register the invalidation directory. The invalidation determination circuit 165-I reads out the contents of the register 83-I and checks whether or not it is necessary to invalidate it.
8-I. And if you need to disable it, register 8
The corresponding valid bit 84- at the address of 8-I
Clear I. Therefore, invalidation determination circuit 1
Valid bit clear signal 171- from 65-I
Give I. Next, cases in which invalidation is necessary will be explained in detail. First, invalidation is performed when the type of access (FUNC) taken in from the activation bus 55 indicates a write access and it is from another source. Then, invalidation is performed when any of the following conditions is met. (a) Bit 18 of address of register 87-I
-27 reads the invalidation directory 83-I and its contents and address bits 0-17
are compared by the comparator 163-I, and when they match. (b) When the parity checker 164-I detects a parity error when reading the invalidation directory 83-I. (c) Invalidate directory 83-I to JOBP4
When used indoors. (Because it is not possible to check) I have described the invalidation process above, but next, in the read access stage (1), the day retrieval 8
2-I, writes the address to the invalidation directory 83-I and explains why the valid bit register 84-I must be set. FIG. 16 shows the case where the read access results in a cache miss and the main memory 10 is read.
The time chart shows how each part is used when cache invalidation processing conflicts with another write access to the main memory 10. Invalidation processing is indicated by diagonal lines, and for write accesses during transfer of the startup bus 55 and data bus 56 in time slots 1 and 3, respectively, the invalidation directory 83-I is checked in time slots 2 and 4. In the first half of time slots 3 and 5, the valid bit register 84-I is cleared and invalidated. On the other hand, the read access that resulted in a cache miss is accessed from startup bus 5 in time slot 2.
Since the address is transferred to main memory 1
The order of access to 0 is after the write access during transfer on the activation bus 55 in time slot 1 and before the write access during transfer on the activation bus 55 in time slot 3. Therefore, in order to maintain consistency between the data in the cache and the main memory 10, the address of the read access that caused the cache miss must be invalidated between time slots 2 and 4 when the write access checks the invalidation directory 83-I. Directory 83-I must be written to and valid bit register 84-I must be set between time slots 3 and 5 to invalidate valid bit register 84-I as a result of the check. The reason why these controls are necessary is that main memory 1
This is because multiple memory accesses are being processed simultaneously at 0. In this configuration example, address information is stored in two places,
In other words, since it is stored in the directory 82-I and the invalidation directory 83-I, only the invalidation directory 83-I is subject to the above restrictions, but if you have the directory in one place, of course the above restrictions apply. subject to restrictions. Next, the data cache 42 will be explained. FIG. 17 is a diagram showing an example of the configuration of the data cache 42, in which the invalidation processing circuit 180-
D is omitted because it is the same as the instruction cache 41. It should be noted that the items in Figures 13 and 17 whose only difference is the suffix are equivalent. 13th
The instruction cache shown in the figure uses I for the suffix, and the data cache shown in FIG. 17 uses D for the suffix. The major difference from the instruction cache 41 is that it must support write access, and in order to shorten this write access time, a common bus sending buffer 8 is used.
9-D is provided, and when writing, virtual address 92 is provided.
-D, write data 95-D, control information 96-
Just by setting D to this buffer 89D,
The end signal 93-D is returned to the E unit 44, and the E
The unit 44 controls the following processing. Next, the operation of this data cache 42 will be explained. However, since the read access process is the same as that for the instruction cache 41, a description thereof will be omitted. (3) Write access (see Figure 18) When the activation signal 91-D comes from the E unit 44, the virtual address 92-D, write data 95-D, control information 96-D (access type, access key, etc.) is set in the common bus sending buffer 89-D, and an end signal 93-D is returned to the E unit 44. At this time, the directory 82-D and valid bit register 84-D are checked, and if the cache bit is present (signal 170-D is output), bit 18-D of the virtual address of the cache data section 81 is checked.
Data is written to the position indicated by 27. Data cache controller 162-D
A startup bus occupancy request 51 and a startup bus occupancy request 52 are issued. When both occupancy requests are granted, the gate 85-D is opened and the virtual address (VA), access type (FUNC), and access key (AKEY) are transferred to the startup bus 55, and the write data is transferred to the data bus 56. Forward. When the end signal and return code are sent from the MCU 12 via the response bus 57, they are latched into the register 86-D. Then, the return code is checked, and if no error or page fault has occurred, the access is removed from the common bus sending buffer 89-D, and the process is terminated. On the other hand, if the condition (a) shown in FIG. 14B is met, that is, a hard error occurs and retry is not over, the process jumps to the stage for retrying. In cases other than the above, the effective bit register 84-D is cleared with the address of the common bus sending buffer 89-D, and the occurrence of an error page fault is reported to the E unit 44. Valid bit register 84-D
The reason for clearing is that, in the case of a protection error, for example, data in the cache data section 81-D that should not be written has already been written in the stage. In addition, from the data cache 42 to the main memory 1
The address that was written to 0 and activated is also activated on the activation bus 55.
From data cache register 87-D
(included in the invalidation process circuit 180-D), but since it was issued by the data cache controller 162-D, the invalidation process circuit 180-D A signal 173-D is sent to D to control it so that it is not invalidated. Since the instruction cache 41 does not perform write access, there is no equivalent to this signal 173-D. As explained in detail above, according to the present invention,
In a virtual memory data processing device that shares an address translation device and has a cache memory in which the job processor has a cache memory, the cache memory is It is possible to control the storage memory and also control when a page fault occurs during writing without inconsistency.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing the overall configuration of a data processing device to which the present invention is applied, FIG. 2 is a diagram showing an example of the configuration of the common bus in FIG. 1, and FIG. Diagram showing how to use parts, 4th
The figure shows an example of how the common bus is used, Figure 5 shows how the common bus is controlled for occupancy, and Figure 6 shows how the common bus is controlled when the interlock signal is output. , FIG. 7 is a diagram showing an example of the configuration of the occupancy control circuit, and FIG. 8 A1 to CC are diagrams showing an example of the processing flow in the MCU and that the MCU processes multiple accesses in an overlapping manner. Figure 9 is a diagram showing an example of the configuration of an MCU, Figures 10A and B are diagrams showing an example of the configuration of a memory board and the order of data return when reading 16B ^yte , and Figure 11 is an address translation device using a TLB. 12 is a diagram showing the flow of address conversion, FIG. 13 is a diagram showing an example of the structure of an instruction cache, FIG. 14 is an explanatory diagram of the processing flow when reading access to the cache, and FIG. The figure is an explanatory diagram of the processing flow of cache invalidation, Figure 16 is a diagram showing an example of the usage timing of each part of the cache, Figure 17 is a diagram showing an example of the configuration of a data cache, and Figure 18 is a diagram showing write access. FIG. 2 is an explanatory diagram of the processing flow of FIG. 10...Main storage device, 12...Memory access controller, 41...Instruction cache, 42...
...Data cache, 43...I unit, 44
... E unit, 50 ... common bus, 75 ... address translation device, 81 ... cache data section,
82... Directory, 162... Cash controller.

Claims (1)

[Scope of Claims] 1. A virtual memory type data processing device in which an address translation device commonly used by a plurality of processors is provided in a memory controller connected to a main storage device, which executes instructions. The job processor includes at least one job processor that performs memory access using a virtual address in order to perform a memory access, and the job processor is provided with a cache memory that is accessed using a virtual address, and the cache memory includes a valid indicator of a data block corresponding to a virtual address. has
Taking into consideration the contents of the valid display area, at the time of read access, if there is a corresponding data block in the cache memory, it will be read out and sent back, otherwise a virtual address will be sent to the address conversion device, and at the time of write access, the data block will be sent to the address translation device. If there is a corresponding data block in the cache memory, the data is written to the main memory at the same time as the data is written to the cache memory. When a page fault occurs during read access to the main memory, the storage memory controller clears the valid display area of the data block corresponding to the virtual address, and when a page fault occurs during write access, it clears the valid display area of the data block corresponding to the virtual address. If the data block is in the cache memory,
A data processing device characterized in that a valid display portion of the data block is cleared. 2. If a cache error occurs during read access, the cache memory controller will
A patent that outputs a memory activation signal to the main storage device, sets the valid display area of the corresponding block, and clears the valid display area when a page fault signal is received from the address translation device. A data processing device according to claim 1.