JPS6113261B2 - - Google Patents

Description

[Detailed description of the invention]

The present invention relates to a data processing device in which a plurality of processors share one main memory (hereinafter referred to as main memory). Here, at least one of the plurality of processors is a processor that accesses memory using a virtual address in order to execute instructions, and this processor is herein referred to as a job processor. In addition, at least one processor is a processor that accesses memory using a virtual address in order to perform input/output with an external storage device (hereinafter referred to as external memory), which is also called an auxiliary storage device. is called a file processor. The job processor is also provided with a cache memory that is accessed using virtual addresses. Further, the data processing device according to the present invention includes an address translation device that is commonly used by each processor and converts a virtual address into a physical address. The present invention solves the problem that occurs when the file processor updates the address translation table when rewriting the contents of the main memory (page roll-in, page roll-out) in such a data processing device. The present invention relates to a data processing device that solves problems arising from the collapse of the conventional idea that the main memory is a copy of the main memory. First, the background of the present invention will be explained in detail. A data processing device in which one main memory is shared by multiple processors is generally referred to as a multiprocessor system. Conventional multiprocessor systems generally allow for multi-system configuration without imposing the cost/performance of a single computer. Therefore, the number of processors is
With about two processors, it was the best configuration, but as the number of processors increased further, there was a problem that mutual interference increased and the hardware configuration became too large. One of the problems that must be solved in multiprocessor systems is the virtual memory system. The virtual memory method is well known, and it assumes that main memory and external memory are apparently one unit. teeth,
The system automatically transfers information from a relatively unused portion of main memory to external memory, and transfers requested information from external memory to main memory. Transferring information from main memory to external memory is called rollout, and conversely, transferring information from external memory to main memory is called rollin. In order to perform such roll-in and roll-out control, the main memory and external memory are generally divided into units called pages. For each page, information is provided as to whether the page is currently in main memory, and if so, what the corresponding physical address (also called real address) in main memory is. placed on the conversion table. The address at the time of memory access from the processor is given as a virtual address, the translation table is indexed using the upper address part, and translation into a physical address is performed. Such a translation table is required for the number of pages of virtual addresses, and the required memory capacity becomes large. Therefore, in an attempt to reduce the capacity, the translation table is divided into two levels, such as a segment table and a page table. Many of them perform address translation. As mentioned above, the conversion table requires a large memory capacity, so it is generally placed in the main memory. Therefore, if the conversion table in the main memory is checked every time there is a memory access from the processor, three or more memory accesses will always occur for one memory access request, and the overhead cannot be ignored. Therefore, for processors that use virtual memory,
Many devices are equipped with a high-speed buffer called a TLB, and this high-speed buffer stores the physical address corresponding to the recently used virtual address. According to this, when a memory access from the processor occurs, it is first checked to see if there is a corresponding address in the TLB, and if there is, the memory access of the translation table for address translation is performed. Access is possible with less address translation overhead. Conventionally, such an address translation device including a TLB was placed in each processor, and a virtual control method was realized with the help of a control device within the processor. On the other hand, in order to improve performance, it has become common to provide each processor with a high-speed memory called a cache memory. This cache memory is a copy of a portion of main memory and is typically designed to be 5 to 10 times faster than main memory. When accessing memory from the processor, it first checks to see if there is a corresponding item in the cache, and if so, the contents are returned, and if not, the main memory is accessed. By the way, when using a virtual memory system and having a cache memory, conventionally, from the perspective of the processor,
TLB, cache memory, and main memory were connected in that order. This is based on the idea that cache memory is a copy of main memory, which is real storage, and access to cache memory must be performed after converting it to a physical address. Such conventional methods have the following problems. The first problem is that the effective memory access time becomes longer. The reason for this is that when accessing cache memory from the processor, it must always go through the TLB. That is, the virtual address from the processor is converted into a physical address by the TLB before the cache memory is accessed. The second problem is that TLB is required for all processors, so when the number of processors increases, not only does the amount of hardware increase accordingly, but also the TLB deviation must be corrected, which increases complexity. It's a familiar thing. Correcting TLB drift is when a processor swaps a page, the translation system
update the entry for the processor, but notify not only the processor concerned but also other processors to that effect.
The relevant part must be cleared. This is generally done by TLB Purge (Translation
It is called "Lookaside Buffer Purge" and is one of the important points when configuring a multiprocessor. The third problem arises from the fact that general job processors use virtual addresses when accessing memory, but input/output processors do not have a TLB and therefore access using physical addresses. The problem is that overhead increases because conversion is required when transferring data. The fourth problem is similar to the second problem, but even if it is not a multiprocessor, in a processor that performs advanced pipeline control, the unit that accesses instructions and the unit that accesses operands are separate. , each unit has a cache memory to increase speed, but in this case too, in the conventional system, each unit must have a TLB, which increases the amount of hardware. In order to solve this problem, Japanese Patent Laid-Open No. 49-53339 discloses a method in which the cache memory is accessed using virtual addresses and address translation is performed only when no bits are present. According to this, it is no longer necessary to perform address conversion every time the cache memory is accessed, and it becomes possible to achieve higher speed. However, this publication points out that this method cannot be adopted because it has the following drawbacks. It does not work if (1) two different virtual addresses refer to the same physical address; This is because when the contents of a certain virtual address are rewritten, the contents of the cache memory designated by another virtual address indicating the same physical address must also be rewritten. (2) When rewriting the contents of a page or segment table, a scan is required to invalidate the cache. (3) Since storage keys correspond to physical addresses, protection checks are impossible. There are three points. Japanese Unexamined Patent Publication No. 56-38649 similarly discloses a method of accessing a cache memory using a virtual address, but does not mention a solution to the above problem. Furthermore, Japanese Patent Application Laid-Open No. 142476/1983 discloses a system in which an address translation device is shared by a plurality of processors. According to this, since it is shared by a plurality of processors, it is possible to achieve economical efficiency in a multiprocessor configuration, but the cache memory is not shown here. The present invention is applied to a configuration in which there are a plurality of processors, at least one of which has a cache memory that is accessed using a virtual address, and an address translation device is shared by all the processors. The purpose of such a configuration is to reduce the amount of hardware required for the address translation device and to shorten the effective memory access time. Another purpose is to provide a method that does not require complicated processing such as matching control between TBLs. Another purpose is to provide a method that allows input/output processors to access memory using virtual addresses, with the aim of unified address management. Another purpose is to realize a high-speed and economical memory control method in a computer consisting of a plurality of units that perform pipeline control. However, the biggest problem with this method is that, as pointed out in JP-A No. 49-53339, when a page or segment table in main memory is rewritten, this is not transmitted to the cache memory; This is when the contents of memory no longer correctly reflect the state of main memory. An object of the present invention is to provide a data processing device that solves this problem. Next, the concept of how the present invention solves the problems pointed out in the above-mentioned Japanese Unexamined Patent Publication No. 49-53339 will be explained. The first problem is that two virtual addresses cannot point to the same physical address.This need is necessary in the case of multiple virtual memory; The first factor is that the bit length for specifying the address is 24.
This was necessary when the virtual space was small, about ²²⁴ bits, and insufficient in size, at about 224 = 16Mega, and if it could support virtual spaces as large as ²³² = 4Giga and ²⁴⁸ = 256Tera, it would eliminate the need for multiple virtual memory. There are few. Furthermore, coplanar subroutines and accessing data using different virtual addresses are not good methods because area management becomes complicated. Therefore, in the case of a single virtual memory where all programs and data are assigned unique addresses, this is not a problem. Next, the second problem, which is essential when accessing a cache using a virtual address, will be explained in some detail. The address translation table is updated when (i) a missing page fault occurs during execution of a program and a necessary page is rolled in, or when a page is rolled out to create an empty area. and,
(ii) This is the case when a program is generated and assigned to a certain virtual address or deleted. In such cases, the cache memory may contain data that has already been rolled out and is not in the main memory, or the previous program may remain in the cache memory even though a new program has been generated. I will do it. On the other hand, in cash,
In that the information that has already been rolled out remains, the cache memory can be thought of as a cache in the space including the external memory, and there is no problem even if the information that has already been rolled out can be read. Conversely, the size of the main memory increases by the capacity of the cache, which can be said to be an advantage of this method. When attempting to write to main memory, with store-through type cache memory, both the cache and main memory are updated each time a write is made.
Each time it passes through an address translator, it is checked whether the page is in main memory or not. Therefore, a program running using rolled out pages will continue to read as long as the cache is hit, and a page fault will occur when a cache miss occurs or a main memory write occurs. It turns out. Here, the check in the address translation device means that the state of the page is (a)
There are three states: existing in main memory, (b) paging, and (c) not existing in main memory.A general processor can only access in (a), and transfers to and from external memory. A file processor that does (b)
It is possible to access the site even when , and it is a check to see if this rule is met. When a page fault occurs, the corresponding block in the cache memory is invalidated, so it will no longer be hit in the cache. Note that if a page fault occurs during read access, the block is controlled not to be written to the cache. Next, when the program that has been running so far is completed and a new program is generated at the same virtual address, it is normally transferred from external memory, but in this case, The problem is solved by providing a means to invalidate the cache during the transfer. Specifically, transfers from external memory to main memory are performed using virtual addresses, and this address is monitored by cache memory, and if there is a corresponding block in cache memory, it is invalidated. It is something. Next, regarding the third problem of protection, virtual addresses are considered to be a better method of protection than physical addresses since it is possible to allocate a unique storage key to each program. However, since writing always passes through the address translation device, write protection is always checked. When a write protect error is detected, the corresponding block in the cache memory is invalidated to prevent the data written to the cache memory from being used. Execution protection needs to be devised so that if there is a corresponding item in the cache, it is returned here so that it does not go through the address translation device in order to read the memory. In the present invention,
An example is shown in which the cache memory is separated into an instruction cache and a data cache. In this example, if an execution protection error occurs, the cache memory is controlled not to be stored in the cache memory. From the above, it is believed that the method of solving the problems of the present invention that has been considered as a problem in the past has been understood, but the present invention also solves the problems of multiprocessors in a similar manner. In a conventional multiprocessor configuration, when the address translation table is rewritten, a command is sent to other processors to invalidate the TLB owned by the other processor (TLB
Purge). This allows the program to be saved even if the previous program remains in cache memory.
By invalidating the TLB, it was possible to prevent the relevant cache memory from being used. A problem with multiprocessors to which the present invention is applied is that when one processor rewrites the address translation table, the cache memory of another processor no longer matches the main memory. , the transfer from external memory is performed using a virtual address, and the cache memory monitors this virtual address, and if the corresponding block is in the cache memory, it is resolved by invalidating it. There is. Hereinafter, one embodiment of the present invention will be described in detail with reference to the drawings. FIG. 1 is a diagram showing an example of the overall configuration of a data processing device to which the present invention is applied. In FIG. 1, a main memory 10 stores programs and data, and is connected to a common bus 50 via a memory bus 11 and a memory controller (MCU) 12. 20 is an external memory for storing programs and data to be stored in the main memory 10; an external memory bus 21; a file processor (FCP);
22 to a common bus 50. 3
0 is an input/output processor (IOP), which controls data transfer with various input/output devices (not shown). A job processor (JOBP) 40, only one of which is shown here, executes programs (instructions). The job processor 40 has an instruction cache 4
1, a data cache 42, an I unit 43 and an E unit;
1 and I unit 43 are connected by bus 45, data cache 42 and E unit 44 are connected by bus 46, and I unit 43 and E unit 44 are connected by bus 47. In this way, the file processor 22, input/output processor 30, and job processor 40 are
Both are connected to a common bus 50, and the main memory 10 can be accessed via the memory controller 12. The job processor 4 performs pipeline processing using an I unit 43 and an E unit 44, and has an instruction cache 41 and a data cache 44 for each unit as described above. Note that the data handled by a program (instruction) is also called an operand, and this data cache is sometimes called an operand cache. When the I unit 43 accesses an instruction word to be executed next, it is first checked whether the instruction word exists on the instruction cache 41, and if it exists, the data is transferred to the bus 45 as an instruction word.
It is sent to I unit 43 via. If it does not exist, the virtual address of the command is sent to the memory controller 12 via the common bus 50. The memory controller 12 converts the virtual address into a physical address and accesses the main memory 10 via the memory bus 11. The obtained data (commands) are sent to the instruction cache 41 via the common bus 50, and further sent to the I unit 43 via the bus 45, where they are processed and simultaneously transferred to the instruction cache 41. Can be stored. The I unit 43 decodes this obtained command and asks the E unit 44 "what to do."
instruct. Based on this command, the E unit 44 collects necessary data from internal registers and the data cache 42 (if it is not on the data cache 42, from the main memory 10 in the same way as the instruction cache), performs arithmetic processing, The result is stored in an internal register or main memory 10. The latter's main memory 1
When storing the result in 0, if the data at the corresponding location has already been taken into the data cache 42, that data is also updated. Next, a configuration example of the common bus 50 will be explained.
As shown in FIG. 2, the common bus 50 includes a startup bus 55, a data bus 56, a response bus 57, and these buses 55-5, which are used to actually transfer information.
A startup bus occupancy request line 51, a data bus occupancy request line 52, and a data bus occupancy request line 52 necessary for determining which processor or memory controller uses each of
Response bus occupancy request line 53 and interlock signal line 5
4 and is used on a time-sharing basis. The contents of the information on each bus 55 to 57 are as follows. (1) Startup bus 55 (a) Address (b) Type of access (for example, read access/write access, how many bytes to access, etc.) (c) Access key (protection performed by MCU 12) (2) Data bus 56 (a) Write data (b) Read data (3) Response bus 57 (a) End signal (b) Return code (errors and page faults that occurred during access) information) etc. FIG. 3 shows how these buses 55-57 are used. As shown in this figure, three combinations are transferred: (i) read request from a and read response from b, (ii) read request from a and write response from d, (iii) write request from c and write response from d. are possible simultaneously in the same time slot. Next, FIG. 4 shows how the buses 55 to 57 are used. In this figure, JOBP40 is set to time slot 0.
activates the memory read on the MCU 12, and the read data for it is sent to time slots N and N+1.
It has been returned in time slot 1, and in time slot 1
The IOP 30 issues a memory write start to the MCU 12, and a response is returned at time slot N+2. In this manner, the common bus 50 performs so-called split transfer in which activation and response are separated. Further, the main memory 10 is configured to be able to process multiple memory accesses. Before performing the transfer of the buses 55 to 57 described above, it is necessary to perform occupancy control.
This is done by the processor or memory controller that wishes to perform the transfer issuing occupancy requests 51 to 53 for the bus used for the transfer one time slot before the transfer, giving priority to these requests, and allowing the transfer. I'll do it. This prioritization method is
Various methods can be considered, but the details are omitted here. However, a response-based occupation request has a higher priority level than an activation-based occupation request. This is because if a response cannot be returned due to an occupancy request due to activation, the activation processing becomes stuck on the memory controller, resulting in a deadlock state. For example, in the case of this embodiment, if there is a conflict between the data read response b shown in FIG. 3 and the occupancy request caused by data write activation c shown in FIG. 3, the former is given priority. The above occupancy control is shown in a simplified manner in FIG. In time slot 0, JOBP40 and
Each of the IOPs 30 is issuing a startup bus occupancy request 51 in an attempt to start a read. Of these,
Assuming that JOBP 40 has a higher priority level than IOP 30, JOBP 40 uses the activation bus 55 to activate the read in time slot 1, and at the same time stops the occupancy request. On the other hand, since occupancy of the IOP 30 was not permitted, the startup bus occupancy request 51 continues to be issued in time slot 1 as well. Since there is no occupancy request from JOBP 40 in slot 1, IOP 30 can start reading in time slot 2. In such a system, when each processor accesses the main memory 10 by excluding access from other processors, that is, by interlocking, the startup bus 55 is prevented from being used by other processors. This is because by occupying the startup bus 55, future startups from other processors are excluded, and in response to memory startups that are already being processed in the main memory 10, the data bus 56 and response bus 57 are This is so that it can be used to return a response. This is because if these responses cannot be returned, the startup process will become stuck on the memory controller 12, resulting in a deadlock state. Next, an example of a method for occupying this startup bus 55 will be explained. A processor attempting to interlock and access the memory controller 12 receives a startup bus occupancy request 51 as shown in FIG.
At the time slot for transferring information to the startup bus 55, an interlock signal 54 indicating that the startup bus 55 is occupied is issued. This signal is used to control the activation bus occupancy request 51 from other processors so that it is not accepted. This is, for example, the seventh
This is realized by the circuit shown in the figure. In this figure, the priority determination circuit 61 for each occupancy request 51 to 53 is distributed for each processor, and the interlock signal line 5
4 is an open collector signal line. First, if the interlock signal 54 is not output,
A priority determination circuit 61 checks each of the occupancy requests 51 to 53, and if the activation bus occupancy request 51 issued by itself has the highest priority, an occupancy permission signal 64 for the activation bus 55 is passed through an AND gate 62 and an OR gate 63. coming out. This processor is therefore able to transfer information to the startup bus 55 in the next time slot. At this time, if the interlock request signal 65 is output from the processor, the JK flip-flop 6 is output via the AND gate 68.
6 is set and an interlock signal 54 is output. This interlock signal 54 is output until the interlock release signal 67 is issued.
During this time, this processor continues to occupy the startup bus 55. Next, if the interlock signal 54 is being output from another processor, the output of the priority determination circuit 61 is prohibited by the AND gate 62, so the startup bus occupancy permission signal 64 is not output.
The startup bus 55 cannot be used, so memory startup is also not possible. Next, the MCU 12 will be explained. In addition to normal memory access processing, the MCU 12 performs address exchange from virtual addresses to physical addresses and protection checks. In addition, since it is commonly used between each processor and requires high throughput, read processing and write processing are divided into several stages ~ or '~' as shown in Figure 8A and B. , multiple accesses can be processed in an overlapping manner as shown in FIG. 8C. FIG. 9 shows an example of the configuration of the MCU 12, and each processing stage shown in FIGS. 8A and 8B performs the following operations. (A): Operation of read processing stage The virtual address (VA), access type (FUN), and access key (AKEY) on the read activation reception activation bus 55 are taken into the common bus reception register 71 from the common bus 50. Address Conversion and Protection Check The address conversion device 75 determines whether a page indicated by a virtual address (VA) exists in the main memory 10 or not, and if so, converts it into a physical address (PA). If not,
This is a so-called page fault. At this time, the protection check circuit 76 determines whether or not the access is permitted. The address translation device 75 and protection check circuit 76 will be described in detail later. The results of these protection checks and page fault information are set in the access register 72 along with other error information as a return code (RC), access type (FUNC), and physical address (PA). If no error or page fault occurs in the access to the memory read start access register 72, the memory controller 77 uses the physical address (PA) on the access register 72 to
A memory activation 151 is applied to the main memory 10, and when the main memory 10 receives the activation, the access type (FUNC) and return code (RC) are transferred to the temporary storage register 73. Furthermore, if the access in the access register 72 already indicates the occurrence of an error or page fault, the memory is not activated and the information is transferred to the temporary storage register 73. Read data reception, data, response bus occupancy request Read data 154 is received from the main memory 10 via the memory bus 11, and the access type (FUNC) and return code (RC) are transferred to the common bus sending register 74. On the other hand, a data bus occupancy request 52 and a response bus occupancy request 53 are output to the common bus 50. When read data and response bus transfer occupancy requests 52 and 53 are accepted,
The read data 154 is transferred to the data bus 56 via the bus 155, and the end signal and return code (RC) are transferred to the response bus 57 via the bus 156 and returned to the accessing processor. (B): Operation of the write processing stage ' Write activation reception from the common bus 50 Virtual address (VA) on the activation bus 55, access type (FUNC), access key (AKEY), and write data (WD) on the data bus 56 ) as common bus reception register 71
Incorporate into. ' The same operation as in read processing stage A is performed except for address conversion and setting protection check write data (WD) in the access register 72. ' Memory write activation write data (WD) 153 is transferred to main memory 10.
This is the same as in read processing stage A, except that the read processing stage is transferred to. The response bus occupancy request access type (FUNC) and return code (RC) are transferred to the common bus sending register 74. On the other hand, a response bus occupancy request 53 is output to the common bus 50. When the occupancy request 53 for 'response bus transfer' is accepted, the end signal and return code (RC) are transferred to the bus 156.
The data is transferred via the response bus 57 and returned to the accessing processor. As described above, read and write processing is divided into stages, and stages with different numbers for different access processing can be processed in parallel as shown in FIG. 8C. In this figure, the common bus 50
From A 4Byte read start, B 4Byte write start,
C. The 16-byte read activation is received and processed at time slots 0, 1, and 2, respectively. Looking at the case of time slot 2, (a) memory read activation 3, (b) address conversion and protection check 2', and (c) read activation reception 1 from the common bus are performed in parallel. Here, the
The 16Byte read is compared to the 4Byte read of
This stage is repeated four times, but this
This is because memory interleaving is performed in units of 4 bytes. This will be explained below. FIG. 10 is a diagram showing an example of the configuration of the main memory 10, and shows a memory board (MB) 14 (14a to
14d) consists of a data width of 4Byte, and each memory board 14a, 14b, 14c, 14d
The lower 2 bits of the address added in 4-byte units are
It has data that is 00, 01, 10, 11. Since the 16 Byte data is on the memory boards 14a, 14b, 14c, and 14d each having 4 Bytes,
When reading 16 Bytes, it is possible to start up the memory boards in succession and continue reading data without causing any contention on the memory board 14, as shown in FIG. 8C. Such a 16-byte read is mainly used for block transfer to send data to the cache memory in the event of a cache miss. When the I unit 43 and the E unit 44 access the instruction cache 41 and the data cache 42, it is done in units smaller than 16 bytes (4 bytes in this example), so when reading this 16 bytes, the I unit 43 and the E unit access the instruction cache 41 and the data cache 42. The 4-byte data required by 44 is controlled to be delivered faster than the rest of the data, reducing access time. To do this, the order of the memory boards 14 to be activated from the MCU 12 may be changed according to the address as shown in FIG. 10B. Next, address translation and protection checking will be explained in detail. FIG. 11 is a block diagram showing the address translation device 75 in FIG. 9 in more detail, and the first
FIG. 2 shows the operational flow of address translation. The virtual address to physical address conversion table 130 is placed in a part of the main memory 10 because its memory capacity is large. However, accessing the main memory 10 to convert a virtual address to a physical address every time a memory access occurs would result in a large overhead, so the TLB 110, which stores recently accessed address conversion information, is It is provided in MCU12. The TLB 110 contains an address translation table 13.
0, the contents of the most recently used pages are stored, so that address translation can be performed at high speed. The contents of each page in the TLB 110 include a valid bit (V) 111, a connect (C) bit 112, and a portion of a virtual address (VAP) 11.
3. consists of part of physical address (PPA) 114, execution protection bit (EP) 115 and storage key (SKEY) 116. V
Bit 111 and C bit 112 indicate the current state of the corresponding page, and when V bit 111 is "0", it indicates that the contents of the corresponding page in TLB 110 are not valid data (invalid). V bit 111 and C bit 112 are both “1”
In this case, it indicates that the page in question is currently being transferred between the main memory 10 and the external memory 20, that is, paging is in progress, and the V bit 111 is "1" and the C bit 112 is "1". 0'' indicates that the corresponding page is in the main memory 10 and can be accessed. In this way, the paging status is added to indicate the area where paging is being performed.
This is to prevent access other than paging access from the ECP 22. In this system, the MCU 12 commonly performs address translation from a virtual address to a physical address for each processor, so even if an access is performed for paging by the ECP 22, it will go through the same address translation device 75. Allowing other processors to access the area being paged can lead to data corruption or loss. Therefore, as mentioned above, V
When the bit 111 and the C bit 112 both indicate "1", the above-mentioned inconvenience is solved by permitting paging access only from the FCP 22. Next, part of the virtual address (VPA) 113 is
When performing address translation in the TLB 110, it is used to check whether the translation pair of the corresponding virtual address (VA) is registered in the TLB 110.
14 is for creating a physical address (PA) when a translation pair of TLB 110 is received. Virtual address (VA), segment address (SA) 121, page address (PA) 122,
It consists of an intra-page address (DISP) 123, and the above-mentioned part of the physical address (PPA) 114 is concatenated with the intra-page address (DISP) 123 to form a physical address (PA). Execution protection bit 115 (EP) is
This is to prevent erroneously reading and executing an instruction with respect to data, and if the protection check circuit 76 reads an instruction to an area where this bit is "1", an execution protection error will occur. Therefore, if the instruction cache 41 and data cache 42 are separated in the JOBP 40 as in this configuration example, all accesses to this area from the instruction cache 41 will result in an execution protection error. The storage key (SKEY) 116 is for write protection and is the access key (AKEY) transferred from the requesting processor.
At the same time, the protection check circuit 76
It is checked whether write access is allowed or prohibited; in the latter case, a write protection error occurs. The access key (AKEY) is SKEY1 like this
In addition to being used to check for write protect errors by comparison with ECP 16, it also contains information on whether or not there is a paging access from the ECP 22, and information on whether or not it is an instruction read, and is also used for these protection checks. Next, the conversion process will be sequentially explained with reference to the flowchart of FIG. Types of memory access can be broadly divided into the following two types. That is, (1) memory access by a general processor, and (2) memory access during paging by the ECP 22. The access distinction in (1) and (2) is
It is on the access key AKEY and is transmitted to the address translation controller 125 via the signal line 140. First, address conversion for memory access and determination of access permission in the general case (1) will be explained. A virtual address output from a certain processor (JOBP 40 or IOP 30) is sent to the common bus reception register 7 in the MCU 12 via the common bus 50.
1 in the virtual address register 120. The virtual addresses set in this virtual address register 120 are segment address (SE) 121 and page address (PA) 122.
First, write TLB using part 120-2 as address.
110. read out by this
The V bit 111 and C bit 112 of the TLB 110 entry are the address translation controller 1
25, and depending on the pattern, subsequent processing is divided into the following three steps. This is the flow step (FO
5). When V bit 111=0 and C bit 112=0. This is displayed as "0,0" in FIG. 12, and as described above, the corresponding page (entry) of the TLB 110 is invalid, and the conversion table 130 on the main memory 10 is read.
(F10) The detailed operation at this time, that is, when a TLB miss occurs, will be described later. When V bit 111=1 and C bit 112=1. In Fig. 12, it is "1, 1", but at this time, part of the virtual address 120-1 and TLB
As a result of comparing the partial virtual address VPA113 of 110 with the comparator 124, it is found that they match,
If the TLB hit signal 141 is output (F205), this indicates that the corresponding page is currently being paged, so the memory access is prohibited and the address translation controller 125
A missing page fault signal 142 is output. (F45) When the TLB hit signal 141 is not output, it is a TLB miss, so the conversion table 130 on the main memory 10 is read out in the same way.
(F10) When V bit 111=1 and C bit 112=0. In FIG. 12, at the time of "1, 0", the TLB hit signal 141 is checked first,
(F30) If no output has occurred, check the protect error signal 143 from the protection check circuit 76, and if no error has occurred, check the in-page address field 123 of the virtual address register 120 and the physical address on the TLB 110. The part 114 is concatenated and the physical address is sent to the access register 72 via the selector 128.
The physical address is sent to the memory address bus 152, and the memory controller 77 outputs the memory activation signal 151 in order to access the main memory 10. (F40) Next, memory access during paging by the FCP 22 in (2) will be explained. The virtual address output from the FCP 22 is set in the virtual address register 120 within the MCU 12 via the common bus 50. In this case as well, first access TLB110,
Depending on the pattern of the V bit 111 and C bit 112 of the accessed entry in the TLB 110, the subsequent processing is divided into three parts as before. When V bit 111=0 and C bit 112=0. The conversion table 130 in the main memory 10 is read. (F10) When V bit 111=1 and C bit 112=1. At this time, the TLB hit signal 114 is checked. (F30) If the TLB hit is indicated, the main memory 10 is accessed using the physical address created on the access register 72. (F
40) If the TLB hit signal is not output, read the conversion table 130 in the main memory 10.
(F10) When the V bit = 1 and the C bit 112 = 0, the TLB hit signal 141 is checked.
(F215) When the TLB hit signal 141 is output, it means that a prohibited area is being accessed.
Notify FCP22 of the error. (F220) Next, the process of reading the conversion table 130 on the main memory 10 in the case of a TLB miss will be described. The conversion table 130 consists of a page table 132 having information necessary for address conversion and a segment table 131 holding the start address of the page table 132 in order to reduce the memory capacity required for the table. When TLB misses,
First, an adder 127 adds the contents of the register 126 (STOR) that holds the start address of the segment table and the segment address (SA) 121 of the virtual address register 120 to create a physical address. The contents are read onto the read data bus 155. This data holds the start address of the page table 132, and the adder 127 adds this value to the page address (PA) 122 of the virtual address register 120 to create an address, which is then used for conversion from the page table 132. Read out information. (F10) In addition to the M bit, this page table 132 includes information in the TLB 110 excluding the V bit 111 and a part of the virtual address 113 (VPA), and these M bits and C bits are used as the read data bus. The bit pattern is input to the address conversion controller 125 through a part 155-1 of the bit pattern 155, and the following processing is performed depending on these bit patterns. When the M bit = 0 and the C bit is 0, this indicates that the corresponding page is not on the main memory 10 but on the external memory 20, and a missing page fault signal 142 is issued in response to an access request for this page. to notify the corresponding processor of the page fault. (F45) When M bit = 0, C bit = 1 Since the corresponding bit indicates that paging is currently in progress, memory access is prohibited for those other than FCP22,
A missing page fault signal 142 is issued. (F45) In the case of memory access from the FCP 22, it is registered in the TLB 110 and accessed. (F20) When M bit = 1, C bit = 0 Part of read data 155-2
, part of the virtual address 120-1, and the V bit "1" are registered in the TLB 110, (F20)
Return to the V and C bit check routine. As described above, the address translation device 75
For memory accesses using virtual addresses from each processor, address translation from virtual addresses to physical addresses can be performed in a concentrated manner, which simplifies control of address translation. Additionally, by changing the control method for access from FCP22 and access from other processors, it is possible to prohibit access from other processors to the page being paged, making it possible to maintain data integrity. . Next, the operation at the time of a missing page fault will be explained. When the requesting processor receives a page fault signal, it interrupts the task it was executing at the time and activates the FCP 22 to load the page containing the requested address into main memory 10. In response to this activation, the FCP 22 reads the corresponding page, and when this is completed, generates an end interrupt. At this time, the required pages are 10 pages in main memory.
Resume the suspended task due to which it has been rolled up. While this task is suspended, the processor performs other tasks. Next, the instruction cache 41 and data cache 4
2 will be explained. FIG. 13 is a diagram showing an example of the structure of the instruction cache 41. The data copied from the main memory 10 is stored in the cache data section 8.
1-I, and the address of the data is on directory 82-I and invalidation directory 83-I.
I, and information indicating whether these are valid or not is in the valid bit register 84-I. The contents of the directory 82-I and the invalidation directory 83-I are the same, and are separated to improve performance. The former is used to check whether the data accessed by the I unit 43 is in the cache data section 81-I, and the latter is used to check whether the data written in the main memory 10 by another processor is in the cache data section 81-I.
1-I, the data is already old and must be invalidated (this is called invalidation processing), but it is used to check for this purpose. Next, the operation of this instruction cache 41 will be explained. Note that unlike the data cache 42, the instruction cache 41 does not process write accesses. FIG. 14 shows the flow when a read access cache miss occurs, and FIG. 15 shows the flow of invalidation processing. (1) Read access (see Figure 14) When the activation signal 91-I comes from the I unit 43, part of the virtual address 92-I, here bits 18-27, is used to access the directory 82-I.
I and the contents of the valid bit register 84-I are read, and a match is checked between the contents of the directory 82-I and bits 0 to 17 of the virtual address 92-I using the comparator 160-I.
Also, the contents are parity checker 161-
Check with I. and comparator 16
0-I indicates a match, no parity error has occurred, and valid bit register 84-I
indicates that the instruction
62-I, and the instruction cache controller 162-I registers bit 1 of the virtual address.
The contents of the cache data section 81-I accessed at 8-29 are transferred to the read data bus 94.
-I, and returns an end signal 93-I to the I unit 43. In the case of a cache miss, the instruction cache controller 162-I issues an activation bus occupancy request 51. If the occupancy request 51 is approved, the gate 85
-I and transfers the virtual address (VA), access type (FUNC), and access key (AKEY) to the startup bus 55. Note that this access key (AKEY) is appended with the fact that it is for command reading. The set signal 172-I sets bits 0 to 17 of the virtual address to the directory 82-I.
I, writes to the invalidation directory 83-I, and sets the valid bit register 84-I. The reason for performing this process at this point will be described later. From the MCU 12 via the data bus 56,
The read data (RD) is also sent to the response bus 57.
When the end signal and return code (information on errors and page faults that occurred during access) (RC) are sent through register 8.
6-Latch to I. As mentioned in the explanation of the MCU 12, the first data sent is the data accessed by the I unit 43, so the return code (RC) is the following (1).
When the state shown in ~(3) is shown (when condition A shown in FIG. 14B is satisfied), an end signal 93-I, read data 94-I, and return code 95-I are returned to the I unit 43. (1) No Error (when no error occurs) (2) Page Fault (when a page fault occurs) (3) Soft Error (when a software error such as a protection error occurs) Hard Errors (errors caused by hardware) can often be saved by accessing the main memory 10 again.
Perform a retry. Therefore, the above signal is not returned, but if the number of retries exceeds the specified number, that is, in the case of retry over, the above signal is returned in order to report an error. Then, the read data read from the main memory 10 is stored in the cache data section 81.
-Write to I. ,, The remaining read data sent from the MCU 12 is stored in the cache data section 81-.
Write to I. Since the end signal 93-I has already been returned to the I unit 43 at the stage , the I unit 43 can perform other operations during this time. In addition to this, at the stage of
It is checked whether an error or page fault has occurred in the stages of . . . , and if no error or page fault has occurred, the operation of the instruction cache 41 is stopped. If an error or page fault has occurred, the instruction cache controller 162-I outputs a valid bit clear signal 171-I to the valid bit register 84-I set at stage 162-I to clear the valid bit register 84-I and clear the valid bit register 84-I. The corresponding data in the data section 81-I is made unusable. Also, on the stage of
If a Hard Error occurs and the retry is not over (condition A shown in FIG. 14B is satisfied), the process jumps to the stage for retrying. The above is the processing procedure for read access, but as mentioned earlier, cache (both instruction and data cache) requires so-called invalidation processing.
The procedure will be explained below. (2) Invalidation processing (see FIG. 15) The virtual address (VA) and access type (FUNC) being transferred on the startup bus 55 are loaded into the register 87 each time. The contents of the invalidation directory 83-I are read using bits 18-27 of the virtual address, and the invalidation determination circuit 165-I checks whether or not invalidation is necessary. Register 8
8-I. And if you need to disable it, register 8
The corresponding valid bit 84- in the address of 8-I
Clear I. Therefore, invalidation determination circuit 1
Valid bit clear signal 171- from 65-I
Give I. Next, cases in which invalidation is necessary will be explained in detail.
First, the type of access (FUNC) taken from the invalidation activation bus 55 indicates a write access, and the access is performed from the other side. Then, invalidation is performed when any of the following conditions is met. (a) Bit 18 of address of register 87-I
-27 reads the invalidation directory 83-I, its contents and bits 0-17 of the address
are compared by the comparator 163-I, and when they match. (b) When the parity checker 164-I detects a parity error when reading the invalidation directory 83-I. (c) Invalidate directory 83-I to JOBP4
When used indoors. (Because it is not possible to check) The invalidation processing has been described above.Next, in the read access stage (1), addresses are written to the directory 82-I and the invalidation directory 83-I, and the valid bit register 84 is written. -I
Explain why it is necessary to set Figure 16 shows how each part is affected when a read access results in a cache miss and there is a conflict between cache invalidation processing when going to read the main memory 10 and when writing access to the main memory 10 is performed from another source. The time chart shows how it is used. Invalidation processing is indicated by diagonal lines, and for write accesses during transfer of the startup bus 55 and data bus 56 in time slots 1 and 3, respectively, the invalidation directory 83-I is checked in time slots 2 and 4. In the first half of time slots 3 and 5, the valid bit register 84-I is cleared and invalidated. On the other hand, the read access that resulted in a cache miss is accessed from the startup bus 55 in time slot 2.
Since the address is transferred to main memory 10
The order of access is after the write access during transfer on the activation bus 55 in time slot 1 and before the write access during transfer on the activation bus 55 in time slot 3. Therefore, in order to maintain consistency between the data in the cache and the main memory 10, write access must be performed at time slot 2 when checking the invalidation directory 83-I.
Disable the read access address that caused the cache error between directory 8 and 4.
The valid bit register 84-I must be set between time slots 3 and 5 to invalidate the valid bit register 84-I as a result of the check. The reason why these controls are necessary is that main memory 1
This is because multiple memory accesses are being processed simultaneously at 0. In this configuration example, address information is stored in two places,
In other words, since it is stored in the directory 82-I and the invalidation directory 83-I, only the invalidation directory 83-I is subject to the above restrictions, but if you have the directory in one place, of course the above restrictions apply. subject to restrictions. Next, the data cache 42 will be explained. FIG. 17 is a diagram showing an example of the configuration of the data cache 42, in which the invalidation processing circuit 180-
D is omitted because it is the same as the instruction cache 41. Note that the items in Figures 13 and 17 whose only difference is the suffix are equivalent. 13th
The instruction cache shown in the figure uses I for the suffix, and the data cache shown in FIG. 17 uses D for the suffix. The major difference from the instruction cache 41 is that it must support write access, and in order to shorten this write access time, a common bus sending buffer 8 is used.
9-D is provided, and when writing, virtual address 92 is provided.
-D, write data 95-D, control information 96-
By simply setting D to this buffer 89-D, a termination signal 93-D is returned to the E unit 44, and the E unit 44 is controlled so that it can perform the next process. Next, the operation of this data cache 42 will be explained. However, since the read access process is the same as that for the instruction cache 41, a description thereof will be omitted. (3) Write access (see Figure 18). When the activation signal 91-D comes from the E unit 44, the virtual address 92-D, write data 95-D, and control information 96-D (access type, access key, etc.) are set in the common bus sending buffer 89-D. Then, it returns a completion signal 93-D to the E unit 44. At this time, the directory 82-D and valid bit register 84-D are checked, and if the cache is being sent (signal 170-D is output), bit 18-D of the virtual address of the cache data section 81 is checked.
Data is written to the position indicated by 27. Data cache controller 162-D
A startup bus occupancy request 51 and a data bus occupancy request 52 are issued. If both occupancy requests are granted, gate 8
5-D is opened and the virtual address (VA), access type (FUNC), and access key (AKEY) are transferred to the startup bus 55, and write data is transferred to the data bus 56. When the end signal and return code are sent from the MCU 12 via the response bus 57, they are latched into the register 86-D. Then, the return code is checked, and if no error or page fault has occurred, the access is removed from the common bus sending buffer 89-D, and the process is terminated. On the other hand, if the condition A shown in FIG. 14B occurs, that is, a hard error occurs and retry is not over, the process jumps to the stage for retrying. In cases other than the above, the valid bit register 84-D is cleared with the address of the common bus sending buffer 89-D, and the occurrence of an error or page fault is reported to the E unit 44. Valid bit register 84-D
The reason for clearing is that, for example, in the case of a protection error, data in the cache data section 81-D that should not be written has already been written in the stage. It should be noted that the address activated by writing from the data cache 42 to the main memory 10 is also set from the activation bus 55 to the data cache register 87-D (included in the invalidation processing circuit 180-D); Since the data cache controller 162-D sends a signal 173-D to the invalidation processing circuit 180-D so as not to perform invalidation, the data cache controller 162-D sends a signal 173-D to the invalidation processing circuit 180-D. Since the instruction cache 41 does not perform write access, this signal 173-
There is no equivalent to D. As explained in detail above, according to the present invention,
There are multiple processors, at least one of which
It is possible to realize a data processing device in which each of the two processors has a cache memory that is accessed using virtual addresses, and the address translation device is shared by all the processors.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing the overall configuration of a data processing device to which the present invention is applied, FIG. 2 is a diagram showing an example of the configuration of the common bus in FIG. 1, and FIG. Figure 4 shows an example of how the common bus is used; Figure 5 shows how the common bus is controlled; Figure 6 shows the interlock signal. 7 is a diagram showing an example of the configuration of the occupancy control circuit, and FIGS. 8A to 8C are examples of the processing flow in the MCU and how the MCU handles multiple accesses. Figure 9 shows an example of the MCU configuration. Figures 10A and B show an example of the memory board configuration and the order of data return when reading 16 bytes. Figure 11 shows an address translation device using TLB, Figure 12 shows the flow of address translation, Figure 13 shows an example of the configuration of an instruction cache, and Figure 14 shows how to convert an address to the cache. Fig. 15 is an explanatory diagram of the processing flow during read access, Fig. 15 is an explanatory diagram of the processing flow of cache invalidation, Fig. 16 is a diagram showing an example of the usage timing of each part of the cache, and Fig. 17 is the configuration of the data cache. FIG. 18, a diagram showing an example, is an explanatory diagram of a write access processing flow. 10...Main storage device, 12...Memory access controller, 20...External storage device, 22...
File processor, 30... Input/output processor, 40... Job processor, 41... Instruction cache, 42... Data cache, 43...
I unit, 44...E unit, 50...common bus, 75...address conversion device.

Claims (1)

[Claims] 1. A main storage device for storing programs and data, an external storage device for storing programs and data to be stored in the main storage device, and a virtual storage device for the main storage device to execute instructions. at least one job processor that accesses memory using an address; a file processor that accesses memory using a virtual address to the main storage to input and output programs and data between the main storage and the external storage; The job processor is connected to the main storage device and has a memory access controller that is commonly used by each processor and includes an address translation device that translates virtual addresses into physical addresses, and the job processor is accessed using virtual addresses. The cache memory receives a virtual address when the file processor writes to the main memory, and if the file processor holds a data block corresponding to this virtual address, A data processing device including invalidation processing means for making a data block unusable. 2. The cache memory consists of a data section that holds a copy of a part of the main storage, a directory section that holds the virtual address on the main storage stored in the data section, and whether or not the virtual address is valid. a latch register that latches the virtual address sent from the file processor; and a comparison that compares the virtual address latched in the latch register with the virtual address held in the directory section. 2. A data processing device according to claim 1, further comprising means for clearing said valid display section in accordance with a comparison result. 3. The address translation device has means for determining whether or not the physical address corresponding to the virtual address exists on the main storage device, and communicating the result of this determination to the processor that issued the access request. The data processing device described. 4. The data processing device according to claim 1, wherein the job processor, file processor, and memory access controller are connected to a common bus. 5 The cache memory is connected to a common bus,
5. A data processing device as claimed in claim 4, adapted to receive virtual addresses on a common bus.