JP3061818B2 - Access monitor device for microprocessor - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to a micro memory having a built-in cache memory.
The present invention relates to an access monitor device connected to a processor.

[Conventional technology]

Cache memory (Cache Memo-rise: ACM Compu
As shown in ting Su-rveys, vol. 14, no3, 1982, pp. 473-530), in an information processing apparatus having a storage hierarchy, a main memory is decomposed in units of a block of a certain size. By copying a part of the block to the cache memory that can be accessed at high speed, when the data requested by the processor exists in the cache memory, the data is passed to the processor at a high speed so that the processor I have improved the access speed. The size of the block (hereinafter, block size) is generally a power of two.

The cache memory records a copy of data held by a block in the main memory (hereinafter, main memory block) and an address tag indicating a position where the block exists in the main memory. The data memory in the cache memory is a part for recording a copy of data held in the main memory block, and the tag memory is an address memory.
This is where the tags are recorded. A block corresponding to one address tag is a unit of mapping between the main memory and the cache memory.

When the cache memory receives a data access request from the processor, the cache memory determines whether the requested data exists in the cache memory by checking whether the address output by the processor exists in the tag memory. I do. As a result, if the requested data exists in the cache (hereinafter, hit), the data is passed from the data memory of the cache to the processor.
If the requested data does not exist in the cache (hereinafter, "miss hit"), the main memory block holding the data is accessed, and this data is passed to the processor and copied to the data memory of the cache. . At this time, the address value output by the processor is recorded in the corresponding tag memory, and the
Hit processing is completed.

The mapping method between the main memory block and the cache memory block includes a full associative method,
There are a set associative method and a direct map method. The full associative method is a method in which an arbitrary main storage block can be mapped to an arbitrary block in the cache memory. In the direct map method,
In this method, the block of the cache memory to be mapped by the address where the main storage block exists is uniquely determined. In the set associative method, the blocks of the cache memory are divided into several groups, and an arbitrary one of the blocks of the cache memory having the group number (set number) determined by the address where the main memory block exists. This is a method that can be mapped to blocks.

Thus, in a fully associative or set associative cache memory,
A cache that can be mapped to one main storage block
There are multiple blocks of memory. Therefore, inside the cache memory, the entry address is used to identify these blocks, and the data memory and the tag memory are used.
Accessing memory. It is considered that a processor having a cache memory has a terminal for outputting the entry address and the set address.

On the other hand, a device for monitoring memory access issued by the microprocessor has been developed for the purpose of supporting hardware and software development of the microprocessor. An example is an in-circuit emulator (ICE).

By monitoring the level of the hardware number at the microprocessor terminals, this device provides a means for all memory accesses issued by the microprocessor.
The address, data content, and type of access (fetch of instruction code, access of operand, read / write) are examined. Based on the information obtained by this operation, the hardware developer checks whether the hardware of the device using the microprocessor operates normally.

Also, by recording the sequence of memory access issued by the microprocessor, the instructions executed by the microprocessor can be checked. So, memory
By presenting an instruction sequence obtained based on an access sequence to a software developer, information on whether the software is operating normally is also provided.

In order to provide such development support, especially software development support, it is necessary to record all memory accesses issued by the microprocessor.

However, in a microprocessor having a built-in cache memory, if an access hits the built-in cache memory, the access content does not appear at the terminal (address bus or data bus) of the microprocessor. For this reason, it is impossible to express an access monitor device for performing the software development support as described above.

[Problems to be solved by the invention]

As described above, in a conventional microprocessor having a built-in cache memory, since all access contents do not appear in the microprocessor terminals (address bus and data bus), software development support is provided. Access monitor device cannot be expressed.

[Means for solving the problem]

The configuration of the access monitor device for a microprocessor according to the present invention includes a cache memory and an entry monitor.
An access monitor device connected to a microprocessor having an address output terminal. The access monitor device has an external tag memory and an external data memory accessed by an entry address, thereby enabling processor access to the microprocessor internal cache. Is characterized in that the address and data contents can be monitored for all of the above.

[Action]

The access monitor device uses a set address and an entry address output by the processor, and when a processor access causes a cache miss,
Update the contents of the external tag memory and external data memory with information appearing at the terminals of the processor;
When a processor access hits the cache, the external tag memory and the external data memory are accessed, and the access content is output to monitor the access content of all accesses performed by the processor.

〔Example〕

 Next, the present invention will be described with reference to the drawings.

FIG. 1 shows the configuration of an access monitor device according to one embodiment of the present invention, FIG. 2 shows the configuration of a cache memory with a built-in microprocessor used in this embodiment, and FIG. The figure which shows the content of the address which performs each is shown.

The addresses in FIG. 3 are, in order from the least significant bit, an in-block address 31, a set address 20, and an address tag 26.
Divided into The number of bits of these addresses depends on the block size and the number of sets.

First, the operation of the processor built-in cache memory (corresponding to 3 in FIG. 1) shown in FIG. 2 will be described.

When the instruction execution unit inside the microprocessor outputs the access address to the processor internal address bus and accesses the internal cache memory,
It is as follows.

First, the tag memory is accessed by the set address 20 in the access address, and the address tags 26 corresponding to the number of entries are output from the tag memory 11. Comparison section
16, the address tags 26 and the access
Compare with address tag 26 in address. As a result, when there is a matching tag, it is a cache hit, and the data requested by the instruction execution unit exists in the internal cache memory.

Therefore, the set address 20 in the access address
Then, the data memory 12 is accessed according to the entry address 21 output from the comparison unit and the data requested by the processor is passed to the instruction execution unit through the processor internal data bus 23.

At this time, the entry address 21 is set to the entry address output terminal 6 (FIG. 1), the set address
20 is output to the outside of the processor through the set address output terminal 1 (FIG. 1).

As a result of the comparison operation by the comparing unit 16, when none of the address tags 26 output from the tag memory 11 match the address tag 26 in the access address, it is a cache miss and the instruction The data requested by the execution unit does not exist in the internal cache memory.

At this time, the address of the entry to be replaced is output from the comparing unit 16 and the access address is output to the memory address bus 24 to access the main memory. As a result, the main memory outputs data requested by the processor to the memory data bus 25,
The built-in cache receives this data and passes it to the instruction execution unit.

Further, in the tag memory 11 and the data memory 12, the tag block 17 and the data block 18 designated by the entry address 21 output from the comparison unit 16 and the set address 20 in the access address are: Writing the address tag 26 in the access address and the contents of the main memory 14 (FIG. 1) completes the update of the cache memory contents at the time of a cache miss. At the time of a cache miss, the address of the entry to be replaced passes through the entry address output terminal, and the set address is the set address output terminal 6 (first address).
Output to the outside of the processor.

The built-in cache is of a write-through type. When the instruction execution unit 13 (FIG. 1) makes a write access, the access content is a memory address.
Output to bus 24 and memory data bus 25. When the built-in cache is updated by this write access, the entry address and the set address are set to the entry address output terminal 6 (FIG. 1) and the set address.
It is output to the outside of the processor through the address output terminal 1 (FIG. 1).

The access monitor device shown in FIG. 1 comprises a bus access monitor unit 15, an external tag memory 4, and an external data memory 5.

The bus access monitor section 15 is a conventional access monitor for a processor having no cache memory.
It has the same function as the monitor device. The external tag memory 4 and the external data memory 5 are
This is a part for the processor. These operations are as follows.

At the time of a processor internal cache miss, of the addresses of the blocks in the cache to be replaced,
The address of the entry is output to an entry address output terminal 6, and the set number is output to a set address output terminal 1. Therefore, the address at which the processor 2 accesses the main memory 14 and the contents of the main memory block obtained as a result of the operation are recorded in the blocks in the external tag memory 4 and the external data memory 5 indicated by these addresses. . The contents are simultaneously transferred to the access monitor unit 15 and used for monitoring processor access.

When the internal cache is updated by a write access issued by the instruction execution unit 13, the external tag memory 4 and the external data indicated by the addresses output to the entry address output terminal 6 and the set address output terminal 1 are output. A processor 2 in a block in the memory 5
Record the output address and data value. At this time, as in the case of a built-in cache miss, the data is transferred to the access monitor unit 15 and used for monitoring processor access.

By these operations, a copy of the contents of the tag memory 11 and the data memory 12 in the internal cache memory is held in the external tag memory 4 and the external data memory 5.

At the time of a cache hit, the address of the entry among the addresses of the blocks in the cache where the data requested by the processor 1 exists is the entry address output terminal.
16, the set number is output to the set address output terminal 2. The access monitor 6 receives these addresses and supplies them to the external tag memory 4 and the external data memory 5. The tags and data in the external tag memory 4 and the external data memory 5 indicated by these addresses are the same as the addresses and data performed by the processor 2. The address and data of the access performed by the processor 2 are output by the above-described method, and these are transferred to the monitor unit 15 and used for monitoring the processor access.

These operations make it possible to configure an access monitor device that monitors all accesses even in the microprocessor 2 having a built-in cache memory.

As described above, the gist of the present invention is to make the external tag memory and the external data memory wait for the same contents as the contents held by the tag memory and the data memory of the cache memory incorporated in the processor, Accessing these memories by the entry address supplied from the processor, the cache built into the processor,
By configuring an access monitor device that waits for the function of obtaining the same value as the tag and data output from the data memory and the tag memory from the external tag memory and the external data memory, the cache memory can be used. The purpose is to enable monitoring of all memory accesses even in a built-in microprocessor. Therefore, it is apparent that various embodiments exist in the present invention. For example, in the present embodiment, both the tag memory and the data memory are provided externally. However, a system in which only the tag memory or only the data memory is provided according to the purpose of the monitor is also included in the present invention. included.

〔The invention's effect〕

According to the present invention, an access monitor device that monitors all accesses can be configured even in a microprocessor having a built-in cache memory.

[Brief description of the drawings]

FIG. 1 is a diagram showing a configuration of an access monitor device according to one embodiment of the present invention, FIG. 2 is a diagram showing a configuration of a cache memory with a built-in microprocessor used in this embodiment,
FIG. 3 is a diagram showing the contents of an address output by the processor at the time of access. DESCRIPTION OF SYMBOLS 1 ... Access monitoring device, 2 ... Microprocessor, 3 ... Built-in cache memory, 4 ... External tag memory, 5 ... External data memory, 6 ... Entry address output terminal, 7 ... ... Set address output terminal, 11 ... Tag memory, 12 ... Data memory, 13 ...
... Instruction execution unit, 14 ... Main memory, 15 ... Bus access monitor unit, 16 ... Comparison unit, 17 ... Tag block, 18 ...
Data block, 20: Set address, 21: Entry address, 22: Processor internal address bus, 23: Processor internal data bus, 24: Memory, address bus, 25: Memory Data bus, 26
... address tag, 30 ... access address, 31 ...
... Address within the block.

──────────────────────────────────────────────────続 き Continuation of front page (56) References JP-A-62-130437 (JP, A) JP-A-1-199251 (JP, A) NEC Technical Report, Vol. 40, no. 10, 1987, p. 84-87 (58) Field surveyed (Int.Cl. ⁷ , DB name) G06F 11 / 28,12 / 08 JICST file

Claims (1)

(57) [Claims] An access monitor device having a built-in cache memory and connected to a microprocessor having a set address terminal and an entry address output terminal, and having an external tag memory and an external data memory accessed by an entry address. Thus, an access monitor device for a microprocessor, wherein the address and the data content can be monitored for all processor accesses to the microprocessor built-in cache.