JPH01288940A - Logical address cache control system - Google Patents

Abstract

PURPOSE:To make unnecessary held data invalid by making invalid the held copy data when the original data on a main memory corresponding to the copy data held on a cache are updated. CONSTITUTION:The physical address of the data given from a physical address input 11 is written into a physical address holding means 5 so as to correspond to the data. When it is written into the main memory, the writing physical address given from a writing physical address input 12 is compared with the physical address held in the means 5, when the data before the updating of the data on the main memory updated by the other access requiring source, which shares the main memory, are held in a data holding means 1, the data concerned is made invalid by an invalidating means 6. Thus, when the original data on the main memory are updated, the coincidence between the original data on the main memory and the copy data held in the cache can be secured.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a logical address cache control method, and in particular is capable of avoiding logical contradictions that occur in a system in which there are multiple access requesters sharing main memory. Logical Address Cache Control Method % Formula % (Prior Art) A cache holds a copy of data in main memory. Access to the copy data held in the cache is faster than access to the original data in the main memory. Therefore, the more the copy data held in the cache is accessed, that is, the higher the hit rate, the shorter the effective access time becomes, and the performance of the system improves.

The cache stores data addresses corresponding to the copy data in order to identify the copy data, but depending on the address it stores, it is divided into two types: a logical address cache that stores logical addresses, and a physical address cache that stores physical addresses. There is a method cache.

(Problems to be Solved by the Invention) Generally, access to main memory is performed using physical addresses, so a physical address cache is employed. However, in the physical address cache, data is searched using physical addresses, so address translation from logical addresses to physical addresses is required. Therefore, compared to a logical address cache that does not require address translation, access is delayed by the address translation time. Therefore, when faster access is required, a logical address cache is employed.

FIG. 4 is a diagram for explaining a conventional logical address cache system. In FIG. 4, numeral 1 is data holding means, 2 is logical address holding means, 3 is logical search means, 4 is writing means, 7 is logical address input, 8 is cache access data input/output, 9 is memory access control output,
10 is a memory access data input/output.

In FIG. 4, data obtained from cache access data input/output 8 or memory access data input/output 10 is stored in data holding means 1. Further, the logical address of the data given from the logical address person cuff is written into the logical address holding means 2 by the writing means 4 in correspondence with the data. When an access is made, first, the logical address of the data to be accessed given from the logical address person cuff is compared with the logical address held in the logical address holding means 2, and a copy of the data to be accessed is stored in the data holding means 1. Check to see if it is retained. If the copy data is held, the copy data is accessed; if the copy data is not held, the memory access means is activated from the memory access control output 9, and the data in the main memory is accessed. I do. The above operations are controlled by the logical search means 3.

In a cache, when data on the main memory is updated by another access request source that shares the main memory, a logical contradiction occurs where the copy data held in the cache differs from the corresponding original data on the main memory. As shown in FIG. 4, the conventional logical address cache does not have a mechanism for detecting the occurrence of this logical contradiction. For this reason,
For example, when writing to main memory such as I10 transfer is performed, all data held in the cache must be invalidated to avoid logical contradictions. Due to this invalidation, the hit rate of the cache decreases, resulting in a problem that the performance of the system decreases. Furthermore, in a multiprocessor system, when a processor of another system writes to the main memory, a logical contradiction occurs. In order to prevent this logical contradiction from occurring, for example, a logical address cache has been employed as an instruction cache that caches only code data that is never written.

The present invention provides a logical address cache control method that eliminates the need to invalidate all data held in the cache even when writing is performed to main memory, thereby improving the performance of a computer system. The purpose is to provide.

(Means for Solving the Problems) In the logical address cache control method of the present invention, a physical address holding means for holding a physical address of data corresponding to data, and a writing means in a logical address cache of the conventional method are provided. It has a means for controlling writing to the physical address holding means, and by monitoring the write physical address, the data holding means holds an unupdated copy of data updated by another access request source that shares the main memory. If so, it has an invalidation means for invalidating the copy data.

(effect) Next, the operation of the present invention will be explained with reference to the drawings.

FIG. 1 is a diagram showing the constituent elements of the present invention. In FIG. 1, the same reference numerals as in FIG. 4 indicate the same components as in FIG. 4. In FIG. 1, physical address holding means 5, write invalidation means 6, physical address power 11, and write physical address power 12 are added to FIG.

Data given from cache access data input/output 8 or memory access data input/output 10 is stored in data holding means 1. Further, the logical address of the data given from the logical address person cuff is written into the logical address holding means 2 by the writing means 4 in correspondence with the data. When an access is made, the logical address of the data to be accessed given from the logical address cuff is compared with the logical address held in the logical address holding means 2. Next, it is checked whether a copy of the data to be accessed is held in the data holding means 1.

If copy data is held in the data holding means 1, the copy data is accessed.

If the data holding means 1 does not hold the copy data, the memory access means is activated from the memory access control output 9 to access the data on the main memory. The above is a known operation of a conventional logical address cache, and is controlled by the logical search means 3.

In the logical address cache control system of the present invention, the physical address of the data given from the physical address manual 11 is further written in the physical address holding means 5 by the writing means 4 in correspondence with the data. When writing to the main memory is performed, the write physical address given from the write physical address manual 12 and the physical address held in the physical address holding means 5 are compared, and other access requests that share the main memory are It is checked whether the data holding means 1 holds the data before the update of the data on the main memory that was originally updated. If the data before update is held in the data holding means 1, the corresponding data is invalidated. Invalidation of data using this write physical address is controlled by write invalidation means 6. As a result, if the original data on the main memory corresponding to the copy data held in the cache is updated, the held copy data is always invalidated, so the original data on the main memory and the original data held in the cache are The consistency of copied data can be guaranteed.

(Example) Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 2 shows an embodiment of the present invention. Further, FIG. 3 shows an example of a system in which the embodiment operates.

In FIG. 2, 110 is a data memory, which corresponds to the data holding means 1 in FIG. do. Further, the logical search control section 130 has a logical address comparison section 131, an erasure data selection section 132, and a logical invalidation control section 133. 14
0 is a write control unit, which corresponds to the write means 4, and the write control unit 140 further includes a data register 141, a logical address register 142, and a physical address register 1.
Has 43. Reference numeral 150 denotes a physical address memory, which corresponds to a physical address holding means; 160, an invalidation control unit, which corresponds to the invalidation means 6; have.

Further, in FIG. 3, 100 is a logical address cache of this embodiment, 200 is a processor, 300 is an address conversion means, 400 is a memory access means, and 500 is a main memory.

As shown in FIG. 3, processor 200 is connected to logical address cache 100 of FIG. 2 by a logical address cache and cache access data input/output 8 for accessing data. Further, the physical address of the data to be accessed, which is required to access the original data on the main memory 500, is generated by the address conversion means 300 using the logical address of the data to be accessed as input. When a processor accesses copy data held on the logical address cache 100 with writing, or when the processor accesses the copy data held on the logical address cache 100,
When accessing data that is not held on 0, the generated physical address is input to the memory access means 400. In this case, the logical address cache 100 further activates the memory access means 400 from the memory access control output 9, and accesses the original data on the main memory 500. In order to access the original data on the main memory 500, the logical address cache 100 is connected to the memory access means 400 by a memory access data input/output 10.

Furthermore, by monitoring the write physical address, it is detected that the logical address cache 100 holds an unupdated copy of data updated by another access request source that shares the main memory, and In order to invalidate data, the physical address of the data to be accessed, generated by the address generation means 300, is input from the physical address input 11 to the logical address cache 100. Further, the write address to the main memory 500 is input from the write physical address input 12 to the logical address cache 100.

As shown in FIG. 2, in this embodiment, first, in the logical address comparing section 131, the logical address of the data to be accessed given to the logical address cuff is compared with the logical address held in the logical address memory 120. Ru.

The logical address memory 120 holds logical addresses of data corresponding to the data held in the data memory 110. As a result of the comparison, if the logical address of the data to be accessed is held in the logical address memory 120, that is, if a copy of the data to be accessed is held in the data memory 110, the data memory 110
Access is made to the copy data held in .

Further, when the access includes writing, the copy data held in the data memory 110 is updated, and at the same time, the memory access control unit 400 is activated from the memory access control output 9 to update the data on the main memory 500. . As a result of the comparison, if the logical address of the data to be accessed is not held in the logical address memory 120, that is, a copy of the data to be accessed is not held in the data memory 110, the memory access control output 9 is
The memory access control unit 400 is activated from the main memory 50.
Access data on 0. In this case, in order to further increase the cache hit rate,
The data accessed by this latest access is held in the data holding means 110. The area where data is held is selected in advance by the erasure data selection unit 132, but if there is no free space, the area where the least valid data is held is selected, and this least valid data is deleted from the cache. Ru. The data to be accessed is stored in the data register 141, the logical address of the data to be accessed given from the logical address manual 11 is stored in the logical address register 142, and the physical address of the data to be accessed given from the physical address manual 11 is stored in the physical address register 143. Hold. When the data to be accessed, the logical address of the data to be accessed, and the physical address of the data to be accessed are obtained by the write control unit 140, the data to be accessed, the logical address of the data to be accessed, and the physical address of the data to be accessed are obtained. are written into a set by the write control unit 140 into the data memory 110, the logical address memory 120, and the physical address memory 150, respectively.

The invalidation control unit 160 monitors the write physical address to the main memory 500. When writing is performed to the main memory 500, the physical address comparison unit 161 compares the write physical address given from the write physical address input 12 with the physical address held in the physical address memory 150. Physical address memory 15
Corresponding to the data held in the data memory 110, 0 holds the physical address of the data. As a result of the comparison, the write physical address is physical address memory 1.
It is held at 50. That is, when the data memory 110 holds an unupdated copy of data updated by another access request source that shares the main memory, the write control unit 140 is activated by the physical invalidation control unit 162, The corresponding copy data held in the data memory 110 is invalidated.

(Effects of the Invention) According to the present invention, when the original data on the main memory corresponding to the copy data held on the cache is updated, the held copy data is always invalidated. Therefore, it is possible to guarantee that the original data on the main memory and the held copy data match while maintaining the characteristic of the logical address cache that it has a faster access time than the physical address cache. This eliminates the need to invalidate the held data even when writing to the main memory, such as in U○ transfer, improves the cache hit rate. Additionally, in a multiprocessor system, a logical address cache can be obtained that can cache data that conventional logical address caches could not cache.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing the components of the present invention, FIG. 2 is a block diagram showing an embodiment of the present invention, FIG. 3 is a diagram showing the components of a system in which the embodiment operates, and FIG. FIG. 4 is a diagram showing the components of the conventional system. DESCRIPTION OF SYMBOLS 1... Data holding means, 2... Logical address holding means, i... Logical search means, 4... Writing means, 5
... Physical address holding means, 6... Invalidation means, 2
00. . . . Processor, 300 . . . Address conversion means, 400 . . . 6 Memory access means, 500 . . . Main memory.

Claims (1)

[Claims] a data holding means for holding data; a logical address holding means for holding a logical address of data corresponding to the data; a logical search means for searching the data using the logical address; and the data holding means and the logical address. In a logical address cache control system having a writing means for controlling writing to the holding means, a physical address holding means holding a physical address of data corresponding to the data, and a write means for the physical address holding means inside the writing means. In the case where the data holding means has means for controlling writing and holds in the data holding means unupdated copy data of data updated by another access request source that shares the main memory by monitoring the write physical address. A logical address cache control method characterized by having an invalidation means for invalidating the copy data.