JPH04191946A - Snoop cache memory control system - Google Patents

Abstract

PURPOSE:To improve the utilizing efficiency of a common bus by dynamically discriminating whether a cache memory having a same block is to be revised or invalidated based on an operating state of the block of a processor when a common data in other cache memory is rewritten. CONSTITUTION:A flag (access flag) 20 set when a processor accesses a block in a cache memory 13 once or over is provided in the unit of blocks. When its own access flag is set up to a point of time when a same block of other cache memory is rewritten, its own block is revised but when the access flag 20 is not set, its own block is invalidated and the consistency is maintained by giving information representing whether the block is revised or invalidated to the cache memory 13 being a revision request source. Thus, undesired revision of the common block is minimized in this way to improve the utilizing efficiency of the common bus 80.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a cache memory control method in a shared bus type multiprocessor 7 system, and in particular, to Coherence of storage contents between cache memories
The present invention relates to a snoop cache memory control method that effectively guarantees e).

[Conventional technology]

In a shared bus multiprocessor system in which a plurality of processors are connected to a shared memory via a shared bus, each element processor often has a cache memory. In this case, consistency in updating the storage contents between these cache memories becomes a problem. For this reason, in a shared bus type multiprocessor system, each cache memory monitors transactions on the shared bus, and updates of information in the cache memory are locally managed for each processor system to maintain the above consistency. A cache memory control method for ensuring such consistency is called a snub cache control method.

This Snoopy 1. Several control methods for cache memory management have been proposed and evaluated or attempted (for example, Cache Coh
erence Protocols:Evaluati
on tlsing a Multiprocesso
r SimulationModel'', James
Archibald, et al + aca + Trnasa
cLions on Computer System
s, 1986. November, Volume
4. Number4. pp. 273-298).

Even in the conventional snob cache memory control method (7)L), it is allowed for multiple cache memories to have copies of blocks that are mutually shared between cache memories (this is called a shared block). . On the other hand, when data in a shared block (this is called shared data) is rewritten, two methods are available: an invalidation method that invalidates the shared block in other cache memories, and an invalidation method that invalidates the shared block in other cache memories. Two methods have been proposed: an update method that updates the block to a new block;

However, neither method is effective for handling all types of shared data; the update method is advantageous when shared data is exchanged frequently between brokers; If the frequency of receiving and passing is low, the invalidation method may be advantageous.

Therefore, if the snoop canosh control method is fixed to either the invalidation method or the update method, it may be effective for passing certain types of data, but the efficiency may be poor for other data.

For this reason, it has been proposed to switch between the above two methods. This switching method involves using software to specify information on which control method to use, the invalidation method or the update method, for each fixed storage area in the cache memory called a page, rather than for the cache memory as a whole. A method has been proposed that switches to either method on a page-by-page basis according to specifications (for example, [Fine-Grained Parallel Execution Support Mechanism], Matsumoto, Information Processing Society of Japan, Information Processing Society of Japan Research Report J, 89-ARC-77). , July 13, 1989 14
(Japanese, pp. 91-98).

[Problem to be solved by the invention]

However, in the switching method described above, the data storage area is divided according to the characteristics of the shared data, and the user must specify whether to use the invalidation method or the update method, which is cumbersome.

Furthermore, even if you carefully consider in advance that the update method is fixedly set to the invalidation method for each page before the start of program execution, the frequency of passing shared data between processors (characteristics of shared data) Since the information may change dynamically, there is a problem that a statically or fixedly specified update method or invalidation method may not work effectively.

Therefore, the present invention provides a snoop cache memory control method that is efficient even in response to changes in the characteristics of shared data, by having hardware decide whether to update or invalidate a corresponding block. The purpose is to

[Means to solve the problem]

To solve the above-mentioned problems, the present invention provides that each cache memory of a plurality of element processors each having a cache memory and a processor is connected to the shared memory via a shared bus, and each cache memory handles transactions on the shared bus. In a snob-catch control method that monitors and manages information in a cache memory, when shared data in a cache memory is rewritten, another cache memory that has a block containing the same shared data updates the block. A means is provided for dynamically determining whether to update or invalidate based on the usage status of the block by the processor.

[Effect]

Cache memory information management, that is, switching judgment between an update method and an invalidation method is performed dynamically depending on the situation (frequency) in which a processor uses a block.

To be more specific, in an update-type snob cache, a block that is updated as a result of a change in cache memory being rewritten will not be updated until the same block is updated by another cache memory. If a block has never been accessed by a processor since then, it is unlikely that the processor will use that block again. Therefore, even if such a block is invalidated, it will not cause much problem in terms of efficiency, and overall efficiency will be better if it is re-registered in the cache memory when it becomes necessary to use it again.

As described above, the present invention is an update type snob cache memory control method, and a flag (access flag) is set for each block when a processor accesses a block in the cache memory once or more. If the own access flag is set by the time the same block is rewritten in the cache memory, the own block is updated, but if the access flag is not set, the own block is invalidated and the block is updated. The configuration is such that consistency is maintained by notifying the cache memory of the update request source of either the updated or invalidated information.

That is, the present invention is based on the idea of improving the efficiency of use of the shared bus by minimizing unnecessary updates of shared blocks.

〔Example〕

As shown in FIG. 2, the shared bus type cache memory control system as an embodiment of the present invention has a shared memory 50 and a plurality of element processors 6o to 70. has a snob cache memory 61 and a processor 62. Each of the cache memories 61 to 71 is connected to the shared memory 50 via a shared bus 80.

The shared bus 80 includes a shared address bus line 1 that transfers addresses common to the shared memory and cache memory, a shared data bus line 2 that transfers data in blocks, and a shared bus control line 3 that transfers read requests and write requests. , and a shared line 4 indicating that data is shared in order to maintain consistency between cache memories, and as shown in the figure, a shared memory 5o and each cache memory 61 to 7.
1 is connected.

Moreover, as shown in FIG. 3, the Snoo 7 according to the embodiment of the present invention
The address in the '-1-yash memory control method is the tag part 41. Index section 42. The block storage position in the shared memory 5° is specified by the tag section 41 and the index section 42, and the data in the block is specified by the offset 43.

Furthermore, the storage position of the block in the cache is specified by the index unit 42.

Each cache memory has the configuration shown in FIG.

In FIG. 1, the cache memory includes an address register 10. a buffer 17 connected to the output of the address register 10; a shared address register 14 in which an address for processing a request from the shared bus 80 is stored;
Address register 10 or shared address register 14
A hit determination unit 11 that determines a cache hit by comparing the value of 1 and a value of a tag memory lla (described later), a status memory 12 (described in detail later), a cache memory 13, data on the shared data bus line 2, and data in the cassonry memory 13. and a bidirectional buffer 19 for mutually exchanging data in the data register 15, a data register 15 for temporarily storing data to be read into the processor and data from the processor, and a cache control unit 16 for controlling the cache in an integrated manner. It is connected and configured as follows.

The access request line 5,
A shared bus control line 3' and a shared line 4 are connected as shown. Further, the shared data bus line 2 is connected to the cache memory 13 and the data register 15 via the bidirectional buffer 19, and the shared address bus line 1 is connected to the buffer 17 connected to the address register 10, and the shared address register 14 is connected to the buffer 17 connected to the address register 10. and is connected to the human judgment section 11.

The hit determination unit 11 includes a tag memory lla and a cache memory hit determination circuit.

The tag memory lla stores tag portions 41 (see FIG. 3) of addresses corresponding to each block stored in the catch memory 13.

The status memory 12 also includes an access flag 20 indicating that the processor has accessed the block once or more, a shared flag 21 indicating that the block is shared by another cache memory, and a shared flag 21 indicating that the block is shared by another cache memory; A valid flag 22 indicates that the block is valid, a dirty flag 23 indicates that the processor has written to the block, and an owner flag 24 indicates that the block is the owner. Determination of these flags and sectoring of values are performed by the cache control unit 16.

The dirty flag 23 is set to "1" when there is a write request from the processor, and is set to "0" when there is an update request for the block from another cache or when the block is evicted from the cache. The owner flag 24 is set to "1" when there is a write request from the processor or when the block is read from the shared memory, and when there is a request to update the block from another cache or when the block is evicted from the cache. Time “0”
” is set. Since the management of these flags is not directly related to the present invention, the following explanation will be omitted.

Requests for reading and writing data from Bromo and Sukara are notified to the cache control unit 16 through the access request line 5. Further, data read and write requests between other cache memories or the shared memory on the shared bus 80 and the cache control unit 16 are mutually performed through the shared bus control line 3.

The address for reading and writing data to the tag memory 11a5, status memory 12, and cache memory 13 of the hit determination unit 11 is determined by the address register 10 or the index unit 42 (third address register) of the shared address register 14.
(see figure).

The hit determination unit 11 determines whether a hit has occurred in the cache memory by checking the value of the tag memory lla specified by the index part of the address register 10 or the shared address register 14 and the tag part 41 of the address register 10 or the shared address register 14. The cache control unit sends a signal 30 indicating that the values match, and a signal 31 indicating that the valid flag 22 of the status memory 12 set in the index part of the address register 10 or the shared address register 14 is "1". This is done by checking 16. From now on, unless otherwise specified, the address for processing a request from the processor is set in the address register 10, and the address for processing a request from the shared bus 80 is set in the shared address register 14.
Assume that it is set to . Also, depending on the process, either register 10.14 is selected such as cache memory 13, status memory 12. It is assumed that addresses are supplied to each part of the hit determination section 11.

Note that the above-mentioned human judgment unit 11. Status memory 1
2. The cache control unit 16 and the like constitute a means of the present invention for dynamically determining whether to update or invalidate a corresponding block based on the usage status of the block.

Next, the operations of the cache memory and access flags performed in accordance with requests from the processor or the shared bus will be explained with reference to FIG.

The cache control unit 16 first determines whether the output request is a request from the processor or a shared bus (step 401).

If the request is from the processor, it is further determined whether the request is a read request or a write request (step 402). In the case of a read request, depending on the determination result of the read request, (1) the data requested to be cached by the read request from the processor is in the cache, or (2) the data requested to be cached by the read request from the processor is cached. The process branches to the case where the requested data is not in the cache (step 403).

If it is determined in step 402 that it is a write request,
Depending on the result of the write request, (3) if Bromo or Sukara cashes in on the write request, or (
4) Branch to the case where a cache miss occurs due to a write request from the processor (step 404).

11,1 Go',: 1 If it is determined in step 401 that the request is a request from the shared bus, it is further determined whether the request is an update request or a read request. (Step 405). If it is an update request, when the update request causes a cache hit (the requested block is in the cache), the process proceeds to (5) the case where an update registration request from the shared bus causes a cache hit (step 406). If it is a read request, when the read request causes a cache hit (the requested block is in the cache), the process proceeds to (6) When the read request from the shared bus causes a cache hit (step 407).
. Note that if a cache miss occurs in steps 406 and 407, nothing is done.

In this way, there are six main cases, but among these, case (5) is the main processing flow for selecting whether to invalidate or update the shared block in the kyanyu, and (5) )<(1) to (6) is a preprocessing flow for making the selection possible. These cases will be explained individually below.

(1) When a cache hit occurs due to a read request from the processor. Since the processor accessed the data, the access flag 20 of the status memory 12 specified by the address register 10 is set to "1", and the hit data is transferred from the cache memory 13. data register 15
(step 411.4.12).

(2) When a cache miss occurs due to a read request from the processor The order of explanation will be reversed, but for convenience, we will explain the steps in the middle.

The explanation will start from step 426. The corresponding block is read from the shared data bus line 2 by outputting the value of the address register 10 excluding the offset to the shared address bus line 1 and issuing a read request to the cache memory or shared memory to the shared bus control line 3. cache memory 13
(steps 426, 427, 428). Also, the tag part 41 of the address register 10 is set in the tag memory lla of the hit determination part 11, and the valid flag 22 is set to "1", but the shared flag 2
1 is set to ``1'' if the shared line 4 is 1 when reading a block from the shared bus 80, otherwise it is set to ``0'' (steps 430, 431, 432).
, 433, 434).

Here, processing is performed in response to the access request by the processor, and since the data requested by the processor is in the block written above, the access flag 20 of the status memory 12 specified by the address register 10 is set to "1'' and the above data is also set from the cache memory 13 to the data register 15 (steps 435, 436).

Note that when registering cache-missed data in the cache memory, if it is necessary to evict a block currently in the cache memory, the following process is performed before the above process (step 426). Note that whether to evict or overwrite the block is determined based on the dirty flag 23 for the block in the cache memory, and if the dirty flag 23 is "1", the block is evicted.

It is determined whether the block is to be evicted or overwritten, and if it is an evicted block, the tag part 41 of the address of the block to be evicted is read from the tag memory 11a of the hit determination unit 11, and the value is combined with the value of the index part 42 of the address register 10. is output to shared address bus line 1 (step 421
, 422, 423). Then, the block of the cache memory 13 is output to the shared data bus line 2, and a write request is sent to the shared memory via the shared bus control signal line 3 (
Steps 424, 425).

(3) If the cache is cached due to a write request from the processor, rewrite the data from the data register 15 to the cache memory 13 (step 441). It is also determined whether the aired flag of the status memory 12 specified by the address register IO is "1" (step 442). If the shared flag is "1", the cache memory 13 specified by the address register 10 is transferred to the shared address bus line 1 from the address register 10 excluding the offset.
block is output to the shared data bus line 2, and a shared block update request is sent to other cache memories via the shared bus control line 3 (steps 443 and 444).
). Furthermore, the shared line 4 is monitored, and if the shared line 4 becomes "1", the unaired flag 21 of the status memory 12 is set to "1", otherwise it is set to rOJ (steps 445, 446, 447). Also, since the access was made from Bromo Tusa, the access flag 20 is set to "1" (Stay 7' 44 a).

(4) When a cache miss occurs due to a write request from the processor Same processing as in (2) when a cache miss occurs due to a read request, except for setting data to the data register 15 and setting the access flag (steps 435□ 436) After performing this, the same process as in (3) when a cache hit is made with a write request is performed.

(5) Kya/Shuhi with an update request from the shared bus.

If so, it is determined whether the access flag 20 of the status memory 12 specified by the shared address register 14 is "1" (step 451). If the access flag 20 is "1", it is determined that the processor has accessed a block updated by another cache more than once, and the processor is updated. That is, the block on the shared data bus line 2 is taken into the cache memory 13, and the block on the shared data bus line 4 is taken into the cache memory 13.
is set to "1", and the access flag 20 is set to "0" in response to the update (step 452.4).
53). In addition, if the access flag 20 is "○J," the block that was updated as a result of the rewriting of the cache at a different location has never been accessed by the processor before the same block is updated by another cache. It is determined that there is no data, and the block is invalidated.In other words, no data is taken in, the shared line 4 is set to rOJ, and the valid flag 22 is set to rOJ.

(6) In the case of a read request from the shared bus If the requested block needs to be supplied to the shared bus, that is, if it is requested to multiple caches, it is necessary to specify the cache that supplies the block. . To make this identification, it is determined whether the owner flag 24 is "lJ" (step 461).
1”, blocks are supplied.

If the owner flag 24 is rlJ, the cache memory 1
3 and outputs the block onto the shared data bus line 2 (step 462). Also, the shared line 4 is set to "1" regardless of the owner flag 24 (step 463). The valid flag 22, shared flag 21, and access flag 20 of the status memory 12 retain their current states (step 464).

(7) If there is no response to the update request from the shared bus, do nothing.

〔Effect of the invention〕

As described above, according to the present invention, when shared data in another cache memory is rewritten, whether to IF or invalidate a cache memory that has the same block is determined based on the usage status of the block by the processor. Since the cache memory is dynamically determined and the cache memory is managed based on this determination, dependence due to changes in data characteristics is reduced, and shared bus usage efficiency can be improved.

[Brief explanation of the drawing]

Fig. 1 is a schematic diagram showing an embodiment of the cache memory configuration in Fig. 2, and Fig. 2 shows a shared bus type multiprocessor system to which the snub cache memory control method of the embodiment of the present invention is applied. FIG. 3 is a diagram showing an example of the address structure in FIG. 2, and FIG. 4 is a flowchart showing the system operation of this embodiment. 1 is a shared address bus line, 2 is a shared data bus line, 3 is a shared bus control line, 4 is a shared line, 10 is an address register, 11 is a hit determination section, 12 is a status memory, 13 is a cache memory, and 15 is data register, 1
6 is a cache control unit, 2o is an access flag, 21 is a shared flag, 22 is a valid flag, 23 is a dirty flag, and 24 is an owner flag. Patent applicant: Director of the Agency of Industrial Science and Technology Ken Sugiyu (1) 7° Kano 1
(2) Operation 70 of this embodiment from 7°0 set 14 - Figure 4 (Part 2) (5) Operation 71 of this embodiment from the shared space Figure 4 (Part 4 (6) A!7 no hits when requesting to read from shared host

Claims (1)

[Scope of Claims] In a system consisting of a plurality of element processors each having a cache memory and a processor, each cache memory is connected to the shared memory via a shared bus, and each cache memory monitors transactions on the shared bus and processes the relevant transactions. In the snoop cache control method that manages information in cache memory, when shared data in a cache memory is rewritten, other cache memories that have blocks containing the same shared data update or invalidate the corresponding block. What is claimed is: 1. A snoop cache memory control method, characterized in that the snoop cache memory control method is configured to dynamically update or invalidate a block by providing means for dynamically determining whether to update or invalidate the block based on the usage status of the block by a processor.