JP2791319B2 - Data processing device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention
The present invention relates to a data processing device having a cache memory. 2. Description of the Related Art Conventionally, microcomputers and the like have
No special instructions are provided to control the
I / O in the same address space as main memory using
I / O devices are accessed by accessing the control registers.
A memory-mapped I / O method for controlling is often used.
You. FIG. 1 shows an example of a memory mapped I / O system.
FIG. 1 is a block diagram of a system. On system bus 100
The connected main memory 2 and input / output control circuits 3 and 5
Controlled by the control unit 1. Main memory 2, input / output control circuit
Unique addresses are assigned to 3 and 5, respectively.
Control registers in input / output control circuits 3 and 5 by processor 1
Is rewritten, and the input / output devices 4 and 6 are controlled.
You. In addition, the input / output devices 4, 6 have changed their states.
At this time, the value of the status register in the input / output control circuits 3 and 5 is written.
Change. The processor 1 executes a main memo by a store instruction or the like.
When rewriting the contents in the file 2, the system bus 100
Write address of main memory 2, data to be written and
Output a write command. Also, by load instruction
When reading the contents in the main memory, the system bus 100
Output the read address of main memory 2 and the read command
Output from the main memory 2 to the system bus 100
Data is taken in as read data. I / O device 4
Is activated by the control register in the input / output control circuit 3.
This is when the start bit is turned on. For example, when executing a store instruction,
Address as the unique address of the control register.
The input / output device 4 is activated by executing the tor instruction.
You. On the other hand, in order to know the completion of the operation of the input / output device 4,
Status register in the input / output control circuit 3 by the load instruction
And the operation complete bit of this status register is turned off.
Check if it is The operation complete bit is on.
Would check the other bits in the status register
You can know the completion status such as normal end, abnormal end, etc.
You. As described above, the memory mapped I / O system is
If used, general instructions can be used without dedicated I / O instructions
Has the advantage that the I / O device can be controlled precisely.
You. [0006] On the other hand, the microprocessor
Microprocessor, etc. to improve the performance of the
Is provided with a buffer storage (cache memory).
This buffer storage and the above-mentioned memory-mapped I / O system
The following problems occur when adopting the method combining
You. This problem will be clarified with reference to FIG. FIG. 2 shows a memory mapped I / O system.
Block diagram showing an example of a system using buffer storage
It is. In FIG. 2, a processor 1 executes an instruction
A processor main body 10 and a buffer memory 11,
The buffer memory 11 is an address for referring to the main memory 2.
Data in the area indicated by the address and its address.
ing. Now, for instruction fetch, data read, etc.
Reference of data in the area on the main memory 2 by the processor body 10
When a write request occurs, first, the buffer memory 11 is checked.
The data in the area on the main memory 2 is buffered.
When stored in the buffer storage 11,
Sends the corresponding data to the processor body 10 and reads it
To end. However, the data in the area on the main memory 2 is
If not stored in the buffer memory 11, the system bus
Reading of the corresponding data from the main memory 2 via 100
And sends the read data to the processor body 10.
At the same time, it is stored in the buffer storage 11. Also, the data
At the time of writing, the writing output from the processor
The write data and write address are stored in the system bus 10
0 to the main memory 2 and the corresponding write data
Data is written to the main memory 2. At the same time, this book
The write data and write address are stored in the buffer memory 11.
Is also stored. [0009] The buffer memory 11 is smaller than the main memory 2 in memory.
Since the access speed is high, if the above control is performed,
Area on the main memory 2 from which data was read or written
Data is stored in the buffer memory 11,
When referencing data in the same area on the main memory 2
There is an advantage that access time can be reduced. However, in the input / output control circuit 3 or 5,
When referring to the status register, the following problems occur:
You. Now, the processor 1 checks the status register.
Program that waits for the operation of the input / output device 4 to complete.
Lines shall be performed. The processor body 10 has an input / output system.
When a request to refer to the status register in the control circuit 3 is made, the status
The value of the register is sent to the processor body 10 at the same time
It is also stored in the buffer storage 11. Processor body 10
Checks the completion bit in the status register and checks if it is on.
To the next program.
Repeat reading and checking the completion bit. But,
Buffer storage for the second and subsequent status register reads
11, the input / output device 4 is turned on.
Completion of output operation, status register in input / output control circuit 3
Processor 1 detects this even if the completion bit of
There is a problem that you can not get out. The control register and the status register are the same.
If they are assigned to different bits of the address, and
Are assigned to the same address.
The status register is accessed when reading.
If the configuration is such that
Is stored in the buffer memory 11
When the status register is read, the value of the control register is
There is a problem of being read. Next, a plurality of processors are used for load distribution.
Buffer in a multiprocessor system
Occurs in the transfer of messages between memory and processors
Explain the problem. For example, a message between two processors
Example of a system that performs processing while transferring data
Is shown in the block diagrams of FIG. 3 and FIG. FIG. 3 shows processors 1 and 7 and their respective processors.
Local memory 2 and 2 'dedicated to the processor and message
Block diagram of a system including a shared memory 8 for wireless communication
It is. Usually, each processor 1 or 7 has its own
Processing is performed using the local memory 2 or 2 'of the processor.
Request from processor 1 to processor 7
When performing the processing, the processor 1 executes the processing contents and data necessary for the processing.
Data to a predetermined area of the shared memory 8 and write
Interrupt the processor 7 Processor 7 generates an interrupt
In other words, the process requested to read the contents of the shared memory 8
I do. When the processing is completed, the processor 7
Write the result to the shared memory 8 to contact the
Interrupt the processor 1. After that, the processor 7
Continue the previous processing. Processor 1 includes processor 7
Processing result from shared memory 8 by interrupt from
Then, the processing is continued. Processor 1 is a processor
While the process requested to the server 7 is being executed, the local
Other processing can be performed using the memory 2. FIG. 4 shows two processors 1, 7 respectively.
Connected to a common system bus 100 and
It is a block diagram of the system shared. each
The processors access the main memory 2 independently of each other.
However, if one processor is accessing the main memory 2,
Access request of the other processor
Controlled. In this system, the
The message communication is performed using a specific area of the main memory 2.
The area for writing the message is a specific area in the main memory 2.
Except in certain respects, a scheme similar to the system shown in FIG.
Has been taken. In these two systems, each processor
General buffer storages 11 and 71 are provided in the servers 1 and 7.
For example, the processor 1 writes in the message communication area.
Buffering, the buffer storage of the processor 1
The value of 11 is updated at the same time as writing,
7, the same address value is stored in the buffer memory 71.
Processor 7 does not update the
Even if the message area is accessed
Is read and the message from processor 1 is read.
Is not received correctly. Therefore, the object of the present invention is to
This was done to solve the problem.
Improve performance of data processing devices with processors
Even if buffer storage is provided for
Access. SUMMARY OF THE INVENTION A machine having buffer storage is provided.
When an microprocessor is used, the level in the input / output control circuit is
The message area of the
Data may be lost due to specific factors such as devices other than
Changes in the data.
Data on storage means that are difficult for the microprocessor to detect
Data is not stored in the buffer memory.
If the microprocessor has access to the buffer storage,
Access to external storage means without
To get the latest data. An outline of a typical invention disclosed in the present application is as follows.
It is as follows. That is, execution of an instruction and generation of a logical address
Processor (10) that performs the
Memory manager that translates logical addresses to physical addresses
Management unit (9) and the above memory management
The bus (100) that receives the physical address from the unit and the memo
Circuit (82) and data read from the memory circuit.
Cache connected to the processor to store
Memory (11) and a control circuit (81, 1) connected to the bus.
3), wherein the control circuit is configured to control the
Receives a physical address from the memory management unit.
The memory with the physical address from the bus
When accessing the specified address of the circuit,
To the cache memory of the data read from the circuit
Is prohibited. Other objects and features of the present invention are as follows.
It will be clear from the examples. FIG. 5 to FIG. 10 show an embodiment of the present invention.
This will be described in detail with reference to FIG. FIG. 5 shows an embodiment of the present invention.
FIG. 6 is an overall system configuration diagram, and FIGS.
3 is a circuit diagram of each block. In FIG. 5, the microprocessor 1 (hereinafter referred to as microprocessor 1)
Lower MPU), memory management unit 9
(Hereinafter abbreviated as MMU), main memory 2, shared memory 8, input
Output control circuit 3, input / output device 4, system bus 100 and
And other microphones (not shown) connected to the system bus
(Hereinafter abbreviated as MPUX). The MPU 1 is a processor that executes instructions.
Main body 10, cache memory 11, cache memory system
Control circuit 13, read / write control circuit 14, and OR gate
And an address signal 116 and a data signal 1
22, read signal 125, write signal 124, PURG
E signal 126, ACK signal 128 and RMA signal 12
7 is connected to the MMU 9 and the data signal 12
2, read signal 125, write signal 124, ACK signal
128 and the RMA signal 127
00 is connected. Here, the operation of the ACK signal ends.
And the RMA signal is a cache memory.
This signal indicates whether writing to the memory 11 is possible. The MMU 9 supports a virtual storage system.
Address translation mechanism for address signals 116
Address conversion table that contains the
To a physical address, and via an address signal 129
Output to the system bus 100. Main memory 2 is the main memo
And a main control unit 21 and a main memory storage unit 22.
Signal 152, address signal 159, read signal 155,
The system is controlled by the write signal 154 and the ACK signal 158.
To be connected to the system bus 100 and perform processing by the MPU 1
Instructions and data. The shared memory 8 includes a shared memory control circuit 81
And a shared memory storage unit 82,
2, address signal 149, read signal 145, write signal
No. 144, ACK signal 148 and RMA signal 147
Therefore, it is connected to the system bus 100, and MPU1 and MP
Data for UX message communication and MPUX
Instructions and data for processing are stored. The input / output control circuit 3 includes a data signal 132,
Address signal 139, read signal 135, write signal 1
34, ACK signal 138 and RMA signal 137.
Connected to the system bus 100 via a signal 130
It controls the input / output device 4 and transfers input / output data. In the system bus 100, the AC
K signal 138, 148, 158 and RMA signal 13
7, 147 are each wired-ORed, and MMU 9,
Any of main memory 2, shared memory 8, or input / output control circuit 3
This turns on the ACK or RMA signal
And ACK signal 128 or RM input to MPU 1
The A signal 127 turns on. Conversely, all of the above devices
When the ACK signal or the RMA signal is turned off, the MPU
ACK signal 128 or RMA signal 12 input to 1
7 is off. In the above configuration, the power-on reset
Sometimes, signal 113 is turned on by processor body 10
And the cache memory is stored in the cache memory control circuit 13.
An instruction to clear the memory 11 is issued. Cache memory control
The circuit 13 turns on the signal 117 to turn on the cache memory.
11 is invalidated. When reading is performed, a processor
The address read by the main body 10 is an address signal 116.
And the signal 111 is turned on. Read or
When the signal 112 indicating the completion of writing is turned on,
The data on the signal 115 is read by the processor body 10.
Is taken in as the output data and sent to the address signal 116.
Output is stopped and the signal 111 is turned off and the read operation is performed.
To end. Further, when writing, the processor
The address to be written is determined by the
The data to be written is output to the
No. 110 is turned on. Read or write complete
When the signal 112 indicating that the
10 to address signal 116 and signal 115
Stop the output and turn off the signal 110 to start the write operation.
finish. Next, reading from the main memory 2 will be described.
Next, the relationship with the cache memory 11 will be described.
The cache memory 11 outputs the address signal 116.
Check if the address is retained
If so, the signal 121 is turned on. Reed / La
When the signal 111 is on and the signal 12
When 1 is on, read from the cache memory 11
Judgment is to be made, the signal 114 is turned on, and the processor
The body 10 is notified of the completion of reading. In parallel with this,
The cache memory control circuit 13 outputs the signal 111 and the signal
When the signal 121 is on, the signal 119 is turned on, and
Output data from the cache memory 11 to the signal 115
To do so. The processor body 10 takes this value.
And the reading is completed. On the other hand, data corresponding to the cache memory 11
When the data is not held, the signal 121 is turned off.
Become. When signal 111 is on and signal 121 is off
In this case, the read / write control circuit 14
Read signal 125 to read
I do. The address output from MPU1 is MMU9.
It is converted and sent to the system bus 100. Main memory control
The circuit 21 determines whether the address signal 159 and the read signal 155
From the main memory
The corresponding data is read from the section 22 and the data signal 15 is read.
2 is output. Read is completed
The main memory control circuit 21 turns on the ACK signal 158
And inform MPU1. The main memory control circuit 21 is RM
RMA signal 127 is off because it is not connected to A signal.
The ACK signal 128 is turned on. ACK signal 128
Is connected to the processor body 10 through the OR gate 15
And the completion of reading is notified. Also this
, The cache memory control circuit 13 turns off the signal 119
So that the data signal 122 and the signal 115 are connected.
Instructed to the cache memory 11, the read data is
The data is transferred to the processor body 10. Under this condition
ACK signal 128 is on and RMA signal 127 is off
At this time, the cache memory control circuit 13 outputs the signal 120
ON, turn on signal 118 to cache memory 11
Instructs to store the read data. Cash
Memory 11 erases one of the stored data
Then, the read data and its address are stored.
Thereafter, if there is a read request to this address,
The data stored in the cache memory 11 is read. Next, writing to the main memory 2 will be described.
Will be explained. When the signal 110 is turned on, the cache
The memory control circuit 13 turns off the signal 119 and sets the cache
The signal 115 and the signal 122 are connected to the
Instruct you to With this instruction, the write data is
The data is transferred to the stem bus 100. Read / write control times
The path 14 has a write signal 124 when the signal 110 is turned on.
On, instructs writing outside the processor,
The address on the address signal 116 is changed by the MMU 9.
It is sent to the system bus 100. Main memory control times
The path 21 includes an address signal 159 and a write signal 154.
Recognizes that a write request has been made by
Data signal 152 to the corresponding address.
The main memory storage unit 22 is controlled during
No. 158 is turned on. Thereby, the ACK signal 128
Is turned on, and the processor body 1
0 is notified of the end of writing. When writing, the cache memory 11
Indicates whether the data at the corresponding address is stored.
A check is performed, and the result is output to a signal 121.
ACK signal 128 is on, RMA signal 127 is off,
When the number 110 is turned on, the cache memory control
The circuit 13 indicates writing to the cache memory 11
However, when the signal 121 is on, the signal 118 is turned on.
And the signal 120 is turned off, and the already stored address is turned off.
Address and data only
And when signal 121 is off, signal 118
And the signal 120 are turned on, and the already stored data
Erase one of the data and store the write address and data
To do so. Next, in the memory mapped I / O system,
Control registers or status registers inside the input / output control circuit 3.
In the case of reading a register, the input / output control circuit 3
Request from the address signal 139 and the read signal 135.
When it knows, it outputs the read data to the data signal 132,
The ACK signal 138 and the RMA signal 137 are turned on. Faith
Signal 111 is on, ACK signal 128 and RMA signal 1
27 is ON, the cache memory control circuit 13
No. 118 is not turned on.
No writing is done. However, when the signal 121 is off,
Therefore, the signal 122 and the signal 115 are connected,
The read data is transferred to the processor main body 10.
You. The control register inside the input / output control circuit 3
I / O control when writing to data or status registers
Circuit 3 is an address signal 139 and a write signal 134
Knows the request, writes the value of data signal 132
Turn on the ACK signal 138 and RMA signal 137
I do. Signal 110 is on, ACK signal 128 and RM
When the A signal 127 is on, the cache memory control circuit
The input / output control circuit 13 does not turn on the signal 118.
3 Internal control register or status register addresses and
That data and data are written to the cache memory 11
There is no. A control register in the input / output control circuit 3 and
When reading or writing the status register or key,
Whether data is stored in the cache memory 11
Is checked, but no data is stored
Therefore, the signal 121 is turned off. Therefore, read
Sometimes they are always read from outside the processor. Therefore, the cache memory is buffer-stored.
Input / output in the memory map I / O system
Force control can be performed without contradiction. Next, reading from the shared memory 8 and
And writing will be described. The shared memory 8 is an MPU
1 and the message communication area between MPUX and MPUX
Instruction and data storage area.
MPU 1 accesses only the message communication area.
Seth is performed. The shared memory control circuit 81
When reading and writing from the communication area,
To turn on the RMA signal 147,
Same as control register and status register inside control circuit 3
The data in the message communication area is also cached by MPU1.
It is not stored in the memory 11. MPUX is also MP
If the configuration is the same as that of U1, the cache memory of MPUX
The data of the message communication area is not stored
No. On the other hand, it stores instructions and data for MPUX.
When reading or writing an area to
The control circuit 81 turns off the RMA signal 147,
UX writes the value of the area to its own cache memory
The same processing as in the main memory 2 in the MPU 1 can be performed.
Work. This control is performed in the shared memory control circuit 81.
The address belongs to the MPU1 area or the MUX area
Is realized by providing a circuit that determines whether
You. Therefore, in the multiprocessor system,
Even if a cache memory is provided as buffer storage,
Sage communication can be performed without contradiction. Here, a multiprocessor with two processors is used.
Although the example of the processor system was shown, three or more processors
It is easy to understand that the same effect can be obtained by
it can. Now, the main ones among the blocks in FIG.
Will be described with reference to FIGS. FIG. 6 is a circuit diagram of the cache memory 11.
, Associative memory 16, counter 17, AND gate 18
And a switch 19. The associative memory 16
Address, data, and valid bits.
When performing a check, it matches with the address signal 116.
Of the entry that stores the address
Output effective bits to signal 160 and signal 121, respectively
I do. If there is no matching address, signal 121 is off
To be. When the signal 117 is turned on, the associative
All valid bits of memory 16 are turned off and all
Invalidation of the memory is performed. On the other hand, the signal 118 is an associative memo.
If the signal 120 is off
If the address having the address corresponding to the address signal 116
Write the value of signal 115 in the data field of the
Turn on the valid bit of the entry. Signal 120 is on
In this case, the entry indicated by the counter 17 is
Write the value of dress signal 116 and signal 115 and enable
Turn on the bit. At this time, the output of the AND gate 18
Is turned on, and the value of the counter 17 is incremented by one. Sand
The counter 17 has already been stored in the associative memory 16.
To replace one of the existing data with a new one
Serves to indicate the entry to be rewritten. Switch
When the signal 119 is turned on, the signals 19 and 11
5 and connect signal 122 and signal 115 when off
This is a bidirectional switch. FIG. 7 shows that data is not held in the buffer memory.
Of the cache memory control circuit 13 having means for performing
FIG. 3 shows OR gates 51 and 53, AND gate 52,
54 and a latch 55, and the OR gate 51
A signal 117 for invalidating the cache memory 11;
The OR gate 53 and the AND gate 52
A signal 118 instructing writing to the flash memory 11,
A scan in the cache memory 11 is performed by the AND gate 54.
A signal 119 for controlling the switch 19 is generated. Ma
The latch 55 holds the value of the signal 121,
By writing the address and valid bit to 16
The value of the signal 121 is prevented from changing. FIG. 8 is a circuit diagram of the read / write control circuit 14.
FIG. 12 shows a delay circuit 56, AND gates 57 and 58, and
And a negation gate 59.
Until the dress is checked and the signal 121 is confirmed
During the period, the signal 121 is not referred to by the delay circuit 56.
To FIG. 9 shows an input / output control circuit 3 having a detecting means.
And a decoder 60, AND gates 63, 6
5, 66, OR gate 64, tristate buffer 6
8, open emitter buffers 61 and 62 and status
The decoder 60 comprises an address signal 1
39 is decoded, and the input / output control circuit 3 is selected.
And determine which register is selected.
judge. If the selected register is in a specific area
If the status register corresponds to the area, the RMA signal 137
Turn on. Open emitter buffer 61
Drives the RMA signal 137 and
The buffer 62 drives the ACK signal 138,
RMA signal 137 and ACK signal 138 are wired O
R, the open emitter buffers 61 and 62
drive. When writing to the status register 67,
The output of the AND gate 65 is turned on and writing is performed.
When reading the status register 67, AND
The output of the gate 66 is turned on, and the tristate
The output from the file 68 to the data signal 132 is performed. Condition
Each bit of the status register 67 corresponds to a signal from the input / output device 4.
Therefore, it changes on or off. FIG. 10 shows a shared memory control having a detecting means.
FIG. 28 is a circuit diagram of a circuit 81, including decoders 69 and 80,
Emitter buffers 86 and 87, OR gate 83, AN
It comprises a D gate 84 and a timing control circuit 85. Deco
The reader 69 determines whether the shared memory 8 has been selected.
Judgment and generation of an address to be sent to the shared memory storage unit 82
And the decoder 80 is selected in advance.
Specified area, that is, message communication area
Make a decision. RMA signal 147 is turned on if it is a specific area
To Open emitter buffers 86 and 87 are RM
Drive A signal 147 and ACK signal 148
U. The output of the AND gate 84 is turned on because the shared memory
Only when there is an access request to the memory 8. Ma
In addition, the timing control circuit 85
A control signal and an operation completion signal required for access are generated. According to the present embodiment, the cache memory 11
And a microprocessor including a cache memory control circuit 13.
Write data to the cache memory 11 in the
The RMA signal that inhibits
Input to the cache memory control circuit 13 in the
For example, information indicating a specific area is prohibited
It can be configured independently of the microprocessor 1
To provide a versatile microprocessor.
it can. By the way, in FIG.
Address conversion table used for a certain virtual storage system
From the MPU 1 by the memory mapped I / O method.
Access is possible. The value of the address signal 116 is
Address of the read signal 125 or the write signal
When the reset signal 124 is on, the address conversion is performed.
The address translation table is read or written
Will be Again, ACK signal 128 and RMA
The signal 127 is turned on. In the case of writing, a PURGE signal
No. 126 is turned on. Cache memory control circuit 1
3 receives the PURGE signal 126 and turns off the signal 117.
And invalidate all of the cache memory 11. By this invalidation, the cache memory 1
1 and the physical address on the actual memory.
To prevent the correspondence with the dress data from being lost.
Can be. For example, data at logical address 100
Is stored in the cache memory 11. this
When data is read, the physical address is
Address conversion for the address corresponding to dress 1000
Rewritten table to correspond to address 500
If the processor reads address 100, the cache
Data of the physical address 1000 in the flash memory 11
Data is read, causing inconsistency. I prevented this
Therefore, if the address translation table is rewritten,
Issue a PURGE signal to invalidate the cache memory 11
Become As is clear from the above description, the present invention
According to the specific area where the memory content changes depending on the specific factor
The processor accesses the storage means containing the
If the access is to a specific area, the data is buffered.
Access by prohibiting the
The inconsistency does not occur in the data.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram of a conventional memory-mapped I / O system. FIG. 2 is a block diagram of a conventional memory-mapped I / O system. FIG. 3 is a block diagram of a conventional multiprocessor system having a shared memory. FIG. 4 is a block diagram of a conventional multiprocessor system having a shared memory. FIG. 5 is an overall system configuration diagram showing one embodiment of the present invention. FIG. 6 is a circuit diagram of the cache memory shown in FIG. 5; FIG. 7 is a circuit diagram of the cache memory control circuit shown in FIG. 8 is a circuit diagram of the read / write control circuit shown in FIG. 9 is a circuit diagram of the input / output control circuit shown in FIG. 10 is a circuit diagram of the shared memory control circuit shown in FIG. [Explanation of reference numerals] 1,7 ... Microprocessor (MPU, MPUX),
2, 2 'main memory, 3 input / output control circuit, 4 input / output device, 8 shared memory, 9 memory management unit (MMU), 10 processor body, 11 cache memory, 13 cache memory control Circuit, 14 read / write control circuit, 21 main memory control circuit, 22
... Main memory storage unit, 81 ... Shared memory control circuit, 82 ...
Shared memory storage unit, 100... System bus, 127, 1
37, 147... RMA signal, 128, 138, 148,
158: ACK signal, 116, 129, 139, 14
9, 159... Address signals, 122, 132, 142,
152 data signal, 124, 134, 144, 154
... write signal, 125, 135, 145, 155 ... read signal, 126 ... PURGE signal.

────────────────────────────────────────────────── ─── Continuation of front page (56) References JP-A-58-48289 (JP, A) (58) Fields investigated (Int. Cl. ⁶ , DB name) G06F 12/08

Claims (1)

(57) [Claims] 1. Execute instructions and generate logical addressesProcessing circuit
When, the aboveProcessing circuitTo physical address of logical address received from
A memory management unit for converting Physical address from the above memory management unit
The bus to receive, A memory circuit; To store data read from the memory circuit
AboveProcessing circuitA cache memory connected to the A control circuit connected to the bus, The control circuit controls the memory money via the bus.
Received the physical address from the
A predetermined address of the memory circuit with the physical address from
Read from the above memory circuit when accessing the dress
Prohibited writing of the written data to the cache memory
A data processing device characterized by stopping. 2. The predetermined address of the memory circuit is a multiple
In the processor methodProcessing circuitMessage communication area between
Claim 1 characterized in that it is a region
Data processing equipment. 3. The memory circuit is a multi-processor system.
Processing circuitPatent that is shared memory between
The data processing device according to claim 1. 4. The control circuit is configured to control the memory management unit.
Receives the physical address from the
Thus, the predetermined address of the memory circuit is accessed.
Control signal generation circuit for generating a control signal indicating that
And in response to the control signal,
A cache memory control circuit that inhibits data writing and
Claim 1 characterized by the following.
On-board data processing device. 5. Having an input / output control circuit connected to the bus
Data processing according to claim 1, characterized in that:
apparatus.