JPH0320834A - Initial diagnostic method for information processor - Google Patents

Abstract

PURPOSE:To prevent multiple bus errors from occurring by performing the diagnosis of a main memory device by storing control data for the execution of initial diagnosis transiently in a cache memory which is loaded on the same substrate with a processor and for which the diagnosis is completed in advance. CONSTITUTION:When the processor 11 performs the initial diagnosis for the start of a system, the control data for the execution of the initial diagnosis is stored transiently in the cache memory 14 loaded on the same substrate with the processor 11, and executes the diagnosis of a main memory device 3. After that the main memory device 3 is judged as normal, the control data is transferred to the main memory device 3, and the diagnosis of another input/ output device is executed. In such a manner, multiple system bus errors can be prevented from occurring, and high functional diagnosis can be applied on the main memory device 3.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to an initial diagnosis method for an information processing device, which diagnoses whether the functions of each part of the device are normal or not when starting up the system of the information processing device. (Prior Art) Figure 2 shows a block diagram of a conventional general information processing device. In the figure, this device has a main memory device (MEM) 3 and an input/output device (I/O) 4 connected to a central processing unit (PU) 1 via a system bus 2. A system bus controller (SPC) 5 is connected in order to control the bus rights of No. 2.

In the input/output device 4, for example, each communication line (CC) is
44, a magnetic disk device (DK) 45, and a floppy disk device (FD) 46 are connected. Information processing devices such as those described above are generally divided into separate boards for specific functional units in order to facilitate expansion in response to requests for increased memory capacity.

FIG. 3 shows a perspective view of the board configuration of such a conventional information processing device.

As shown in the figure, this device includes the central processing unit 1 shown in FIG.
It is divided into a central processing unit board IB on which is mounted a main memory device board 3B on which a main memory device 3 is mounted, and three input/output boards 4B on which various input/output devices are mounted. All of these boards are plug-connected to the system bus port 2B via connectors (not shown) or the like. The system bus port 2B has the system bus 2 shown in FIG.
is installed. In this way, the division of each functional block becomes clear, and it is easy to add more memory boards, for example.

Now, when starting up a system of this type of information processing apparatus, initial diagnosis is required to check whether each part of the apparatus operates normally and whether each board is securely installed.

A conventional initial diagnosis method will be explained using FIGS. 4 to 6.

FIG. 4 is a block diagram of an information processing device when performing initial diagnosis using a conventional method.

In the central processing unit 1, for the processor 11,
Read-only memory (RO
M) 13, cache memory 14, and input/output port l
5 is connected.

The processor 11 is composed of a microprocessor or the like that controls the entire system, and the read-only memory 13 is a memory that stores an operating program for the processor 11. Incidentally, this read-only memory 13 stores an initial diagnosis program 13a, etc., which is executed when starting up the system of this device. In order to speed up the memory access operation of the processor 11, the cache memory 14 receives data from the main storage device 3 etc. connected to the system bus 2 via the input/output port 15.
Random access data that receives some transfer of its data
Consists of memory, etc.

FIG. 5 shows an address space for initial diagnosis when, for example, a Motorola MC68020 microprocessor is used as the processor 11. This address space 200 has an IPL space 201 placed at the beginning, followed by a main memory (MEM) space 202, an input/output device (I/O
) space 203, read-only memory (ROM) space 204, cache memory space 205, and the like.

When the IPL space 201 is reset, a part of the read-only memory l3 shown in FIG. I'm trying to get it out.

In addition, at the start of the initial diagnostic operation, as shown in FIG. In the middle, a vector base register 113 pointing to the access point in the address space shown in FIG. 5 is set. Further, the read-only memory l3 stores an initial diagnosis program 13a and an interrupt vector table 13b. This interrupt vector table 13b consists of address conversion table data for determining the interrupt destination address when an interrupt occurs during program execution.

FIG. 6 is a conventional initial diagnosis flowchart.

First, when the device is powered on and the processor 1l shown in FIG. 4 is reset, the vector base register 113 inside the processor 11 is initialized to "O" and the fifth
Address "O" in the address space shown in the figure is accessed (as indicated by the arrow in FIG. 5). As a result, the value of the program counter and the value of the interrupt stack pointer are read out and set in the program counter 111 and interrupt stack pointer 112 inside the processor l1 (step Sl in FIG. 6).

When the initial diagnosis program is started in this way, as shown in FIG.
As shown in FIG. 2, the start address of the interrupt vector table in the read-only memory space 204 is used as an access point.

Next, a hash check of the read-only memory l3 in FIG. 4 is performed (step S2 in FIG. 6). The initial diagnosis program 13a is written inside the read-only memory l3, and if this read-only memory 13 cannot be read correctly, any subsequent diagnosis will be useless. It is. Note that hash check refers to read-only memory 1
The data in the read-only memory 13 are sequentially read out, the values are added, and the results are compared with the calculation results stored in advance in the read-only memory 13 to confirm the normality of the read-out of the read-only memory 13. It is a method.

If the read-only memory 13 is determined to be normal by this hash check, the vector base register 113 moves the access point to the arrow ■ in FIG. Set the control data 3a on the storage device 3 (step S3 in FIG. 6)
. A stack area 31, a work area 32, an interrupt vector table 33, and a vector base register 34 are set in this control data 3a. Stack area 3
1 and the work area 32 are areas for temporarily storing various data and parameters during execution of the diagnostic program.

In addition, the vector base register 34 includes the processor 1
Vector base register 11 set in 1
Move the value of 3 (step S4 in Figure 6). In the above state, the processor l1 reads the initial diagnosis program from the read-only memory 13, uses the control data 3a set on the main storage device 3, and performs a function check of the cache memory 14 (step 6 in FIG. S5),
Diagnosis of the main storage device 3 (step S6 in FIG. 6), implementation diagnosis of the input/output device 4 (step S7 in FIG. 6), etc. are executed. The function check of the cache memory 14 includes a diagnosis of the cache memory 14 itself and an operation diagnosis of the peripheral circuit for controlling the cache memory. Diagnosis of the main memory device 3 is based on determining whether data is written to and read from the main memory device 3 normally. In this case, the cache memory 14 that has already been diagnosed is utilized. The implementation diagnosis of the input/output device 4 is performed by issuing a predetermined command to the input/output device 3 and checking whether there is a proper response.

When these initial diagnoses are completed and it is determined that the functions of each part are normal, the IPL shown in FIG. , starts loading the system program, etc. (step S8 in FIG. 6).

As described above, in conventional information processing devices, the initial diagnostic program executed after power-on is stored inside the read-only memory l3, and is first stored in a very limited area on the central processing unit board. From there, we proceed with diagnosis while gradually expanding the scope while confirming its normality.

When control data such as a stack area and a work area are set on the main storage device 3, the processor 11 can execute a complex diagnostic program on the main storage device 3 using interrupts and subroutines. Become. (Problem to be Solved by the Invention) In the conventional method as described above, first, the processor 11 stores a stack area and a work area on the main storage device 3 via the system bus 2 in order to execute an initial diagnosis. Control data 3a including the following information is set. On the other hand, for example, Motorola's MC68020 microphone
When a failure occurs in the main storage device 3 or the system bus 2 and a bus error is notified, the 7' processor changes the register values of the processor 1l so that it can return to its original state after processing the bus error. It is saved to the stack area 31 on the main storage device 3.

However, if the failure in the main storage device 3 or the system bus 2 is permanent, a bus error will occur again. This state is called a multiple bus error, but when the processor recognizes a multiple bus error, it becomes a fault state.
Program execution is halted. Therefore, when a multiple bus error occurs, the processor cannot operate at all, making it impossible to recognize the details of the failure and to notify or display it to the outside. In particular, as shown in Fig. 3, when each part of the information processing device is separated by a board and connected to each other via the system bus board 2B, the system bus due to poor connection etc. Errors are relatively easy to occur. On the other hand, if you create a program that can diagnose the main memory device 3 without setting a work area or stack area, the above problem can be solved. However, this makes the diagnostic program complicated and makes it difficult to create a highly functional memory diagnostic program.

The present invention has been made with attention to the above points, and enables diagnosis to be performed without any trouble even when the main memory device or system bus does not operate at all, and furthermore, enables highly functional diagnosis of the main memory device. It is an object of the present invention to provide a method for initial diagnosis of an information processing device that can be performed.

(Means for Solving the Problems) An initial diagnosis method for an information processing device according to the present invention includes a main storage device and other input/output devices connected to a board on which a processor is mounted via a system bus. When the processor performs an initial diagnosis for system startup, the processor temporarily stores control data for executing the initial diagnosis in a cache memory mounted on the same board as the processor, and stores the control data for executing the initial diagnosis in the main memory. After the device is diagnosed and the main storage device is diagnosed as normal, the control data is transferred to the main storage device and the other input/output device is diagnosed. .

(Operation) In the above method, first, side control data is temporarily stored in a cache memory mounted on the same board as the processor in order to perform an initial diagnosis. That is, a stack area, a work area, etc. are created on the cache memory. Cache memory mounted on the same board as the processor is much more reliable than main memory connected via a system bus, and the cache memory itself has a small capacity, so it can be easily programmed. Diagnosis is possible. In this state, the main storage device is diagnosed, and if the main storage device is diagnosed as normal, the control data is transferred to the main storage device. This is to use the cache memory in its normal state and speed up the diagnostic processing when the processor accesses the input/output device. As described above, a highly functional diagnosis of the main memory device is possible, and after the control data is transferred to the main memory device, the conventional diagnosis is executed.

(Example) Hereinafter, the present invention will be explained in detail using embodiments shown in the drawings.

FIG. 1 is a block diagram of an information processing device that implements the initial diagnosis method of the present invention.

In the figure, a main storage device 3 and a human output device 4 are connected to a central processing unit 1 via a system bus 2. As explained in FIG. 4, the central processing unit 1 has a processor 11, a read-only memory (ROM) 13, a cache memory 14, and an input/output port 15 connected to an internal bus 12. It is a composition. Further, the input/output device 4 is composed of various input/output devices such as a magnetic disk device and a floppy disk device, as explained in FIG. 2. Note that the configuration of this input/output device 4 is substantially the same as that shown in FIG. 2, so a redundant explanation thereof will be omitted.

Here, in carrying out the method of the present invention, the following data is set in each block of the above device.

First, the processor l1 has a program counter 111.
, interrupt stack pointer 112, and vector base register 113 are set. Also, lead, talent,
An initial diagnosis program 13a and an interrupt vector table 13b are stored in the memory 13 in advance.

Furthermore, in the method of the present invention, the cache memory 14
An area for storing the control data 14a is set inside, and a stack area 141, a work area 142, an interrupt vector table 143, and a vector base register 144 are set there.

This control data 14a is set in the cache memory 14 at least when the main storage device 3 is diagnosed, and is transferred to the main storage device 3 after the diagnosis of the main storage device 3 is completed. That is, the main storage device 3 is provided with an area 3a for storing control data to be transferred, and a stack area 3 is provided here.
1. Set the work area 32, interrupt vector table 33, and vector base register 34.

FIG. 7 shows the address space for initial diagnosis of the present invention. As shown in the figure, in the method of the present invention, first, an IPL space 201 is placed at the beginning of the address space 200, as in the prior art.
Following this, a main memory space 202, an input/output device space 203, a read/control memory space 204, and a cache memory space 205 are set.

FIG. 8 shows a flowchart of the initial diagnosis method of the present invention.

The method of the present invention will be explained step by step using this flowchart.

First, the power of the information processing device shown in FIG. 1 is turned on,
When the device reset is completed, the access pointer of the vector base register 113 is initialized to “O” (7th
1), the processor 11 shown in FIG. 1 reads the value of the program counter and the value of the interrupt stack pointer from address "O" of the address space 200 shown in FIG. These are set in the program counter 111 and interrupt stack pointer 112 shown in FIG.
Figure step S1). Furthermore, at the start of the initial diagnostic program execution, the access point of the vector base register 113 is changed to the start address of the interrupt vector table 204a in the read-only memory space 204, as indicated by the arrow ■. When the diagnostic program is started, first, a hash check of the read-only memory 13 shown in FIG. 1 is executed (step S2 in FIG. 8). The contents of the hash check are as already explained in the prior art.

Next, in the method of the present invention, the cache memory l4 shown in FIG. 1 is diagnosed. The cache memory 14 consists of a small capacity random access memory, and its diagnosis can be completed by relatively simple data writing and reading operations.

In this case, it is only necessary to diagnose the minimum area necessary for setting the control data 14a, and checking the cache function itself including the peripheral cache memory control circuit etc. would be complicated, so it is not performed at this stage. .

If the cache memory 14 is determined to be normal,
A stack area 141 in this cache memory 14
, the work area 142 is secured, and the interrupt vector table 14 read from the read storage memory l3 is
Store a. Also, the vector base register 113 set in the processor 11 is read out, and the vector base register 144 is set in the cache memory 14 (steps S4 and S5 in FIG. 8). The processing up to now is as shown in FIG.
This is a diagnosis of resources on the same board on which 1 is mounted, the number of parts is small, there is no intervening connector, etc., and the probability of failure occurring is low. Therefore, in the conventional diagnostic operation,
It is considered that multiple bus errors occur extremely rarely. Through the above processing, the control data 14 is secured in the cache memory 14, which is used for the operation of a complex program that can diagnose each part of the information processing apparatus using interrupts and subroutines. Therefore, in this state, in the same way as when control data is set in the main memory,
Diagnosis of each part of the device becomes possible.

In the method of the present invention, the main storage device 3 is then diagnosed (step S6 in FIG. 8). During this main memory diagnostic,
Even if there is an abnormality in the system bus 2 or main storage device 3, bus error interrupt processing is executed using the vector table 143 and stack area 141 of the cache memory 14. Therefore, the operation stoppage or the like due to multiple bus errors as in the conventional case does not occur.

When the diagnosis of the main storage device 3 is successfully completed, the system bus 2 and the main storage device 3 are diagnosed as being healthy. Next, the control data 14a previously temporarily stored in the cache memory 14 is transferred as is to the main storage device 3 (steps S7 and S8 in FIG. 8).

Furthermore, the control data 1 set in the cache memory l4
4a can be used to diagnose not only the main storage device 3 but also the input/output devices 4 and the like connected to the system bus 2. However, in the present invention, in order to ensure high-speed diagnosis, etc., after the diagnosis of the main storage device 3 is completed, control data is set in the main storage device 3 as in the conventional case. Next, we will diagnose the cache function (
FIG. 8 step S9).

Normally, the main memory device 3 and the input/output device 4 are
1 makes an access, a part of the data to be accessed is temporarily transferred to the cache memory 14 to speed up the access. It is desirable to speed up such access even in the initial diagnostic operation. Therefore, after the diagnosis of the main storage device 3 and the function diagnosis of the cache memory 14, the cache memory is made to function normally and is utilized.

Additionally, most of the conventional diagnostic programs can be used as is. After the control data 3a is set in the main storage device 3, implementation diagnosis of the input/output device 4 is performed (step SIO in FIG. 8).
), the process moves to IPL reading (step Sll). Note that, for diagnosing the main storage device 3, it is also possible to utilize memory other than the cache memory mounted on the same board as the processor 11.

However, storing control data for complex diagnostic programs requires a memory element with a certain bit width and a certain capacity. Therefore, normally, registers other than cache memory do not satisfy this condition. Furthermore, mounting a dedicated memory on the board for this purpose increases costs and increases the size of the board. Therefore, it can be said that using cache memory is the most effective. Next, an example in which the method of the present invention was implemented more specifically will be described.

FIG. 9 shows a block diagram of the substrate configuration of a central processing unit that implements the method of the present invention.

The processor 11 in the figure includes, for example, Motorola's MC6.
8020 microprocessor is used. A 32-bit wide logical address line 12a and a data bus 12b are connected to this processor 11.

The logical address line 12a is connected to the memory management unit 1l5 (
Motorola MC68851) and select section 118
It is wired to input to the In addition, the data bus 12
b is also connected to the memory management unit 115. A timer 116, a read-only memory (ROM) 13, an I/O register 120 in the PU, etc. are connected to this data bus 12b. An MMU address line 12d is provided to transmit the address signal output from the memory management unit 115, and is connected to be input to the select section 118 and buffers 119 and 120. The memory management unit 115 is a circuit that converts the logical address output from the processor 1l into a physical address and outputs the physical address toward the MMU address line 12d.

The selection unit 118 is a selection circuit that selects either a logical address or a physical address and outputs it to the physical address line 12c.

The decoder 117 is a circuit that decodes the physical address input from the physical address line 12c and outputs a signal for selecting various memory spaces. Also, MMU
The 13th to 25th bits of the address line 12d are connected to be input to the buffer 119, and the 2nd to 12th bits are connected to be input to the buffer 120. The buffer 7119 is connected to a tag address line 151 that transfers a tag address for cache control, and the buffer 120 is connected to a set address line 152 that transfers a set address for cache control.

The tag address line 151 is connected to the system bus 2C via a buffer 122, and the set address line 152 is also connected to the system bus 2 via a buffer 123. Further, the physical address line 12c is connected to the system bus 2 via a buffer 121. Note that the buffers 122 and 123 are connected to the cache memory 14.
It is provided to perform write invalidation processing to invalidate specified data inside. That is, when an input/output device (not shown) connected to the system bus 2 rewrites the contents of data in a main storage device (also not shown), if the data at the rewritten address is stored in the cache memory 14, then the Write invalid processing is required to prohibit the use of data. In this case, the addresses used for rewriting are temporarily stored in buffers 122 and 123, and predetermined processing is performed. In addition, the buffer +21 is used by the processor 11 to use the system bus 2.
This is used to temporarily store the physical address that is output when accessing the main storage device (not shown) through the . The cache memory 14 is composed of data array sections 140a and 140b with 82 sides.

In order to control writing of data to the cache memory 14, a cache control section 145, a comparator 146. 147 and a two-sided tag array section 148
a, 148b are provided. physical address line 12
c is connected to be input to tag array sections 148a and 148b via a buffer 127. The buffer 127 is used to provide an address for mapping the tag array sections 148a, 148b into the cache diagnosis space of the processor 11 when diagnosing the tag array sections 148a, 148b themselves. In addition, the tag address line 151 is connected to the buffer 1
31 and 132, and these outputs are connected to comparators 146, 147, tag array sections 148a, 148b, and puffs 7 128, 12, respectively.
It is wired to input to 9. Comparator 146, 1
In addition to the outputs of the buffers 131 and 132, the output of the tag address line 151 is directly connected to the line 47. The buffers 131 and 132 store the address of the tag array section 14 at the time of a cache mishit.
This is used to temporarily store the tag address for writing to 8a or 148b.

Note that the comparator 146. 147 are the tag addresses output from the tag array sections 148a and 148b, respectively;
This circuit compares the address with the address outputted to the tag address line 151 at that time, and if the two match, it notifies the cache control unit 145 of this fact.

In addition, the data array section 140a of the cache memory 14
, 140b are connected to the data path signal line 12e. Further, tag array sections 148a and 148b
The output of is connected to data bus 12b via buffers 128 and 129. As a result, the tag array section 148a, ! 48b, data output from the tag array section is recognized by the processor 11 via the data bus l'b.

The buffer 125 connects the data bus 12b and the data bus 12
The buffer 124 is used to separate the data path 12e from the system bus 2. In addition, the buffer 124 is configured such that when a cache hit occurs,
It functions to separate the system bus 2 and data bus 12e.

FIG. 10 shows the address space of the processor 11 shown in FIG. The address space shown on the left side of the figure is similar to that shown in FIG. 7, with an IPL space 201 located at the beginning, followed by a main storage space 202, an input/output device space 203, and an address space within the PU. 210 is set. This P
As shown on the right side of the U address space 210, P
I/O space 211 in U, read-only memory space 2
04 and cache memory space 205. In addition, as shown on the right side of the cache memory space 205,
A-side tag array space 205a and B-side tag array space 2
05b, an A-side data array space 205C, and a B-side data array space 205d. By setting such a diagnostic address space, the processor 11 shown in FIG. 9 stores the control data 14a described in FIG. 1 in either the data array section 140a or 140b of the cache memory 14. You can set the area that should be used.

In FIG. 9, when accessing the data array section 140a, when the processor 11 outputs a predetermined logical address to the memory management unit 115, the memory management unit 115 outputs the corresponding physical address as MM.
It is output to the U address line 12d and input to the data array section 140a via the buffer 120. Control data to be written to the data array section 140a is read from the read/write memory 13, etc., and is input to the data array section 140a via the data bus 12b and buffer 125. FIG. 11 shows the cache memory space entries of the processor shown in FIG. Figure (a) shows the cache tag entry on side A, and Figure (b) shows the cache tag entry on side B. Each entry has a 32-bit configuration, with the Oth bit to the 18th bit being the tag address, and the 19th bit being the least recently used bit L R
U (Least Recently Llsed)
Bit), the 20th bit is a valid bit V. The LRU of the 19th bit is data in which, in a cache tag entry that has two sides, the side that is most recently unused, that is, the side that has not been hit, becomes “O”, and is the data that will be “O” when evicted from the cache entry. Used to determine the target. Further, the 20th bit V is for indicating whether the cache tag is valid or invalid.

FIGS. 11(C) and (d) show side A cache data entries and side B cache data entries, respectively. All of these are 32-bit data. FIG. 11(e) shows the contents of the cache control register, and the “O” bit enable bit E is used.
Only. This enable bit E has the content “
When the flag is "I", the cache operation is valid, and when the flag is "O", it is the cache diagnostic mode.

If the board configuration of the central processing unit is selected as described above,
The processor 11 shown in FIG. 9 reads the diagnostic program from the read-only memory 13 and executes the read-only program.
Memory 13 hash check. cache memory 14
After performing the diagnosis, the control data is read from the read-only memory 13 and written into the cache memory 14 via the data bus 12, the buffer I 25, and the data bus 12e. After that, see Figure 7. The operations described in FIG. 8 and the like are executed.

However, since the amount of control data is extremely small, the data array section 140a or 140b of the cache memory 14 is
It is sufficient to use only one of them.

Therefore, the diagnosis of the cache memory l4 can be limited to the minimum area as described above. (Effects of the Invention) According to the above-described initial diagnosis method for an information processing device of the present invention, control data for executing the initial diagnosis is stored in the cache memory that is mounted on the same board as the processor and has undergone diagnosis in advance. Since the data is temporarily stored and the main memory is diagnosed, multiple bus errors are prevented from occurring, and the main memory can be diagnosed using a complex test program. In addition, if you later move the control data to main memory and run diagnostics on other input/output devices, you can use the same program as before to run a fast and efficient diagnostic program. Can be executed.

[Brief explanation of drawings]

FIG. 1 is a block diagram of an embodiment of an information processing device that implements the initial diagnosis method of the present invention, FIG. 2 is a block diagram of a general information processing device, and FIG. 3 is a perspective view showing the board configuration of the information processing device. 4 is a block diagram of an information processing device according to a conventional method, FIG. 5 is an explanatory diagram showing a conventional initial diagnosis address space, FIG. 6 is a conventional initial diagnosis flowchart, and FIG. 7 is an initial diagnosis address space of the present invention. 8 is an initial diagnosis flowchart of the present invention, FIG. 9 is a block diagram of the board configuration of a central processing unit implementing the method of the present invention, and FIG. 10 is an initial diagnosis address of the processor in FIG. 9. FIG. 11 is an explanatory diagram showing the space, and FIG. 11 is an explanatory diagram of the cache memory space entry of the processor in FIG. 1...Central processing unit, 2...System bus, 3...
・Main storage device, 3a, 14a...control data, 4...
- Input/output device, 11... Processor, 12... Internal bus, 13... Read only memory, 13a... Initial diagnosis program, 13b... Interrupt vector table, 14... Cache memory , 3 1, 141, ... stack area, 32, 1
42...Work area, 33,143...Interrupt vector table, 3 4
, 113, 144...vector base register,
Ill...Program counter, 112...Interrupt stack pointer. Conventional initial diagnosis address space Figure 5 Initial diagnosis address space of the present invention Figure 7 Conventional initial diagnosis flowchart Figure 6 Initial diagnosis flowchart of the present invention Figure 8

Claims (1)

[Claims] In a board on which a processor is mounted, a main storage device and other input/output devices are connected via a system bus, and the processor performs initial diagnosis for system startup. temporarily storing control data for executing the initial diagnosis in a cache memory mounted on the same board as the processor, executing a diagnosis of the main storage device, and diagnosing that the main storage device is normal. 1. An initial diagnosis method for an information processing apparatus, wherein the control data is transferred to the main storage device of the information processing apparatus after the information processing apparatus is processed.