JPS62184564A - Electronic computer control system - Google Patents

Abstract

PURPOSE:To reduce the activity ratio of a bus by selecting a required inseparable read/write signal out of signals outputted from a processor, and making perform a bus access. CONSTITUTION:When a reference to a storage device in which an inseparable readout/write signal 5 is at a level of 1 is generated, an address 7 and a data 8 at that time are stored at registers 28 and 29 respectively, and an FF22 is set at the level of 1. And at every reference to the storage device by a processor 1, an address is compared with the previous one stored at the register 28, and when they coincide with each other, a bus request signal 32 is set at a level of 0, thereby preventing a bus operation from being generated, and also, the data 8 at the register 29 is returned to the processor 1 as a result read out from the storage device. Meanwhile, by detecting a coincidence between the address signal 7 on a bus 2 and the address in the register 28 at a comparator 33, and detecting both that it is a write operation, and that it is not an inseparable signal by an AND gate 34, the FF22 is reset through an OR gate 21.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] This invention relates to a computer system in which a plurality of processing units share one storage device via a bus in a time-sharing manner. This paper relates to a control method for improving overall system performance.

``Prior Art'' There is an electronic computer system that uses multiple processing units to increase processing capacity. The most commonly used connection method for processing devices in this system is so-called bus connection. The bus coupling method is a method in which a bus is shared in a time-division manner to exchange shared data stored in a storage device and to communicate with each other. An important point for the performance of this system is to keep the bus usage rate low. That is, when reads and writes (hereinafter collectively referred to as accesses) are concentrated on a storage device, the bus becomes a bottleneck in the system, and the system performance is limited by the bus's capacity.

A cache memory method is a conventional method that has been confirmed to be effective in reducing bus accesses.

This has a memory dedicated to the processing device between the processing device and the bus, holds some of the data in the storage device in that memory, and if necessary data is held in this memory, it can be saved. The data is output to the processing device and controlled so that the bus is not used, thereby reducing the number of bus accesses.

On the other hand, software for a computer system that has multiple processing units has, for example, 1 byte of information for each resource in order to manage system-shared resources, and if the corresponding resource is in use, it will have 1 byte of information. If it is not, it stores '0'', and when a processing device wants to use that resource, it writes 'II I I+' after confirming that it is ``0''.Then, other processing devices can use that resource. Knowing that the resource is currently unavailable, perform some other processing that can be done without using that resource, or wait until the resource is freed. In other words, read that information over and over again until the resource is freed. The operation used is atomic read/write, and in the above example, confirm that it is ``0'', and make sure that other processors read ``0'' while writing ``1''. To avoid this, °°1 is read after °′0°”
The bus is controlled so that no other processing device is allowed to use it until `` is written.

Since atomic reads and writes occupy the bus for a longer time than normal bus use, it is necessary to minimize the number of times they occur. Even if data at a given address is in the cache memory, there is no guarantee that only that processing device has rewritten the data at that address unless control is taken to prevent bus access. In other words, even if cache memory is used, the bus usage rate will not decrease.

Further, as a method of suppressing bus usage during indivisible reading and writing, there is a method shown in Japanese Patent Laid-Open No. 58-163451 and Japanese Patent Laid-Open No. 58-214534.

This operates in such a way that if rewriting fails in an indivisible read/write operation, the processing device is stopped by the action of the microprogram, thereby avoiding the use of the bus.

"Problems to be Solved by the Invention" As described above, the cache memory method has the drawback that it is not possible to reduce the bus usage rate for atomic reading and writing.

Also, JP-A-58-163451 and JP-A-58-
No. 214534 The methods shown in each publication have the disadvantage that the processing device may stop during indivisible reading and writing, making it impossible to perform other processing, and because it depends on the internal workings of the processing device, it cannot be applied to existing microprocessors, etc. There was a drawback.

An object of the present invention is to provide an electronic computer control system that can reduce the bus usage rate by selecting only necessary reads and writes issued by a processing unit and causing bus access. It is in.

"Means for Solving the Problems" The electronic computer control method of the present invention includes a first means for storing an address at the time when an indivisible read/write operation is performed;
A second means for storing the data written at that time, a collation means for collating the address and the address stored by the first means when the next atomic read/write operation occurs, and the collation matches. If the data has been read from the storage device, the data stored by the second means is returned to the processing device, and the third means controls the bus so that it is not used, and monitors the write operation by the other processing device. monitoring means; and fourth means for controlling, when a write operation is performed to the address stored by the first means, no verification by the verification means until a new inseparable read/write is performed. Equipped with:

"Example" Next, the present invention will be explained with reference to the drawings.

In order to clearly show the characteristics of the operation of the embodiment of the present invention, the explanation will be made to show the difference between a case not based on the present invention and a case according to the present invention.

FIG. 1 partially shows an example of an electronic computer not according to the invention, and shows how a processing device 1 is connected to a bus 2. In FIG. In this example, when the processing device 1 uses the bus 2 to read/write to a storage device (not shown), it first sets the bus request signal line 3 to II II II.

Although not shown in FIG. 2, when the bus arbitration circuit receives this and determines that it can grant the right to use the bus 2 to the processing device 1, the bus approval signal 4 is shall be.

The processing device 1 receives this and sends an indivisible read/write signal 5 and a read/write signal 6 as information to the storage device.
, address signal 7, and data signal 8, respectively.

However, the data signal 8 is sent only when writing, and is received when reading. At this time, the buffer circuits 11, 12, and 13 are activated when the bus acknowledge signal 4 becomes ``1'', and operate so as to be able to send out the upstream signals 5, 6, and 7, respectively. In addition, the buffer circuits 14 and 15 are connected to the bus acknowledge signal 4 and the read/write signal 6 by the AND gate 16 so that one is activated depending on whether it is a read or a write.
and the output of the AND gate 16 is supplied to the buffer circuit 1.
4. The signal is supplied to the NOT gate 17, and the buffer circuit 15 is controlled by the output of the NOT gate 17. Further, the processing device 1 is provided with a signal for initialization, a reset signal 18.

FIG. 2 shows an example in which the method of the present invention is applied to the electronic computer shown in FIG. This is the case.

The circuit of FIG. 2 operates in the same manner as the circuit of FIG. 1 as a whole unless atomic read/write is performed.

When the reset signal 18 is issued, the flip-flop 22 is reset to "0" together with the processing device 1 via the OR gate 21, and this output is sent to the AND gate 23. Since the AND gate 23 outputs "O" at that time,
Orgate 24. The AND gate 25 is the same as without these, and the multiplexer 26 selects the data signal coming from the bus 2 side, and the operation for bus 2 is the first one.
This is the same as the circuit shown, and this operating state continues until an atomic read write is issued.

When an atomic read/write, that is, a reference to a storage device in which the atomic read/write signal 5 is 1''' occurs, the AND gate 27 outputs 0'1'' during the latter half of the write cycle. This signal becomes the register 28 no strobe signal, and the address 7 at that time is stored in the register 28.
Also, the flip-flop 22 is set to 1"'. The signal from the AND gate 27 becomes a strobe signal for the register 29, and the data 8 at that time is stored in the register 29.

When the flip-flop 22 is reset to "1", the processing device 1 starts monitoring the reference of the address stored in the register 28 to the storage device.

That is, each time the processing device 1 attempts to refer to the storage device, the comparator 31 compares that address with the address stored in the register 28 at the time of the previous indivisible read/write.
compared by. If there is no match as a result of this comparison, the comparator 31 outputs 0'', so the output of the AND gate 23 becomes 0, and the flip-flop 22 described above outputs 0.
The operation is the same as if it had been reset to ”.

If the comparison results of the comparator 31 match, the output of the AND gate 23 becomes 1'' during indivisible read/write and normal read, the output of the OR gate 24 becomes "1", and the output of the AND gate 25 becomes "1". °°0”, multiplexer 26
The output of is assumed to be the output side of the register 29. Through this operation, the bus request signal 32 is set to "0" to control the bus so that no bus operation occurs, and the bus acknowledge signal 4 is transmitted as "1'° to the processing device 1, and the read data 8 is stored in the register 29. The write data stored when the previous atomic read/write was performed is given.

Meanwhile, write operations on bus 2 are monitored. A comparator 33 detects the match between the address signal 7 on the bus and the address stored in the register 28, and an AND gate 34 detects that it is a write operation and that it is not inseparable. Detect, or gate 21
The operation of resetting the flip-flop 22 is performed via the . This operation causes the flip-flop 22 to become
When reset to I, the circuit returns to its operating state prior to detecting an atomic read write.

In addition to this, the embodiment of the present invention includes registers 28 and 2.
It is also possible to have multiple sets of 9 and perform the above-mentioned control on multiple addresses at the same time.

"Effects of the Invention" As explained above, this invention has an inseparable read/write function.11) When a write is performed, the address and data are stored, and the same address is subsequently referenced (except for normal writes). ) is performed, the bus operation is not performed, and when it is detected that a write has been performed to that address, the above operating state is canceled. , which selects only the necessary items and has the effect of reducing bus usage.

Further, the present invention has the advantage that it can also be applied to conventional processing devices.

[Brief explanation of drawings]

FIG. 1 is a diagram partially showing an example of an electronic computer not based on the present invention, and FIG. 2 is a diagram showing an example in which the system of the present invention is applied to the electronic computer of FIG. 1: Processing unit, 2: Bus, 28 Near address storage register, 29: Data storage register, 31.33 Near address comparator.

Claims (1)

[Claims] (1) Multiple processing devices share one storage device in a time-sharing manner via a common signal line (hereinafter referred to as a bus),
The processing device that uses the bus can be switched for each read/write, and after reading data at one address,
In an electronic computer system that can be controlled by a signal from a processing unit so that no other bus operation occurs during a write operation to that address (hereinafter referred to as an inseparable read/write), the inseparable a first means for storing an address at the time when a read/write operation is performed; a second means for storing data written at the time; a collation means for collating the address stored by the first means; and if the verification results in a match, the data stored by the second means is returned to the processing device as a result of reading from the storage device, and the bus is used; a third means for controlling the write operation on the bus; and a monitor means for controlling the write operation to the address stored by the first means; and a fourth means for controlling the collation by the collation means so that the collation is not performed after the detection by the collation means is performed until a new indivisible read/write is performed.