JPS6174045A - Channel control system in multi-processor system - Google Patents

Abstract

PURPOSE:To make small a load on a CPU by setting an interruption address to an exclusive control flag and a CPU interruption register during obtaining of a channel by a processing device and resetting the flag during a completion by a channel device to transfer the contents of a channel number section. CONSTITUTION:In case of accessing to a channel device by plural calculation devices, in a channel device, a CPU interruption address register 10 and a exclusive control register 20 except for a channel control register are provided and the register 20 comprises an exclusive control flag 11, exclusive control mode designating section 12 and a channel number section 14. Further, at a top bit position 13 of the number section 14, an error information is stored, and the content of the designating section 12 is set by a 2 bit constitution code. The CPU, after inspecting the flag 11, writes an address on a common bus of an interruption register 22 in the register 10 and a writing data in the number section 14, respectively to set a mode code and based on the code, the channel device controls the flag 11.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] This invention provides an integrated circuit in which a plurality of arithmetic processing units (hereinafter referred to as CPUs) and an I or a plurality of channel devices are connected via a common bus. This paper considers a channel control method in a multiprocessor system in which a channel device is accessed by a plurality of CPUs.

[Conventional technology]

Information is exchanged between the CPU and the channel device using the channel command word (
CCW) method, and a method in which the channel device has a channel control register having an address allocated to the address space of the main memory, and control is performed via the register.

FIG. 4 shows a typical configuration example of a channel control register used in a conventional single CPU system. In the figure, 31 is a status register (STR), 3
2 is a byte count register (BCR), 33 is a main memory address register (MAR), and 34 is a command register (CMR).

When the CPU accesses a channel device, it first refers to 5TR31 and determines whether access is possible. If accessible, BCR32 and MAR33
Then, necessary data is written to the CMR 34, and processing is requested to the channel device. On the other hand, when the channel device finishes processing, it generates an interrupt to the CPU.

[Problems to be Solved by the Invention] When a multiprocessor system is configured using a channel device having such a channel control register,
In order to control the acquisition of exclusive channel devices, it is necessary to provide information for managing the usage status of the channel devices, such as status information, in the main memory, etc.
In order to prevent duplicate access by each CPU, each CPU must be a master CPU or the like to manage its access. For this reason, there is a drawback that the control becomes complicated and the load on each CPU increases.

Also, the shorter the time the CPU occupies the channel device, the better, but this kind of management creates the problem of wasted time from when the channel device is released until it is used by another CPU. be.

[Purpose of the invention]

An object of the present invention is to provide a channel control system in a multiprocessor system that can reduce the load on the CPU as much as possible and shorten the time from when one CPU releases a channel device until the next time it is used. An object of the present invention is to provide a channel control method that can realize exclusive control and interrupt control.

[Means for solving problems]

In order to achieve the above problem, the present invention provides a channel device accessed by a plurality of arithmetic processing units connected by a common bus to a CP that issues a command end signal.
A U-interrupt address storage unit and an exclusive control storage unit that stores an exclusive control flag and a channel number, and each of the plurality of arithmetic processing units refers to the exclusive control flag when acquiring a channel device. , upon acquisition, the channel device stores its own interrupt address in the exclusive control flag and the CPU interrupt address register, and upon completion of command execution, the channel device resets the exclusive control flag and stores the CPU interrupt address storage unit. This attempts to transfer the contents of the channel number part according to the address information.

[Effect]

By adopting an appropriate configuration, it becomes possible to release the occupation of the channel device at the same time as the command ends, or to continue to occupy the channel device, regardless of the interrupt response time of the CPU.

(Example) 1. Figures 2 and 3 are examples of the present invention. Figure 1 shows the general configuration of a multi-CPU system, where 1 is a common bus, 2 and 3 are CPUs. , and 4 and 5 are channel devices.

Further, 6 and 7 shown as blocks in the channel devices 4 and 5 are channel control registers used for exchanging information with the CPUs 2 and 3, and are similar to the conventional one shown in FIG. In addition to the control registers shown in FIG. 2, there are a CPU interrupt address register 10 and an exclusive control register 20 shown in FIG.

Here, FIG. 2 shows the CPU interrupt address register 10.
FIG. 2 is an explanatory diagram of the configuration of the exclusive control register 20 and its operation. The right side of FIG. 2 shows the internal configuration of each CPU, and the left side shows the main internal configuration of each channel device.

As seen from the figure, the exclusive control register 20 has an I-bit exclusive control flag (ARP) 11 that indicates whether or not it is in use.
．． Exclusive control mode specification section (MOD) 12 and channel number section (CHNO) 1 for identifying four types of modes
It consists of 4. Here, the first bit position 13 of the channel number section 14 stores error information. Further, 15 is a decoder, 16, 17 and 18 are gates, 102 and 103 are mode selection signal lines, 100 is a command end signal line, and 101 is an error signal line during command execution. Here, decoder 15. gate 1
6.17 etc. can selectively use AR depending on the set mode.
Generates a signal to reset the FII flag. on the other hand,
On the CPU side, 22 is an interrupt register that temporarily holds interrupt information from the channel device, 23 is a first-in/first-out memory (Ft Fo),
24 is loca/L/bar F-'J, 26 is a calculation unit,
25 is a local bus, and 104 is a detection signal line indicating that data exists in FHFo 23.

FIG. 3 shows the contents of the exclusive control mode specifying section 12 in the exclusive control register 2o in FIG. 2 using a 2-bit code. When the 2 bits are "00" in mode 0, the exclusive control flag (ARP) 11 is always 1, and this is a mode in which the CPU continues to occupy the channel device without being reset.

In mode 1, when 2 bits are "O1", the channel device resets ARFII and releases the CPU occupation when the command ends normally, but continues to occupy the CPU when the command ends abnormally. In mode 2, when the 2 bits are "10", ARFII is reset and the CPU is freed up, regardless of whether the command terminates normally or abnormally, and in mode 3, the 2 bits are "11". Time is in reserve.

Next, these operations will be explained.

When requesting processing to a channel device, the CPU first
Exclusive control flag (ARP) 1 in exclusive control register 2o
1 is checked and only if it is ``0'', it is set to ``1'' to acquire the channel device. After that, the CPU
writes the address on the common bus of the register 22 (address allocated in the address space) to the CPU interrupt address register 10, and writes the data to be written to the register 22 to the channel number section 14 of the exclusive control register 20. .

Next, the CPU sets a predetermined mode code in the exclusive control mode specifying section 12 to determine how to occupy the channel device after the command execution is completed, and sends an activation signal to the channel device.

The channel device executes a predetermined process in response to this activation signal, and when the command execution is completed, the channel device generates a command end signal, thereby transmitting the contents of the mode specifying section 12 through the decoder 15. decode and
Controls ARFII flags.

That is, in the case of mode 0 (00''), both signal lines 102 and 103 are turned OFF, and the ARF
Always set the il flag to 1. Mode 1 (“Ol”
), the signal line 102 is turned "ON" and the AND gate 16 is established on the condition that the command is completed normally, that is, there is no error signal on the signal line 101, so the ARFII flag is reset. If the process ends abnormally, that is, if there is an error signal on the signal line 101, the ARFII flag is saved as "11". For mode 2 (“1o”), signal line 1
03 becomes “ON”, the AR
Reset the FII flag, that is, set it to "0".

On the other hand, the error signal on the signal line 101 is entered into the most significant focus section 13 of the channel number section 14.

As a result, when an error occurs as a result of command execution in the channel device, this is reset to "1", and when no error occurs, this remains at "0".

After performing the termination process in this way, the channel device performs an interrupt process to notify the CPU of the end of command execution.

In this interrupt processing, the channel device specifies the address on the common bus 1 indicated by the CPU interrupt address register 10, that is, the address of the interrupt register 22, accesses it, and adds the error signal 101 to the channel number section 14. This is done by transferring and writing the contents of the interrupt register 22 to the interrupt register 22.

On the other hand, on the CPU side, the data written in the interrupt register 22 is input to the FiFo 23. If data exists in the Fi Fo 23, a data valid signal is generated on the detection signal line 104 and output to the calculation unit 26.
6 enters interrupt processing, reads data from the channel stored in the Fi Fo 23, and learns that the command execution of the corresponding channel has ended. At this time, if an error has occurred, error handling processing such as re-execution is performed.

Moreover, in this embodiment, since the exclusive control flag indicating whether or not to continue using the channel device is managed to be selectively set by the mode setting, when the CPU continues to use the channel device, the continued use is controlled. Although there is an advantage that management of single-use and one-time use can be performed at the same time, the present invention does not necessarily need to adopt such mode settings.

Further, in this embodiment, the CPU interrupt address, exclusive control flag, etc. are stored in a register, but this may be a general memory, and may be any so-called storage unit for such information.

In addition, in the embodiment, after resetting the exclusive control flag, CPU side loading processing is performed on the CPU to finish the command execution.
The exclusive control flag may be reset at the same time as the PU side interrupt processing or after this interrupt processing. When resetting at such timing, for example, gate 1
It is preferable to insert a delay circuit into the detection signal line No. 7.

〔Effect of the invention〕

As explained above, in this invention, the channel device side manages the interrupt address for the CPU, further manages the acquisition state of the channel with its exclusive control flag, and resets it at the end of the command. Therefore, the channel device can be released and continued at the same time as the command ends, regardless of the CPU's interrupt response time. Therefore,
There is no wasted time until the CPU acquires the next channel device.

Furthermore, by specifying the mode from the CPU, fine control can be achieved.

As a result, it is possible to perform exclusive control suited to the system, and at the same time, the time occupied by the channel device can be minimized.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of a multi-CPU system according to the present invention, FIG. 2 is an explanatory diagram of the configuration of the CPU interrupt register and exclusive control register according to the present invention, and their related operations with the CPU, and FIG. 3 is an illustration of the exclusive mode An explanatory diagram showing the contents,
FIG. 4 is a block diagram of a channel control register in a conventional single CPU system. 1-common bus, 2.3-CPU, 4.5-channel device, 6.7-.-channel control register, 10
--CPU interrupt address register, 20-exclusive control register.

Claims (2)

[Claims] (1) A channel device accessed by a plurality of arithmetic processing units connected by a common bus has a CPU interrupt address storage unit that issues a command end signal, and an exclusive control storage unit that stores exclusive control flags and channel numbers. each of the plurality of arithmetic processing units refers to the exclusive control flag when acquiring a channel device; and sets its own interrupt address in the CPU interrupt address register, and the channel device resets the exclusive control flag at the end of command execution and sets the contents of the channel number section according to the address information of the CPU interrupt address storage section. A channel control method in a multiprocessor system characterized by the transfer of . (2) The arithmetic processing device stores information for setting a mode in the exclusive control storage unit, and the channel device selectively resets the exclusive control flag according to the set mode at the end of command execution. A channel control method in a multiprocessor system according to claim 1, characterized in that: