JP2594611B2 - DMA transfer control device - Google Patents

Description

Detailed Description of the Invention [Table of Contents] Overview Industrial application Field of the Invention Prior Art Problems to be Solved by the Invention Means for Solving the Problems Action Embodiment One Embodiment of the Present Invention (FIGS. 1 and 2) [Outline] Regarding the DMA transfer control device, the purpose is to provide a DMA transfer control device capable of processing even if it is terminated in the middle of the transfer, and transfer information stored in a table in an external storage device and stored sequentially. In a DMA transfer control device that holds in storage and transfers a plurality of data based on the held transfer information,
Transfer means for outputting transfer information held in the internal storage and updated along with the data transfer to a predetermined position in the external storage device when the data transfer is completed, and recognizing the transfer status of the data when the data transfer is completed And determining means for determining whether or not to output the transfer information to a predetermined position of the storage device at the end of the data transfer, and causing the storage device to output the transfer information at the end of the data transfer. It is configured to be able to arbitrarily set whether or not.

[Industrial applications]

The present invention relates to a DMA transfer control device, and more particularly, to a DMA transfer control device that writes a block transfer end status to a memory area.

Recently, with the increase in the amount of data that can be handled by computer systems, it is necessary to handle very large amounts of data at high speed, such as input / output with an auxiliary storage device such as a magnetic disk device, or image data processing. In response to these, so-called DMA transfer for performing data transfer without the intervention of a CPU is performed. That is, since normal data transfer is performed via the CPU, the processing speed of data transfer is CP
The processing speed of U is dominant, and it is impossible to perform high-speed data transfer that the processing speed of CPU cannot keep up with. Even if the data transfer is not so fast, the transfer process takes a long time if the amount is large. Therefore,
By using a DMA transfer control device to directly transfer data between an external peripheral device and memory or between memories without using a CPU with a slow processing speed, the data transfer speed is increased to achieve high-speed or large-volume data transfer. Processing efficiently.

[Conventional technology]

A DMA transfer control device (hereinafter, referred to as a DMA controller: DMAC) is a part of the computer system as described above, and usually a CPU exclusively uses a bus in the system to transfer data. That is, the bus exclusive right is usually the CPU
And generally has the highest CPU ownership within a system.

When a DMA transfer request occurs, the CPU changes the bus
The bus is transferred to the AC and released to the DMAC, and the DMAC occupies the bus in place of the CPU and performs DMA transfer. In this case, DMA transfer methods are roughly classified into two types: register direct and descriptor chain.
DMA transfer based on information written in registers in the MAC, for example, transfer source address (source address), transfer destination address (destination address), transfer data amount (byte count), and other transfer information necessary for transfer I do. In the latter case, the DMAC sequentially reads out tabulated transfer information (descriptor) registered in the memory in the system before the DMA transfer by the CPU, stores the information in an internal register, and performs DMA transfer based on the information in the register. In the DMA transfer by the descriptor chain, when the transfer of data of a block indicated by a set of descriptors, that is, data of a continuous area in the memory indicated by each address of a source or a destination and a byte count is completed, the next descriptor is read. , A plurality of block transfers are continuously performed.

Specifically, prior to the DMA transfer by the DMAC, the CPU tabulates the descriptor and writes the table to the memory, and also writes a descriptor address register (DSR) in the DMAC.
The address at which the descriptor of the first block of the block transfer is stored (hereinafter, referred to as the descriptor address). When a transfer request occurs, the DMAC
The descriptor is registered in the internal memory address register (MAR) and the byte count register (BCR) from the address indicated by (1), and DMA transfer of one data block indicated by MAR and BCR is started. D of one block
When the MA transfer ends, the DMAC updates the DSR value according to the internal microprogram, reads the next descriptor, registers it in the internal MAR and BCR, and starts the transfer of the next data block. As described above, the DMA transfer of a plurality of data blocks is performed by sequentially reading the descriptor of the data block to be transferred next.

[Problems to be solved by the invention]

However, in such a conventional DMA transfer device, when data transfer of a plurality of blocks is performed, each time data transfer of one block is completed, the next descriptor is stored and updated internally. Had the following problems.

That is, when the DMAC terminates the transfer, it terminates due to a transfer termination request from an input / output controller (hereinafter referred to as IOC), terminates when the byte count value of the data to be transferred becomes zero, or causes a fatal error such as a bus error. However, when a fatal error occurs, the next descriptor is not read.
By reading the register inside C, the end status of this time can be known. However, at the end of the normal transfer, the information disappears when the next descriptor is read, so that the CPU cannot know the end status when the DMAC ends the transfer. For example, when the transfer is completed, the memory area in which the transferred data is already stored is unknown, so that it is difficult to know where valid data is stored and at what address, and system processing becomes difficult. .

Therefore, the present invention writes the block transfer end status to the memory as needed, so that the CPU can know the block transfer end status, and even if the transfer is ended halfway, the DMA that can be processed can be processed. It is intended to provide a transfer control device.

[Means for solving the problem]

In order to achieve the above object, a DMA transfer control device according to the present invention sequentially stores, in an internal storage, transfer information stored in a table in an external storage device, and transfers a plurality of data based on the held transfer information. In the transfer control device, there is provided transfer means for outputting transfer information held in the internal storage and updated at the time of data transfer to a predetermined position of the external storage device at the end of the data transfer, wherein the data at the end of the data transfer is provided. To be able to recognize the transfer status.

Further, a determination unit is provided for determining whether or not to output the transfer information to a predetermined position of the storage device at the end of the data transfer, and optionally determines whether or not to output the transfer information to the storage device at the end of the data transfer. Configurable.

[Action]

In the present invention, when the block transfer ends, the value of the status at the end of the transfer is transferred to a predetermined memory area in the system.

Therefore, at the same time when the block transfer is completed and the bus right is returned to the CPU, the information at the time of the transfer is transferred to the territory of the CPU, and the CPU confirms the end state of the block transfer according to the application of the system.

〔Example〕

 Hereinafter, embodiments of the present invention will be described with reference to the drawings.

FIGS. 1 and 2 show an embodiment of the DMA transfer control device according to the present invention.

First, the configuration will be described. For convenience of description, the following description is based on the assumption that block transfer is performed between a memory of the system and a device outside the system.

In FIG. 1, reference numeral 1 denotes a DMAC, and DMAC 1 denotes a data control unit (hereinafter, referred to as a D unit) 2, a micro sequence control unit (hereinafter, referred to as an M unit) 3, and a transfer request control unit (hereinafter, referred to as an R unit).
The units 2, 3, and 4 are interconnected via a data bus 5 and an address bus 6 inside the DMAC 1. As shown in FIG. 2, the DMAC 1 is connected to the RAM 10, the IOC 11, the CPU 19 and the like via the data bus 7, address bus 8 and control bus 9 of the system. The D unit 2 is connected to the data bus 7, the address bus 8 and the control bus 9, and mainly controls input / output data of the DMAC1. The R unit 4 determines the processing to be performed, for example, a transfer request signal REQ and a transfer end request signal D.
ONE is accepted, and the processing to be performed next is determined. The M unit 3 operates the transfer control information in accordance with the processing determined by the R unit 4, and outputs necessary control information to the D unit 2.

Prior to the instruction to start the DMA transfer, the CPU 19 writes the descriptor table 13 in which the descriptor is tabulated in a predetermined area of the RAM 10 and instructs the descriptor address register DSR15 in the DMAC 1 to indicate the start address of the descriptor table 13 and to update the descriptor table. Write whether or not to update the descriptor table in register DTU20. In this embodiment, a descriptor table corresponding to one data block is composed of two words of a memory address MAn and a byte count BCn (n is a natural number), and the descriptor table is stored in a continuous memory area in the order in which transfer is performed. Shall be performed. When a DMA transfer start is instructed by the CPU 19 and a transfer request signal REQ is output from the IOC 11, the R unit 4 accepts the transfer request signal REQ and notifies the micro sequence controller (M) in the M unit 3 that a transfer request has occurred. This is notified to the MC unit 12 and the D unit 2. The D unit 2 that receives the transfer request generates the CPU 19
Hold request signal HREQ for requesting exclusive use of the bus to
The CPU 19 returns a hold permission signal HACK to the D unit 2 if the bus can be released, and the D unit 2 receives the hold permission signal HACK and notifies the M unit 3 that the exclusive right of the bus has been acquired. Notice. When the exclusive right of the bus is acquired, the MC unit 12 of the M unit 3 outputs control information necessary for performing the DMA transfer to the D unit 2 according to the microprogram stored therein. At this time, DMAC1
Starts a DMA transfer via the data bus 7, address bus 8 and control bus 9 of the system.

In the DMAC 1 shown in FIG. 2, in order to clarify the relationship between the information transmitted by the data bus 7, the address bus 8 and the control bus 9 and the register group 14 including DSR 15, MAR 16, BCR 17, DSRW 18 and DTU 20 Register group 14
Only the others are shown and the others are omitted.

The D unit 2, the data bus 5, the address bus 6,
The MC unit 12, DSR15 and DSRW18 constitute transfer means, and the MC unit 12 and DTU20 constitute decision means, and exhibit predetermined functions according to the microprogram stored in the MC unit 12. However, details will be described later.

 Next, the operation will be described.

When DMAC1 starts DMA transfer, MC unit 12
The contents of DSR15 are transferred to DSRW18, and the D unit 2 accesses the address of RAM10 indicated in DSR15. The address of the accessed RAM 10 is a descriptor corresponding to the first data block, that is,
Are written memory address MAR ₁ and byte count BCR ₁ is the descriptor is held in the descriptor table 13, respectively MAR16 and BCR17 is read from, DSR15 is updated by the number of words descriptors read. Then, according to the instruction of the M unit 3 based on the microprogram stored in the MC unit 12, MA
The transfer between the RAM 10 and the IOC 11 indicated by R16 and BCR17 is performed by the D unit, and the MAR16 and BCR17 are updated by the number of bytes transferred by the MC unit 12. For example,
When performing a DMA transfer from the RAM 10 to the IOC 11, the data bus 7,
A data block in the memory area indicated by the MAR 16 and the BCR 17 is read out via the address 8 and the control bus 9, and transferred to the IOC 11. When the transfer of one data block is completed, the DTU 20 is referred to by the MC unit 12, and when the update of the descriptor table is instructed, the contents of the DSR 15 and the DSRW 18 are converted, and the MAR 16 and the BCR 17 are converted into the address of the RAM 10 indicated by the DSR 15. Is written, and then the contents of DSR15 and DSRW18 are converted again. That is, the value of the descriptor updated by the DMA transfer is written to the address where the descriptor was read. When the update of the descriptor table is not instructed, the updated descriptor is not written in the memory. Here, the MC unit 12 checks whether or not the transfer end condition specified in advance is satisfied. If the transfer end condition is not satisfied, the descriptor corresponding to the next block indicated in the updated DSR 15 Is read. The transfer end condition is, for example, a predetermined number of data blocks are transferred.
And so on. Thereafter, the descriptors are sequentially read from the descriptor table 13 until the transfer end condition is satisfied.
The DMA transfer is performed between the RAM 10 and the IOC 11, and when the DTU 20 is instructed to update the descriptor table every time the transfer of one data block is completed, the updated descriptor is read out. Is written to the address of the RAM 10.

When the update of the descriptor table is instructed to the DTU 20, after the transfer of all the data blocks is completed, the CPU 19 can know the end state of each data block by reading the descriptor table 13 of the RAM 10. In other words, the descriptor table of the block whose byte count value is zero and finished has a byte count of zero, and the byte count of the descriptor table of the block that is completed after the transfer end request signal DONE is input is calculated from the initially set value. It indicates the value obtained by subtracting the number of bytes transferred, that is, the number of bytes not transferred.

In addition, since the MC unit 12 determines whether or not to update the descriptor table after referring to the DTU 20, when a series of data transfer is repeatedly performed using the same table as well as the block transfer Can respond quickly.

In this embodiment, the transfer of the descriptor to the RAM 10 is realized by using a microprogram. However, the application of the present invention is not limited to this. For example, the transfer can be realized by hardware.

Further, in this embodiment, the DSRW 18 is provided in addition to the DSR 15 to hold the descriptor address, but when the address of each descriptor is continuous, the DSRW 18
Instead, the value of DSR15 may be decremented and counted by the number of bytes corresponding to two words each time transfer of one data block is completed.

〔effect〕

According to the present invention, when the block transfer is completed, a transfer control means for transferring the value of the register at the time of completion of the transfer to a predetermined memory area is provided.
At the same time as returning to U, the information at the end of transfer is transferred to the territory of the CPU, so the CPU can check the end status of the block transfer according to the system application and it can be terminated in the middle of the transfer. DM that can be processed even
A transfer controller can be obtained.

[Brief description of the drawings]

1 and 2 are diagrams showing an embodiment of a DMA transfer control device according to the present invention, FIG. 1 is a block diagram showing an overall configuration thereof, and FIG. 2 is a main part configuration diagram showing the system. is there. 1 ... DMAC, 2 ... D unit (transfer control means), 5 ... data bus (transfer control means), 6 ... address bus (transfer control means), 12 ... MC unit (transfer control means), 15 ... DSR (transfer control means), 18 ... DSRW (transfer control means), 12 ... MC unit (decision means), 20 ... DTU (decision means).

Claims (2)

(57) [Claims] 1. A DMA transfer control device for sequentially holding transfer information stored in a table in an external storage device and storing the transfer information in an internal storage, and transferring a plurality of data based on the held transfer information. Transfer means is provided for outputting transfer information held and updated along with the data transfer to a predetermined position in the external storage device when the data transfer is completed, so that the transfer status of the data can be recognized when the data transfer is completed. A DMA transfer control device, characterized in that: And determining whether or not to output the transfer information to a predetermined position of the storage device at the end of the data transfer, and determining whether or not to output the transfer information to the storage device at the end of the data transfer. 2. The DMA transfer control device according to claim 1, wherein said DMA transfer control device can be set arbitrarily.