JPS55154623A - Input and output control system - Google Patents

Input and output control system

Info

Publication number
JPS55154623A
JPS55154623A JP6260079A JP6260079A JPS55154623A JP S55154623 A JPS55154623 A JP S55154623A JP 6260079 A JP6260079 A JP 6260079A JP 6260079 A JP6260079 A JP 6260079A JP S55154623 A JPS55154623 A JP S55154623A
Authority
JP
Japan
Prior art keywords
unit
input
output control
control information
dma
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP6260079A
Other languages
Japanese (ja)
Inventor
Toshihiko Matsuda
Sunao Hirata
Morihiko Takashi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP6260079A priority Critical patent/JPS55154623A/en
Publication of JPS55154623A publication Critical patent/JPS55154623A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE: To increase the processing efficiency of a computer system, by storing the control information of an input and output control unit to the device control block of a main memory, and directly transferring the information to this unit with a specific instruction in the direct memory access interface mode.
CONSTITUTION: When a main memory 1 of a data processor and an input and output control unit 3 are in direct memory access interface DMA mode, the control information of the unit 3 is stored in the device control block DCB of the memory 1 and this control information is transferred to the unit 3 in DMA mode with a specific instruction. Thus, the storage of the value of head address of DCB to the DMA address register 5, allows the occupied time of processor to be minimized and the processing efficiency of computer system to be increased.
COPYRIGHT: (C)1980,JPO&Japio
JP6260079A 1979-05-23 1979-05-23 Input and output control system Pending JPS55154623A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP6260079A JPS55154623A (en) 1979-05-23 1979-05-23 Input and output control system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6260079A JPS55154623A (en) 1979-05-23 1979-05-23 Input and output control system

Publications (1)

Publication Number Publication Date
JPS55154623A true JPS55154623A (en) 1980-12-02

Family

ID=13204978

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6260079A Pending JPS55154623A (en) 1979-05-23 1979-05-23 Input and output control system

Country Status (1)

Country Link
JP (1) JPS55154623A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60122452A (en) * 1983-12-05 1985-06-29 Fujitsu Ltd Controller
JPS615364A (en) * 1984-06-19 1986-01-11 Fujitsu Ltd Bus control system
JPS6132144A (en) * 1984-07-25 1986-02-14 Hitachi Ltd Exclusive data processing system by microprogram control
JPH01261763A (en) * 1988-04-13 1989-10-18 Fujitsu Ltd Dma transfer control device

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60122452A (en) * 1983-12-05 1985-06-29 Fujitsu Ltd Controller
JPH0136138B2 (en) * 1983-12-05 1989-07-28 Fujitsu Ltd
JPS615364A (en) * 1984-06-19 1986-01-11 Fujitsu Ltd Bus control system
JPS6132144A (en) * 1984-07-25 1986-02-14 Hitachi Ltd Exclusive data processing system by microprogram control
JPH01261763A (en) * 1988-04-13 1989-10-18 Fujitsu Ltd Dma transfer control device

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