JPH0136138B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (a) Technical Field of the Invention The present invention relates to a control method for efficiently performing input/output control in a control device controlled by a microprocessor.

(b) Background of the Technology With recent remarkable progress in semiconductor devices, control devices controlled by microprocessors have come into widespread use.

On the other hand, input/output devices (for example, display devices, printer devices, etc.) connected to such control devices
There is a trend toward faster speeds as general data processing systems become larger and faster.

However, the processing power of control devices controlled by microprocessors is limited, and when multiple high-speed input/output devices such as those mentioned above are connected, it is difficult to fully utilize the characteristics of the input/output devices. I had a problem that didn't exist.

Therefore, there is a need for a control method for the input/output device in the above-mentioned control device that reduces the burden on the microprocessor as much as possible.

(c) Prior art and problems Figure 1 is a block diagram of a control device related to the present invention, where 1 is a control device, 11 is a microprocessor (hereinafter referred to as MPU), and 12 is a memory (hereinafter referred to as MPU). 12a is a memory control unit, 13 is an input/output control unit (hereinafter referred to as IOC), 14 is a common bus, 15 is a bus control unit, and 2 is an input/output device (hereinafter referred to as I/O).

The IOC 13 of the control device 1 includes a line control unit (ADLC) 131 that performs line control using, for example, a high-level transmission control procedure (HDLC procedure). , information is now being exchanged using half-duplex.

The information exchange is performed in the following steps.

A transmission control parameter value is set from the MEM 12 in a control register (CR) 1311 provided in the IOC 13, and the line control unit (ADLC) 131 is switched from the "idle" state to the "transmission state".

Sends commands and data (in the case of write commands) to I/O2.

At the completion of sending commands and data (IOC1
3, when byte counter (BC)=0 is detected), the line control unit (ADLC) 131 is switched to the "receiving state".

Data from I/O2 (at the time of read command),
Or receive the status (for read and write commands).

After receiving the status, line control unit (ADLC) 1
31 is "vacant".

In the above information exchange procedure, in the conventional system, is executed by a program executed by the MPU 11, and is executed by the IOC 13 by direct memory access (hereinafter referred to as DMA). In this DMA, the program executed by MPU 1 specifies the number of words to be transferred and read/write in advance.
After setting information such as writing in the byte counter (BC) and register (R/W) in the IOC 13, and setting the memory transfer start address in the address register (AR) in the memory control unit 12a, By issuing an output command, the corresponding IOC1
It was carried out by 3.

Among the above processes, the process of IOC
13 requests the bus control unit 15 for the right to use the common bus 14 and is granted the right to use the common bus 14.
Through 4, perform the above DMD and at the same time MPU
IOC1 is set in advance by the program executed in IOC1.
Byte counter (BC) set within 3
The IOC 13 updates the byte every time a 1-byte transfer is completed, and when the value of the byte counter (BC) reaches "0", the IOC 13 generates a termination interrupt for the program, and the MPU 1 The final processing program executed in the IOC 13 reads the reception control parameter value from the input/output control parameter area 121 of the MEM 12 into the control register (CR) 1311 in the IOC 13, and
By setting the control register (CR) 1311 in the I/O2 (indicated by 1 in Figure 1), the transmission/reception is switched, and then it prepares to receive the status which is the completion report sent from I/O2. Ta.

Therefore, if the MPU 1 uses multiple line control units (ADLC), for example, the above-mentioned completion report will be displayed from the "transmission state" where command processing is being performed, since the processing is performed by the above program. There was a problem that it was not possible to switch to the "receiving state" in time to receive the status.

(d) Purpose of the Invention In view of the above-mentioned drawbacks of the conventional technology, the present invention provides an MPU and
It is a control device consisting of MEM and IOC, and the above
A control device that controls transmission and reception with I/O based on the transmission and reception control parameter values set in the control register (CR) for communication control provided in the line control unit (ADLC) in the IOC. In the above
It is an object of the present invention to provide a method of writing the reception control parameter value to the control register (CR) of the line control unit (ADLC) in the IOC using DMA.

(e) Structure of the Invention According to the present invention, this object comprises at least a microprocessor, a memory, a memory control section, an input/output control section, a bus control section, and a common bus. , a control device in which direct memory access from an input/output control unit permitted to use a common bus by the bus control unit and memory access by the microprocessor use the same bus,
When the transmission/reception control parameter values prepared in advance on the memory are stored in the control register provided in the input/output control section by the program executed by the microprocessor, the contents are Therefore, in the above control device in which the input/output control section performs transmission/reception control with the input/output device,
The microprocessor activates data transfer to the input/output control unit, the activated input/output control unit transfers data to and from the input/output device, and detects the end of the data transfer. At that point, the bus control unit requests the use of the common bus, and when it is granted, autonomously reads the reception control parameter values from the memory by direct memory access and stores them in the input/output control unit. The input/output control unit is provided with means for storing information in the control register of the common bus, and when the input/output control unit requests the bus control to use the common bus and is granted permission, the input/output control unit stores the data in the control register by the means. This is achieved by providing a method for the input/output control unit to perform reception operations with the input/output device in parallel with the microprocessor based on the stored reception control parameter values, Parameter values for reception control are set in the control register in the output control unit by direct memory access from the input/output control unit without going through the program, improving program execution efficiency in the microprocessor. At the same time, since the parameter values for reception control are set in the control register at high speed, it becomes possible to use a plurality of input/output control sections, which has the advantage of improving the processing capacity of the main body of the control device.

(f) Examples of the invention Examples of the invention will be described in detail below with reference to the drawings.
FIG. 2 is a diagram illustrating an embodiment of the present invention in comparison with a conventional system, and includes 11, 12, 12a,
13, 14, 15 are the same as those explained in FIG. 1, 15 is a bus control section, 121
1 is an input/output control parameter storage area in the MEM 12, 131 is a line control unit (ADLC), and 1311 is the control register (CR). The dotted line (1) shows the transfer route of the reception control parameter value when the process explained in FIG. This shows the transfer route in this case.

In the conventional method shown in (1), IOC13
When detects byte counter = 0,
By issuing a termination interrupt to the MPU 11 and having the MPU 11 execute the interrupt program,
The reception control parameter value is read from the input/output control parameter storage area 121 in the MEM 12 and written to the control register (CR) 1311 provided in the line control unit (ADLC) 131 in the IOC 13. )13
11, the IOC 13 performs transmission/reception switching control, and then the IOC 13 executes the operations described in FIG. 1 (receiving data and status from the I/O 2).

The above transmission/reception switching control method when implementing the present invention is shown in (2). In this case, the IOC 13 itself performs the control explained in FIG. 1 when the byte counter (BC) = 0. At the point when the program to be executed on MPU1 is set in advance,
Input/output control parameter storage area 1 in MEM12
Line control unit (ADLC) 1 prepared in 21
The reception control parameter value to be set to 31 is
The input/output control parameter area 12 of MEM12
1 by DMA and set in the control register (CR) 1311 provided in the line control unit (ADLC) 131 in the IOC 13.
The subsequent operation is the same as that of the conventional method.

When the IOC 13 reads the reception control parameter value from the MEM 12 using the above DMA,
It is necessary to secure the common bus 14 for one bus cycle, but this bus cycle stealing operation
The IOC 13 sends a bus use request to the bus control unit 15 when the DMA is required,
This can be done by receiving a bus use permission (OK) signal from the bus control section 15. At this time, the number of transferred words is set to the byte counter (BC) in the IOC 13, the read information (R) is set to the register (R/W), and the address register (AR) of the memory control unit 12a is set. The memory transfer start address is set by the corresponding IOC.
13 autonomously performs the above-mentioned operation, that is, at the time when the sending of the command and data is completed, that is, when the above-mentioned byte counter (BC)=0 is detected.

In this control device, DMA from IOC13
When there is no bus access from MPU 11, bus access from MPU 11 is unconditionally permitted, and when there is bus access from both
The bus controller 15 controls the DMA and the DMA so that the common bus 14 can be used alternately.

As described above, when the present invention is applied, IOC1
3, the DMA switches between transmission and reception, so after the IOC 13 completes data transmission and until it receives the status information of the completion report sent from the I/O 2, the contents of the control register can be changed. can be quickly put into the "receiving state",
This is the main focus of the present invention. That is, the above-mentioned half-duplex information exchange operation (i.e., the above-mentioned operation) is executed by software, and the subsequent information exchange (i.e., the above-mentioned operation) is performed, as well as reception control for switching between transmission and reception. The setting of parameter values for the control register (CR) 1311 in the control register (CR) 1311 is also performed by DMA, and when the information exchange is completed and the line control unit (ADLC) 131 becomes 'vacant' (i.e.,
The feature of this method is that it interrupts the software and performs the finalization process.

(g) Effects of the Invention As explained in detail above, the control device of the present invention has a common control device that can be used at least for a microprocessor, a memory, a memory control section, an input/output control section, and a bus control section. Direct memory access from the input/output control unit, which is permitted to use a common bus by the bus control unit, and memory access by the microprocessor are control devices that use the same bus. When the transmission/reception control parameter values prepared in advance on the memory by the program executed by the microprocessor are stored in the control register provided in the input/output control section, the contents are changed. Therefore, in the control device in which the input/output control unit performs transmission/reception control with the input/output device, data transfer is activated from the microprocessor to the input/output control unit, and the activated input The output control unit performs transmission data transfer with the input/output device, and when it detects the end of the data transfer (byte counter = 0), requests the bus control unit to use the common bus and grants permission. means is provided in the input/output control unit to autonomously read the reception control parameter value from the memory by direct memory access and store it in a control register in the input/output control unit, when the input/output control unit When the control unit requests the bus control to use the common bus and is granted permission, the input/output control unit controls the microcontroller according to the reception control parameter value stored in the control register by the above means. Since it is controlled to perform reception operations with input/output devices in parallel with the processor,
This eliminates the burden on the program to control transmission/reception switching in the input/output control unit, which was done in the conventional method, which improves program execution efficiency on the microprocessor and reduces switching processing. Since the speed is increased, it becomes possible to use a plurality of line control units (ADLC), which has the effect of improving the processing capacity of the entire control device.

[Brief explanation of drawings]

FIG. 1 is a diagram showing the configuration of a control device related to the present invention, and FIG. 2 is a diagram illustrating an embodiment of the present invention in comparison with a conventional system. In the figure, 1 is a control device, 2 is an input/output device,
11 is a microprocessor (MPU), 12 is a memory (MEM), 12a is a memory control unit,
13 is an input/output control unit (IOC), 14 is a common bus,
15 is a bus control section, 121 is an input/output control parameter area, 131 is a line control section (ADLC),
1311 shows a control register (CR), (1) shows a control register update route according to the conventional method, and (2) shows a control register update route when the present invention is implemented.

Claims (1)

[Claims] 1 Consists of at least a microprocessor, a memory, a memory control section, an input/output control section, a bus control section, and a common bus, and is permitted to use the common bus by the bus control section. The control device uses the same bus for direct memory access from the input/output control unit and memory access by the microprocessor, and is configured such that direct memory access from the input/output control unit and memory access by the microprocessor use the same bus. When the parameter values for transmission/reception control prepared in the input/output device are stored in the control register provided in the input/output control unit, the input/output control unit controls transmission/reception between the input/output device and the input/output device depending on the contents. In the control device that performs
The activated input/output control unit transfers data to and from the input/output device, and upon detecting the end of the data transfer, requests the bus control unit to use the common bus and is granted permission. The input/output control section is provided with means for autonomously reading the reception control parameter value from the memory by direct memory access and storing it in a control register in the input/output control section, when the input/output control section When the unit requests the use of the common bus from the bus control unit and is granted permission, the input/output control unit requests the microprocessor to use the common bus based on the reception control parameter value stored in the control register by the above means. A control device that performs a receiving operation with an input/output device in parallel with a setter.