JPS61285566A - Input and output controller - Google Patents

Abstract

PURPOSE:To attain the transfer of data at a high speed by setting two FIFO buffers storing the data of n-bit width respectively in parallel between a host bus of 2n-bit width and a local bus of n-bit width. CONSTITUTION:A multiplexer/demultiplexer 19, an FIFO buffer 17 and a buffer circuit 18 are provided between a host bus 14 and a local bus 12. Thus the DMA transfer is possible with 16-bit and 8-bit widths. The changeover between these two data widths is carried out when the execution is started according to the contents of information written to an input/output controller from a host system. Then it is decided from the information set to a control register 10 whether the DMA transfer of 8 bits or 16 bits should be carried out. Based on this information, a local processor 2 decides the data width and informs it to an FIFO controller 20 before execution of the DMA transfer. Thus the controller 20 works by said information.

Description

[Detailed Description of the Invention] [Summary] In an input/output control device that has a local bus of n bits and performs data transfer with a host system having a host bus of 2n bits, each of n bits Two FIFO buffers for storing data are provided in parallel between a 2n-bit wide host bus and a local bus in n pinpoints, and when transferring n-bit data, one of the FIFO buffers is used. A configuration is shown in which both FIFO buffers are used when performing bit-width data transfers.

[Industrial application field]

The present invention relates to an input/output control device that transfers data between a host system and, for example, controls high-speed input/output devices such as a hard disk drive, a floppy disk drive, and a modem device in a computer system. The present invention relates to an input/output control device that transfers information using DMA transfer.

[Conventional technology]

In input/output devices of computer systems, the data is often configured in units of 8 bits (1 byte). Therefore, for transfers with the host, the bus width of the host processor is 16
Even for bits (one word), many use only 8-bit data.

FIG. 2 is a diagram showing one configuration example of a conventional input/output control device. In the figure, 1 is an internal DMA controller, 2 is a local processor, and 3 is a local RAM.

4 is a local ROM, 5 is an input/output controller, 6 is a register buffer, 7 is a register control circuit, 8 is a receiver/driver circuit, 9 is an address decoder, 10
is a control register, 11 is a status register,
12 is a local bus, 13 is an interface bus, 14
1 is a host bus, 15 is a data bus, and 16 is an address bus.

In FIG. 2, illustrations of the host processor, host DMA controller, etc. connected to the host bus are omitted.

In the conventional configuration shown in FIG. 2, an 8-bit buffer register 6 is provided between the host bus 14 and the local bus 12, and data is exchanged by latching input/output data to this buffer register 6. ing.

[Problem that the invention seeks to solve]

If data transfer is performed using only 8-bit data in this way, a problem arises in that high-speed data transfer cannot be performed. Furthermore, there are few DMA controllers that can transfer 16-bit data. Therefore, the DMA data width of the input/output control device is limited to 8 bits. Furthermore, in order to increase the speed, a system capable of executing 16-bit DMA is being considered, but it has the drawback that it is not possible to switch between 8 and 16 bits using a command.

[Means for solving problems]

In order to solve the above problems, the present invention provides an input/output control device that has a local bus of n bits and performs data transfer with a host system having a host bus of 2n bits. Store the data of 2
2n FIFO buffers connected to a 2n-bit wide host bus
A configuration in which one FIFO buffer is provided in parallel between the local buses of bits, and when transferring data of n bits, one specified FIFO buffer is used, and when transferring data of 2n bits, both FIFO buffers are used. is presenting.

〔Example〕

FIG. 1 is a diagram showing the configuration of an input/output control device according to an embodiment of the present invention.

In the figure, 1 is an internal (local) DMA controller, 2 is a local processor, 3 is a local ROM, 4 is a local RAM, 5 is an input/output controller, 8 is a receiver/driver circuit, 9 is an address decoder, 10 is a control register, 11 is a status register, 12 is a local bus, 13 is an interface bus, 14 is a host bus, 15 is a data bus, 16 is an address bus, 17 is a first-in first-out (FIFO) buffer,
18 is a buffer circuit, 19 is a multiplexer/demultiplexer, and 20 is a FIFO controller.

In the embodiment, between the host bus 14 and the local bus 12, a multiplexer/demultiplexer 19, a FIF
An O buffer 17 and a buffer circuit 18 are provided to enable 16-bit and 8-bit width DMA transfer. Furthermore, the data width is switched based on the information content written from the host system to the input/output control device at the time of execution start-up.

FIG. 3 is a diagram showing in more detail the FIFO buffer 17 and its peripheral circuits in the embodiment shown in FIG.

In FIG. 3, 8 is a receiver/driver circuit, 12 is a local bus, 20 is a FIFO controller, 30 and 3
1 is a buffer circuit, 32 and 33 are FIFO buffers, 3
4 and 35 are registers, 36 and 37 are multiplexers, 3
8 is a demultiplexer.

The operation of the embodiment will be explained below.

First, the overall operation of the input/output control device is as follows.

In order to reduce the burden on the control host of the connected I10 device, this device controls Ilo using the firmware of the local processor 2, and the host only controls data exchange using DMA transfer. An example of an execution flowchart is shown in FIG. 4 as an example of the operation of this apparatus. After the control consists of several bytes, the host knows the end from the information in the status register 11. In this device, when the host finishes writing to the control register 10, an interrupt is applied to the local processor 2, and the operation is started. Then, the local processor 2 analyzes the contents of the control register 10, executes the operation, and when the internal operation is completed, sets termination information in the status register 11 and notifies the host, thereby terminating the operation.

In DMA transfer, the control register 10 determines whether to perform 8-bit transfer or 16-bit transfer.
Determined by the information set in .

The local processor 2 of this device determines the data width based on this information, and notifies the FIFO controller 20 of the data width before executing the DMA transfer, and the FIFO controller 20 operates based on this information.

Next, the operation of the FFO buffer, which is the main part of this device, and its surroundings will be explained below. The operation of this circuit section is in four states: 8-bit read, 16-bit read, 8-pin write, and 16-bit write.All these operations are mainly based on the configuration shown in FIG. This is shown in the flowchart in Figure. In each flowchart, since the input/output control device and the host operate independently, the input/output device side and the host side are shown in two separate charts.

These two operations are asynchronous operations because the FIFO buffer is involved.

First, the 8-bit data read operation will be explained based on FIG. 5(a).

■ When the input/output control device becomes activated, DM is sent from the FIFO controller 20 to the local DMA controller 1.
Request A action.

(2) The local DMA controller 1 responds by taking out data from the local RAM 4 used as a temporary buffer and setting the data in the register 35. Note that the multiplexer is set in advance to select data on the local bus 12.

■ Check whether the FIFO buffer 33 is full of data.

■ If there is space in the FIFO buffer 33, data is written.

(2) The number of remaining data to be transferred is checked, and if there is any remaining data, it will be related to the DM and A operation requests, and if the remaining data is "0°", the operation will end.

(2) On the host side, a host DMA controller (not shown) is activated asynchronously with the input/output control device.

■ Check whether there is data to be output in the FIFO buffer 33.

■ If there is data to be output, request DMA transfer from the host.

(2) The host DMA controller responds and reads data from the FIFO buffer 33 to the host bus 14.

Here, the data is transferred to the lower 8 bit positions of the host bus via the buffer circuit 31 and the receiver/driver circuit 8.

[Phase] If there is remaining data, operation continues,
If there is no remaining data, the operation on the host side ends.

Next, the 16-bit data read operation will be explained based on FIG. 5 (bl).

■ When the human output control device becomes activated, DM is sent from the FIFO controller 20 to the local DMA controller 1.
Request A action.

@The local DMA controller 1 responds, takes out data from the local DMA 4 used as a temporary buffer, and sets the data in the register 34.

@ Tomioka checks whether the FIFO buffer 32 is in a data-full state.

@ If there is space in the FIFO buffer 32, data is written.

(2) The FIF◯ controller 20 requests the local DMA controller 1 to perform a DMA operation.

(2) The local DMA controller 1 responds, takes out data from the local RAM 4, and sets the data in the register 35.

@Check whether the FIFO buffer 33 is full of data.

@ If there is space in the FIFO buffer 33, data is written.

[Phase] If there is remaining data, operation continues,
If there is no remaining data, the operation on the host side ends.

[Phase] On the host side, the host DMA controller is activated asynchronously with the input/output control device.

Both OFIFO buffers 32 and 33 are checked to see if there is any output data.

If there is output data in both buffers, request DMA transfer to the host.

(2) The host DMA controller responds and reads data from the FIFO buffers 32 and 33 to the host bus 14.

Here, data is transferred via buffer circuits 30 and 31 and receiver/driver circuit 8 in the form of 16-bit data.

■If there is any remaining data, the operation continues; if there is no remaining data, the operation on the host side ends.

Next, the 8-bit data write operation will be explained based on FIG. 5(C).

(If there is rewrite data, a DMA activation request is generated on the host side.

■ A DMA request is sent to the host DMA controller.

O host DMA controller responds and sets data in register 35. Data is input to register 35 via receiver/driver circuit 8 and multiplexer 37. The multiplexer is preset to pass data from the host bus. Only the lower 8 bits are used for host data.

@Check whether the FIFO buffer 33 is full of data.

@ If there is space in the FIFO buffer 33, data is written.

■If there is any remaining data, the operation continues; if there is no remaining data, the operation on the host side ends.

(2) On the input/output control device side, check whether there is output data in the FIFO buffer 33.

@ If FIFO buffer 3 core 33 data is available, request DMA operation t- to local DMA controller 1.

■ Local DMA controller 1 responds and sends the FIF
○Read data from buffer 33 and store it in local RAM 4
Write data to the header.

Note that the data in the FIFO buffer 33 is transferred onto the local bus 12 via the demultiplexer 38.

Demultiplexer 38 is set to pass lower order data.

■If there is any remaining data, the operation continues; if there is no remaining data, the operation of the input/output control device ends.

Next, the data write operation 16 will be explained based on FIG. 5(d).

■When there is write data, a DMA activation request is generated on the host side.

■ A DMA request is sent to the host DMA controller.

- The host DMA controller responds and registers 34.
Set the data to 35.

@ Check whether FIFO buffer 32.33 is full of data.

If both buffers 32 and 33 are not in a data full state,
Write data (16 bits) to both buffers 32 and 33.

■If there is any remaining data, the operation continues; if there is no remaining data, the operation on the host side ends.

■On the input/output control device side, one FIFO buffer 32
Check whether there is output data.

@ If there is output data in the FIFO buffer 32, a request is made to the local DMA controller 1 for DMA operation.

(2) The local DMA controller 1 responds, reads data from the FIFO buffer 32, and transfers the data to the local RAM 4.

Data is transferred to local bus 12 via demultiplexer 38.

Here, the demultiplexer 38 is set to pass the upper 8 bits of data.

0 Next, it is checked whether the other FIFO buffer 33 has output data.

@If there is output data in the FIFO buffer 33, DMA operation 1 is sent to the local DMA controller 1! ! seek

@Local DMA controller 1 responds, reads data from FIFO buffer 33, and transfers the data to local RAM 4.

Here, the demultiplexer 38 is set to pass the lower 8-bit data.

If there is any remaining data, the operation continues; if there is no remaining data, the operation of the input/output control device ends.

〔Effect of the invention〕

According to the present invention, it is possible to efficiently transfer data between devices having different data transfer widths, and it has the excellent effect of improving system performance.

[Brief explanation of drawings]

Fig. 1 is a diagram showing the configuration of an input/output control device according to an embodiment of the present invention, Fig. 2 is a diagram showing an example of the configuration of a conventional input/output control device, and Fig. 3 is a diagram showing a FIFO buffer and its peripheral circuits. Figure 4 is a diagram showing an example of an execution flowchart, Figure 5 is a diagram showing details (
a) to (d) are diagrams showing flowcharts of various operations. In FIG. 1, 1 is a local DMA controller, 4 is a local DMA controller, and 4 is a local DMA controller.
is local RAM, 10 is control register, 12
is a local bus, 14 is a host bus, 17 is a FIFO buffer, 19 is a multiplexer/demultiplexer, 2
0 is the FIFO controller. Example of execution flowchart E 1 Figure 4 ebLt Data read meeting X+4 Flowchart 1
1E5e] (α) ebLmu Light Gravity 20-Chart @5 (2) (C) No. 59 (d)

Claims (3)

[Claims] (1) An input/output control device having an n-bit width local bus (12), the input/output control device having a 2n-bit width host bus (12);
4) in an input/output control device that transfers data with a host system having first and second first-in first-out (FIFO) buffers (32, 33) each storing n-bit data. A first-in bus is provided in parallel between the 2n-bit width host bus (14) and the n-bit width local bus (12), and when performing n-bit width data transfer with the host system, a predetermined one first-in bus is provided. A first-out (FIFO) buffer (33) is used to transfer data, and when performing a 2n-bit width data transfer with the host system, both the first and second first-in first-out (FIFO) buffers (FIFO) are used. An input/output control device characterized in that it is configured to transfer data using buffers (32, 33). (2) A local RAM used as a temporary buffer and a local DMA controller are provided, and the local RAM is controlled by the local DMA controller.
M and the above first-in, first-out (FIFO)
) buffer, and the first-in/first-out (FI
The input/output control device according to claim 1, wherein the input/output control device performs data transfer between the FO) buffer and the host bus 2. (3) A control register is provided for storing command information from the host system, and the host DMA controller and local DMA controller are controlled based on the contents of the control register, and the n-bit width or 2. The input/output control device according to claim 2, wherein the input/output control device performs data transfer with a width of 2n bits.