JP3605987B2 - Image processing device - Google Patents

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to an image processing apparatus such as a printer, a copying machine, a facsimile apparatus, and more particularly to an image processing apparatus having a high-speed image processing function.
[0002]
[Prior art]
In conventional image processing apparatuses, especially in recent printers, the resolution and printing speed have been improved. In connecting the printer to the system bus of the image data input / output device, data transfer speed is one of the most important factors. Has become. Therefore, to realize high-speed printing, it is necessary to increase the data transfer speed including image processing.
[0003]
As a method for improving the data transfer speed, for example, Japanese Patent Application Laid-Open No. 4-256186 discloses a method in which a control device compresses data and transfers the data to a printer to reduce the amount of transferred data. In this method, a compression circuit in the control device locally reads out image data stored in an image memory, compresses the image data, and outputs it to a printer. On the printer side, the received compressed image data is expanded by an expansion circuit and printed out.
[0004]
[Problems to be solved by the invention]
In the conventional method as described above, the maximum transfer speed to the printer is determined by the time required for the compression process because there is no scheme for improving the transfer speed in the compression process itself.
[0005]
As a method for compressing data to be sent to a printer, a method shown in FIG. 8 can be generally considered. A CPU 52, a ROM 53, a RAM 54, a compression device 55, and a decompression device 56 are connected to the system bus 51, and a printer 57 is connected to the decompression device 56. The compression device 55 includes a bus bridge 61, a first FIFO 62, a compression circuit 63, and a second FIFO 64.
[0006]
The operation of this method will be described. During the data reading period from the RAM 54, the data read from the RAM 54 is sent to the first FIFO 62 via the bus bridge 61. When data is stored in the first FIFO 62, the compression circuit 63 performs a compression operation, and the compressed data is stored in the second FIFO 64. Next, during a period of writing data to the RAM 54, the compressed data stored in the second FIFO 64 is written to the RAM 54 via the bus bridge 61. The period for reading data from the RAM 54 and the period for writing data to the RAM 54 are alternately performed. On the other hand, the compressed data stored in the RAM 54 is sent to the printer 57 via the decompression device 56. According to this method, the amount of data sent from the RAM 54 to the decompression device 56 is reduced, and the transfer speed is improved.
[0007]
However, during the period of writing data to the RAM 54, there is no data in the first FIFO 62, so that the data compression operation by the compression circuit 63 is not performed, and there is a problem that the compression processing speed is slow. In addition, there is a problem that high-speed image processing / printing is difficult.
[0008]
SUMMARY OF THE INVENTION It is an object of the present invention to provide an image processing apparatus capable of solving the above-mentioned problems of the related art and performing high-speed image processing.
[0009]
[Means for Solving the Problems]
In order to achieve the above object, according to the present invention, in an image processing apparatus, a system bus, a buffer storage unit for temporarily holding image data input from the system bus, and a buffer read from the buffer storage unit Image processing means for inputting data and performing compression or decompression processing; data transfer between the respective means so that input of data to the image processing means and input / output of data to / from the system bus operate in parallel. And a separating means controlled by the control means and disconnecting the connection between the system bus and the buffer memory means at least during the parallel operation.
[0010]
According to the present invention, with the above-described configuration, input of data to the image processing unit and input and output of data to and from the system bus can be performed in parallel, and the operating efficiency of the image processing unit is reduced. It can be greatly increased. As a result, the processing speed of the image processing device can be improved.
[0011]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, the present invention will be described in detail with reference to the drawings. FIG. 2 is a block diagram showing an example of a system configuration of a printer control device which is an embodiment of the image processing device of the present invention.
The CPU 1 controls the entire apparatus according to a control program stored in the ROM 2. The RAM 3 is used as a work area for processing and a buffer for image information. The disk device (DISK) 4 is, for example, a hard disk device and stores image information or programs. The printer 5 is a device that prints the input image information, and the decompression device 6 restores, for example, the compressed image data stored in the RAM 3 or DISK 4 to the original data and outputs the original data.
[0012]
The compression device 7 receives image information from the RAM 3 or DISK 4, performs compression processing, and outputs the compressed image data to the RAM 3 or DISK 4 again, as will be described in detail later. The LAN interface circuit 8 is a circuit for interfacing with an external LAN 10, and image information to be printed is input from another workstation connected to the LAN 10 through the circuit. The system bus 9 connects each circuit in the device. The image information may be input using a detachable information recording medium such as a one-to-one parallel or serial interface circuit or a floppy disk drive, in addition to the LAN.
[0013]
FIG. 1 is a block diagram showing a configuration of the compression device 7 of FIG. The bus bridge 20 is connected between the system bus 9 and the local bus B21, and performs two functions. One is to execute a process of writing / reading parameters and status information from the CPU 1 to the control unit 28 and the compression processing unit 26, and the other is to execute a DMA transfer process. In the DMA transfer processing, the bus bridge 20 becomes a bus master on the system and executes read / write access to the RAM 3 (or DISK 4). For this purpose, a data buffer exists in the bus bridge 20.
[0014]
The gate circuit 22 serving as a separating unit is a tri-state bus driver connected between the local bus B21 and the local bus A23 and outputting data on the local bus B21 to the local bus A23 under the control of the control unit 28. is there. The RAM buffer 24 serving as a buffer storage unit is a RAM for storing image data DMA-transferred from the RAM 3 via the gate circuit 22, and is composed of, for example, an SRAM having a capacity of 32 kbytes. The FIFO-2 (25) is a FIFO buffer having a capacity of, for example, about 4 kbytes, and buffers image data read from the RAM buffer 24 under the control of the control unit 28.
[0015]
The compression processing unit 26, which is an image processing unit, reads out image data from the FIFO-2 (25), performs compression processing using a general compression algorithm based on a method instructed by the CPU 1, and performs FIFO-1 (27). ). The FIFO-1 (27) is a FIFO buffer also having a capacity of about 4 kbytes. When a certain amount (for example, half) of data is accumulated in the FIFO buffer, the data is locally controlled by the control unit 28. DMA transfer is performed to the RAM 3 (or DISK 4) via the bus B21 and the bus bridge 20. The control unit 28 controls the image data transfer operation so that the compression processing unit 26 can execute the compression processing without delay by the configuration and operation described below.
[0016]
FIG. 3 is a block diagram illustrating a configuration of the control unit 28. The arbiter A31 is a circuit that arbitrates contention for access to the local bus A23, receives bus request signals from the plurality of control units 34 and 35, and sends the bus request signal to only one of the control units in accordance with a method described later with reference to FIG. This is a circuit for giving a bus use permission signal. The arbiter A31 also performs write / read timing control on the RAM buffer 24.
[0017]
The arbiter B30 is a circuit that arbitrates contention for access to the local bus B21, receives bus request signals from a plurality of control units 32 to 34, and uses the bus to only one of the control units in a round-robin manner. This is a circuit for giving a permission signal. The permission signal is continuously output until the permitted control unit completes one transfer cycle.
[0018]
The slave write control unit 32 receives write / read access to the register inside the control unit 28 or the compression processing unit 26 sent from the CPU 1 via the bus bridge 20, and uses an arbiter to use the local bus B 21. A bus request signal is sent to B30. Then, with permission, the slave write cycle shown by the dotted line (3) in FIG. 1 is controlled. When the transfer is completed, the arbiter B 30 is notified of the end.
[0019]
The DMA write controller 33 monitors, for example, the amount of data stored in the FIFO-1 and starts transfer control when half or more of the data has been stored. When the bus use permission is obtained from the arbiter B30, the FIFO-1 ( 27), the compressed image data is read out, and as shown by a dotted line (4) in FIG. 1, a DMA write cycle for performing a DMA transfer to the RAM 3 via the local bus B21 and the bus bridge 20 is executed. When the buffer of the bus bridge 20 becomes full, this cycle is interrupted, and at the end of the cycle, an end notification is sent to the arbiter B30.
[0020]
The DMA read control unit 34 is activated by an instruction from the CPU 1 and controls DMA transfer from the RAM 3 to the RAM buffer 24. For this purpose, it is necessary to obtain bus use permission from both the arbiter A31 and the arbiter B30. When the permission is obtained, the gate circuit 22 is controlled to a conductive state, a write address and a write control signal are given to the RAM buffer 24, and output from the bus bridge 20 as shown by a dotted line (1) in FIG. A DMA read (RAM buffer write) cycle for writing image data to the RAM buffer 24 is executed.
[0021]
The RAM read control unit 35 reads image data from the RAM buffer 24 under the control of the CPU 1 and transfers the read image data to the FIFO-2 (25) as indicated by a dotted line (2) in FIG. The control unit 28 having the functions as described above can be created by individual hardware, and can also be realized by a storage program type control device.
[0022]
FIG. 5 is a flowchart showing operations (processes) of the DMA read control unit 34, the RAM read control unit 35, and the arbiter A31 of FIG. This processing is roughly divided into three parts. S1 to S7 in FIG. 5 are RAM buffer read cycles, S8 to S12 are loops for waiting for a use permission signal from the arbiter A31, and S13 to S20 are DMA read (RAM buffer write) cycles. It is. In step S1, it is determined whether or not a read counter R_CTR in the RAM read control unit 35 is zero. This R_CTR sets the read data amount (for example, 4 kbytes) from the CPU 1 and is decremented by one every time one (for example, one byte) is transferred. Therefore, if R_CTR is not 0, data to be transferred remains.
[0023]
If the determination result in step S1 is negative (there is data), the process proceeds to step S2, and a predetermined value is preset in an interval counter R_INT for counting the number of data transferred in one read cycle. For example, if the number of data transferred in one read cycle is 4 bytes, a predetermined value 4 is preset in R_INT. In step S3, the RAM read controller 35 outputs an output enable signal (OE) and a chip select signal (CS) to the RAM buffer 24, and simultaneously outputs a read address. Based on these signals, one image data is read from the RAM buffer 24 and stored in the FIFO-2.
[0024]
In step S4, R_CTR and R_INT are each decremented by one. Here, the read address is also sequentially updated (+1) and reset when it reaches the maximum value. In step S5, it is determined whether or not R_CTR is 0. If the result is affirmative, the process proceeds to step S8, but if negative, the process proceeds to step S6. In step S6, it is determined whether or not R_INT is 0. If the result is affirmative, the process proceeds to step S8, but if negative, the process proceeds to step S7. In step S7, it is determined whether or not there is a free space in the FIFO-2. If the result is negative, the process proceeds to step S8. If the result is affirmative, the process returns to step S3 to return the data from the RAM buffer 24. Is repeated.
[0025]
In step S8, it is determined whether the write counter W_CTR in the DMA write control unit 33 is 0 or not. This W_CTR is set by the CPU 1 for the amount of write data, and is decremented by one each time one is transferred. Therefore, if W_CTR is not 0, data to be DMA-transferred remains. If the determination result in step S8 is affirmative, the process returns to step S1, but if negative, the process proceeds to step S9. In step S9, a predetermined value (for example, 4) is preset in an interval counter W_INT that counts the number of data transferred in one write cycle.
[0026]
In step S10, it is determined whether or not the bus use permission signal W_GNT from the arbiter B30 is 1 (permitted). If the result is affirmative, the process proceeds to step S15; Move to S11. In step S11, W_INT is decremented by one, and in step S12, it is determined whether W_INT is 0. If the result is negative, the process returns to step S10, but if the result is positive, the process proceeds to step S1. I do. The processing of steps S10 to S12 is a processing for waiting for a use permission signal from the arbiter B. When the W_GNT signal becomes 1, the flow immediately proceeds to the write processing of step S15 and thereafter.
[0027]
In step S13, it is determined whether W_CTR is 0. If the determination result is affirmative, the process returns to step S1, but if negative, the process proceeds to step S14. In step S14, it is determined whether or not W_GNT is 1, and if affirmative, the process proceeds to step S15. In step S15, a predetermined value (for example, 4) is preset in the interval counter W_INT. In step S16, the DMA read controller 34 outputs a write enable signal (WE) and a chip select signal (CS) to the RAM buffer 24, and simultaneously outputs a write address. Further, it outputs an operation signal to the gate circuit 22. Based on these signals, image data is stored in the RAM buffer 24 from the bus bridge 20 via the local bus B and the gate circuit 22.
[0028]
In step S17, W_CTR and W_INT are each decremented by one. Here, the write address is also sequentially updated (+1) and reset when it reaches the maximum value. In step S18, it is determined whether or not W_CTR is 0. If the result is affirmative, the process proceeds to step S1, but if negative, the process proceeds to step S19. In step S19, it is determined whether or not W_INT is 0. If the result is affirmative, the process proceeds to step S1, but if negative, the process proceeds to step S20. In step S20, it is determined whether there is no data to be transferred to the buffer in the bus bridge 20, and if the result is negative, the process proceeds to step S16, but if affirmative, the process returns to step S1.
[0029]
By performing the above processing, when there is data to be transferred, the data is transferred collectively by a preset number in each interval counter, and when there is both a write request and a read request, the data is alternately transmitted. It is processed.
[0030]
FIG. 7 is a time chart showing the operation of the RAM buffer 24. FIG. 7A shows an operation when the CPU 1 sets an arbitrary value to R_CTR when image data has already been stored in the RAM buffer 24. In such a case, the process proceeds from step S1 to S2 in the flowchart of FIG. 5, and the image data is read out a number of times (for example, four times) preset in R_INT. When R_INT becomes 0, the process proceeds from step S6 to S8, and when W_CTR is 0, the process returns to S1 again to repeat the read cycle. Note that even when a value is set only for W_CTR, the write cycle of steps S16 to S20 is repeated in the same manner as in FIG. 7A.
[0031]
FIG. 7B shows a process in the case where a value is set to W_CTR from the CPU 1 during execution of the read cycle of FIG. 7A. When writing to W_CTR is performed at an arbitrary timing, the process proceeds from step S6. The process proceeds to steps S8 and S9. Then, a bus request signal is sent to the arbiter B30, but the permission signal W_GNT does not become 1 while the bus is being used by another control unit. Therefore, it waits until W_GNT becomes 1 by the number of times preset in W_INT in the maximum step S9. This is to prevent the reading process of steps S3 to S7 from being executed and the data in FIFO-2 to be lost when waiting indefinitely.
[0032]
When W_GNT becomes 1, the process proceeds to step S15, and the image data is written to the RAM buffer 24 the number of times preset in W_INT. Then, when W_INT becomes 0, the process returns from step S19 to step S1, and if R_CTR is not 0, the process proceeds to step S2, and a read process is executed this time. Therefore, when both R_CTR and W_CTR are not 0, the read cycle and the write cycle are executed alternately, and the number of transfer data in each cycle can be set arbitrarily.
[0033]
FIG. 4 is a waveform diagram showing signal waveforms in each transfer cycle. The left side of FIG. 4 shows a write cycle (1) to the RAM buffer 24. In this case, the local bus B shown above and the local bus A shown below operate synchronously. First, the control unit 28 sends a buffer read enable signal BUF_RE (negative logic: 0 is active and the other signals are the same) to the bus bridge 20 and synchronizes the clock signal CLK with the data from the buffer in the bus bridge 20. Are sequentially output to the local bus B. The control unit 28 makes the gate circuit 22 conductive by the gate enable signal GATE_EN, and outputs data on the bus B21 to the bus A23. In addition, WE and CS signals and a write address signal are generated for the RAM buffer 24 to write data on the bus A. In this example, four data are written in one write cycle, but the number can be arbitrarily set to R_INT.
[0034]
The right side of FIG. 4 shows the operation of the read cycle (2) from the RAM buffer 24 and the DMA write cycle (4). In this case, the control unit 28 turns off the gate circuit 22 with the gate enable signal GATE_EN to disconnect the bus B21 from the bus A23. Therefore, these operations (2) and (4) can be performed simultaneously. Note that the slave write cycle (3) can be executed simultaneously with the read cycle (2).
[0035]
The embodiments have been described above, but the following modified examples are also conceivable. FIG. 6 is a circuit diagram showing a second embodiment of the gate circuit 22. In a printer or the like, for example, when performing double-sided printing, it is necessary to rotate an image by 180 degrees. In this case, it is necessary to reverse the arrangement of the image data and the pixel arrangement in each image data. In the second embodiment of the gate circuit, this pixel data array inverting means is provided in the gate circuit 22.
[0036]
6, the image data on the local bus B21 received by the bus receiver 30 is connected to the input terminal group A of the selector 31 in the same arrangement, and the most significant bit is located at the least significant bit position, and The bits are rearranged so as to be at the most significant bit position and connected to the input terminal group B of the selector 31. The selector 31 outputs data of the terminal group A to the output terminal group O if the control signal input to the terminal C from the control unit 28 is 0, and outputs data of the terminal group B if it is 1. The tristate bus driver circuit 32 outputs data output from the selector 31 to the local bus A based on a control signal from the control unit.
[0037]
With such a circuit, the bit arrangement in each image data can be inverted. For example, if the image data in the RAM 3 is rearranged under the control of the CPU 1, image data inverted by 180 degrees can be obtained. Alternatively, if the entire page of image data can be stored in the RAM buffer 24, the data may be rearranged by reversing the order of writing and reading to the RAM buffer 24.
[0038]
As described in detail above, in the image processing apparatus of the present embodiment, the local bus A23 and the local bus B21 can be separated by the gate circuit 22. For this reason, the transfer of data from the RAM buffer 24 to the FIFO-2 and the transfer of the compressed data stored in the FIFO-1 to the RAM 3 can be performed in parallel, without stopping the compression processing unit 26. Alternatively, since the operation can be performed in a short stop period, the compression processing speed can be greatly improved as compared with the related art. Further, in the image processing apparatus of the present embodiment, the data input speed to the RAM buffer 24 and the data transfer speed to the FIFO-25 can be independently controlled by adjusting the value of the interval counter, for example. In addition, it is possible to control so that the processing in the compression processing unit is executed without delay. The permission of the arbiter B is required at the time of the writing process to the RAM buffer 24, but the waiting time can be reduced by, for example, transmitting the bus request in advance.
[0039]
As an embodiment, an example in which compression processing is performed as image processing is disclosed, but the present invention is applicable to, for example, decompression processing and other arbitrary image processing.
[0040]
【The invention's effect】
As described above, according to the present invention, in the image processing apparatus, the separation unit is provided so that the connection between the system bus and the buffer storage unit can be disconnected. The input of data to the image processing means for performing processing and the input and output of data including the data after the image processing to and from the system bus can be operated in parallel, and the operating efficiency of the image processing means can be reduced. It can be greatly improved as compared with the conventional one. Therefore, the image processing apparatus can be operated at a high speed. Further, since the speed of the image processing apparatus does not become a bottleneck in the transfer speed to the printer, there is an effect that the printing speed can be increased as a whole.
[Brief description of the drawings]
FIG. 1 is a block diagram showing a configuration of a compression device 7 in FIG.
FIG. 2 is a block diagram illustrating a system configuration example of a printer control device according to an embodiment of the present invention.
FIG. 3 is a block diagram showing a configuration of a control unit 28.
FIG. 4 is a waveform chart showing signal waveforms in each transfer cycle.
FIG. 5 is a flowchart showing operations of a DMA read control unit, a RAM read control unit 35, and an arbiter A31.
FIG. 6 is a circuit diagram showing a second embodiment of the gate circuit 22.
FIG. 7 is a time chart showing the operation of the RAM buffer 24.
FIG. 8 is a block diagram illustrating a conventional system configuration example of a printer control device.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 ... CPU, 2 ... ROM, 3 ... RAM, 4 ... disk device, 5 ... printer, 6 ... expansion device, 7 ... compression device, 8 ... LAN interface, 9 ... system bus, 10 ... LAN, 20 ... bus bridge, 21 local bus B, 22 gate circuit, 23 local bus A, 24 RAM buffer, 25 FIFO-2, 26 compression processing unit, 27 FIFO-1, 28 control unit

Claims (13)

In an image processing apparatus in which image data is compressed and stored, decompressed and output to a printing device,
A system bus,
Buffer storage means for temporarily holding image data input from the system bus;
Image processing means for inputting data read from the buffer storage means and performing compression or expansion processing,
Control means for controlling data transfer between the means, so that input of data to the image processing means and input and output of data to and from the system bus operate in parallel;
An image processing apparatus controlled by the control unit, comprising: a separating unit that disconnects the connection between the system bus and the buffer storage unit at least during the parallel operation. The image processing apparatus according to claim 1,
When transferring the image data from the system bus to the buffer storage unit, the control unit deactivates the separation unit and connects the system bus to the buffer storage unit. apparatus. The image processing apparatus according to claim 1,
The image processing apparatus according to claim 1, wherein the data input / output to / from the system bus when the separation unit is operated includes data processed by the image processing unit. In an image processing apparatus in which image data is compressed and stored, decompressed and output to a printing device,
A system bus,
A local bus connected to the system bus;
Buffer storage means provided on a local bus for storing compressed data or decompressed data transmitted from the system bus;
Image processing means for compressing or expanding compressed data or decompressed data read from the buffer storage means;
Separating means for separating said local bus connection between the buffer storage means and said system bus,
Control means for controlling a transfer operation of transferring the compressed data or the decompressed data transmitted from the system bus to the system bus via the local bus;
An image processing apparatus comprising: The image processing apparatus according to claim 4,
Wherein, when the image data transfer from the system bus to the buffer memory means is adapted to connect the system bus and the buffer memory means, when the image data output from the buffer storage unit to the image processing means, the image processing apparatus being characterized in that so as to control the separation means to isolate the connection between the system bus and the buffer memory means. The image processing apparatus according to claim 4,
Wherein said control means includes a wherein when buffering the image data output from the storage means to the compression and expansion processing means, and adapted to concurrently process the transfer to the system bus of the image data processed by said image processing means Image processing device. The image processing apparatus according to claim 4,
The image processing apparatus according to claim 1, wherein said control means performs parallel processing of data transfer from said system bus to said control means when outputting image data from said buffer storage means to said image processing means. The image processing apparatus according to claim 4,
An image processing apparatus, wherein the control means reads out the compressed data or the decompressed data from the buffer storage means while inverting the data and outputs the data to the image processing means. The image processing apparatus according to claim 4,
An image processing apparatus according to claim 1, wherein said buffer storage means is constituted by an SRAM. The image processing apparatus according to claim 4,
The front and rear stages of the image processing unit, an image processing apparatus characterized in that a FIFO. The image processing apparatus according to claim 4,
The separation unit separates the local bus into a first local bus connected to the system bus and a second local bus connected to the buffer unit and the image processing unit. Image processing device. The image processing apparatus according to claim 4,
An image processing apparatus according to claim 1, wherein said separating means includes a data array inverting means. The image processing apparatus according to claim 4,
An image processing apparatus according to claim 1, wherein said separating means is constituted by a gate circuit.

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