JP2567428B2 - Data transfer rate converter - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to data transfer between a serial signal processing device and a parallel signal processing device having different transmission speeds, in order to perform highly efficient and highly reliable data transfer. Speed converter.

[Conventional technology]

A conventional composite printer system is disclosed in Japanese Patent Laid-Open No. 60-54042.
As described in the publication, serial signals such as image data read by an image scanner (hereinafter referred to as IS) and video data printed by an optical printer cannot be stopped midway when the signal transfer is started. Further, for such a serial signal, a central processing unit (hereinafter referred to as a CPU) that processes data handles the data in units of 8 bits or 16 bits, and therefore serial / parallel conversion of data is necessary. Among them, for parallel / serial conversion (P / S), D _P : Transfer rate of parallel signal per word sent by CPU (word / second) N _B : Number of parallel bits (bit / word) D _S : External Transfer rate of serial signal to be sent to (bits / second) T _PS : If the time required for P / S (seconds / word) is set, when sending data directly from the CPU to the outside without any intervention, Must be satisfied. However, in the composite printer system, the transmission speeds of the two are very different, so that the expression (1) is not satisfied. Therefore, conventionally, as shown in FIG. 2, a buffer memory (hereinafter referred to as BM) 101 is provided between a CPU and an external device, and data is temporarily stored in the buffer memory 101 to eliminate the difference in transmission speed between the two. Is taking. This BM uses first-in first-out (FIFO) memory and alternate buffer memory.

When this BM is used, it is generally assumed that D _W : BM writing speed (word / second) and D _R : BM reading speed (word / second) Must be satisfied. When D _W = D _R , BM is not necessary, but as described above, it is not generally established in the composite printer system. However, when D _W > D _R , it becomes possible to send a continuous serial signal to the outside. At this time, the memory capacity M (word) of BM is determined in consideration of the least common multiple of D _W and D _R and the data editing time T _P (second) by the program. That is, M = a · D _W = b · D _R (3) (a and b are coprime and the unit corresponds to time) and To obtain M.

Such data input to the BM is performed by program data transfer or direct memory access (DMA) control.

[Problems to be solved by the invention]

Since data transfer under software control is determined by the machine cycle of the CPU, D _W has a limit. Therefore, when sending a serial signal to the outside at high speed and continuously,
The BM requires a memory capacity for each work, that is, a minimum memory capacity for performing a predetermined job. This corresponds to that in Expression (3), when D _R is increased, the value of M obtained from the least common multiple of D _W and D _R is also increased.
The increase in memory capacity cannot meet the demand for system miniaturization. Also, when using DMA transfer, there is a problem that D _W cannot be freely controlled because it is determined by hardware.

The object of the present invention is to provide a CP
A buffer memory (BM) that uses a data transfer rate converter that can transfer serial signals with reasonable and high reliability to the outside even if the U side has a program-based data transfer rate and has a small capacity. To provide.

[Means for Solving the Problems] The above-mentioned problem is that in the data transfer rate conversion device including the buffer memory and the parallel / serial converter as an interface of the composite printer system, the buffer memory and the parallel / serial converter are connected to each other. It is solved by providing a transmission rate converter that changes the number of parallel signals to change the transmission rate of signals.

[Action]

A transmission rate converter that changes the number of parallel signals is provided between the buffer memory and the parallel / serial converter of the composite printer system, and the transmission rate of the signal to the parallel / serial converter is changed.

〔Example〕

An embodiment according to the present invention will be described below with reference to FIGS. 1 and 3 to 8.

Embodiment 1 FIG. 1 is an embodiment of data transfer rate conversion. CPU3
Data sent from 01 at program data transfer rate (D _W ) 106 is temporarily buffer FIFO memory (BM)
Stored in 101. Thereafter, in synchronization with the external clock 110, the data output based on the read address output from the conversion control circuit 102 is temporarily latched by the latch 103, The parallel signal output circuit in byte units until the number of parallel bits (N _B ) that is predetermined to satisfy
Sent to 4. This N _B value is preset in the conversion control circuit 102 by the N _B setting signal 114 from the CPU 301.

The conversion control circuit 102 confirms that the data sent to the parallel signal output circuit 104 has reached N _B or more, and then outputs the output of the parallel signal output circuit 104. Set to. Then, the parallel signal output circuit 104 To the parallel / serial converter (P / S) 105. After that, the parallel signal output circuit 104 The rest of the signals that exceed is shifted to the upper bits. Also, The number of remaining signals beyond is sent to the conversion control circuit 102,
This is the initial value for bit number control.

On the other hand, the P / S 105 converts a parallel signal into a serial signal and transmits the serial signal to the outside at a transmission rate (D _S ) 111. Thus BM101 and P / S1
It is possible to control the transfer rate conversion efficiency when 05 is converted to a serial signal.

Next, the conditions for converting the data transfer rate will be described with reference to FIG.

The transfer rate of the parallel data in the parallel bit number converter 112 (D _L) 108 (word / s), also, the transfer rate of data read from BM101 During D _L , Holds. Also, compared with the conventional method, this method The number of signals to send in parallel so that From the formula (2) by increasing The memory capacity (word) obtained from the least common multiple of is M> ... (7).

Thus, the number of parallel bits in equation (6) Controls the data transfer rate for parallel and serial signals. As a result, as shown in the equation (7), the memory capacity of the BM101 can be reduced. This also leads to miniaturization of the composite printer system.

The above relationship applies when data is transferred from the CPU side to the outside, but also holds when data is transferred from the outside to the CPU side. The word shown in units means the number of signals (bits) when sending in parallel, which is determined by work units.

Embodiment 2 FIG. 3 is an example in which a speed conversion buffer 308 having the configuration shown in FIG. 1 is provided between the optical printer 309 and the CPU 301, and information on the system side is transferred to the printer side.

The CPU 301 issues a print request signal to the optical printer 309,
If printing is ready, the optical printer 309 returns a print enable signal to the CPU 301. After receiving this signal, the CPU 301 starts sending data to the speed conversion buffer 308 via the data bus 303.

Writing parallel data to the speed conversion buffer 308
When the decode signal 304 becomes valid, it is performed in synchronization with the system clock 305 of the CPU 301. On the other hand, the reading is executed in synchronization with the clock of the optical printer 309 regardless of the writing timing 307.

The above timing is shown in FIG. When the vertical synchronizing signal 31 becomes valid, the reset signal 32 initializes the write / read pointer of the FIFO memory. For writing, based on the write enable signal 34 created based on the horizontal synchronizing signal 35, the data B _W for the I block is written like parallel video data 33. On the other hand, read is a signal
35 is synchronized with the clock signal 36 of the optical printer 309, and after parallel / serial conversion, is output as serial video data 37.

As described above, the data transfer from the CPU 301 to the optical printer 309 uses the signal 31 and the signal 35 as reference signals, but writing and reading timings are performed at independent transfer rates.

Third Embodiment FIG. 5 shows an example applied to data transfer between an image scanner (IS) 501 and a CPU 301.

The basic operation is almost the same as in FIG. 3, and the CPU 301 issues a transmission request signal to the IS 501, while the IS 501 transmits a transmission start signal and a serial signal of image data to the CPU 301. Writing to the speed conversion buffer 308 is executed after serial / parallel conversion based on the clock signal of IS501.

On the other hand, reading is output to the data bus 303 in synchronization with the system clock 305 regardless of the writing timing.

The above timing is shown in FIG. Upon receiving the transmission request from the CPU 301, the IS 501 validates the ready signal 51, synchronizes with the line synchronization signal 52, and outputs the image data 53 as a serial signal.
Send

For image data, 16 lines of signal 52 are set to 1 line in consideration of the capacity of the FIFO memory and the transfer rate of serial signals and parallel signals.
It is treated as a block. The serial signal 53 continuously sent from the IS 501 is converted into a parallel signal by this method and written in the FIFO memory like the image data signal 55. After that, the image data signal 57 is transferred to the main memory of the CPU 301 based on the processing sequence of the CPU 301. The write pointer of the FIFO memory is initialized by the reset signal 54 and the read pointer is initialized by the reset signal 56 for each block.

Conventionally, when performing data transfer as shown in FIG. 3 and FIG. 5, a pair of memories having the capacities obtained from equations (3) and (4) are prepared, and data is written to one BM under software control. It is common to use the so-called alternate buffer method, in which the other BM reads out under hardware control when it is out.

On the other hand, in this method, by using it in combination with one FIFO memory having the capacity obtained from the equations (3) and (4), the data transfer equivalent to the alternate buffer can be realized as described above. In other words, this method requires less than half the memory capacity of the BM101 compared to the replacement buffer method. This is also clear from equation (7). Also, since the address control of the speed conversion buffer 308 becomes simple,
The size of the buffer device can be reduced.

Fourth Embodiment FIG. 7 shows an example in which the IS501, the optical printer 309, and the CPU 301 are integrated. The speed conversion buffer 308 is composed of the following five parts.

FIFO memory 703. A parallel bit conversion unit 704 that performs parallel / serial conversion and changes the number of signals sent in parallel to control the data transfer rate. A parallel / serial conversion unit 705 for converting data in parallel / serial or serial / parallel. A signal control unit 702 that controls hardware and software write and read operations to and from the FIFO memory 703. A decoder 701 that selects a signal from the CPU 301.

 An example of data processing using this device is shown below.

(1) When receiving an image signal from Image Scanner (IS) 501 Signal speed of serial signal sent from IS501 and CPU301
The number of signals to be parallel-converted from equations (3), (4), and (6) (the number of bits in equation (6)) in consideration of the processing speed of (Corresponding to the above) and set the number in the parallel bit conversion unit 704. Further, the parallel / serial conversion unit 705 is set to serial / parallel conversion. After that, the image data of the IS501 is transferred to the main memory through the speed conversion buffer 308 based on the program by the method described with reference to FIGS.

(2) When printing a document created by the composite printer system by the optical printer 309: Determine the number of signals for parallel / serial conversion as in the case of (1), and set the number in the parallel bit conversion unit 704. To do. Further, the parallel / serial conversion unit 705 is set to parallel / serial conversion. After that, the text data in the main memory is transferred to the optical printer 309 through the speed conversion buffer 308 based on the program by the method described with reference to FIGS.

As described above, by using this device, it becomes possible to arbitrarily send and receive serial data between the CPU and an external device (optical printer or IS).
Eliminates the need to set the IS buffer memory separately.
Therefore, the device becomes smaller.

FIG. 8 is a detailed example of the speed conversion buffer 308 shown in FIG. The signal control unit 702 and the parallel bit conversion unit 704 in FIG. 7 are the R / W permission signal generation circuit 801 and the bit control circuit 803 in FIG. 8, respectively. CPU301 is the reset of FIFO memory 703, R / W
Permission, parallel data load to parallel / serial conversion circuit 805,
Controls such as serial / parallel or parallel / serial conversion settings. Furthermore, the number of bits shown in equation (6) To realize speed conversion with the bit control circuit 803 Set. This bit control circuit 803, as described in the principle diagram of the speed conversion buffer in FIG. 1, reads the data read from the FIFO memory 703 in units of 1 byte (8 bits), and outputs the data in an arbitrary number of bits. Set to and output. The frequency divider circuit 802 reads and writes from the FIFO memory 703 based on the transmission / reception clock of the external device control bus 806 according to the command of the CPU 301, and further outputs a timing signal 804 for loading parallel data to the parallel / serial conversion circuit 805. create. Thus, the number of signals to send in parallel By operating, the effect as described in FIG. 7 can be obtained.

Thus, according to the present invention as described in detail in Embodiments 1 to 4, according to the present invention, from software control to hardware control,
Or in the reverse data transfer, when converting serial / parallel, by changing the number of signals sent in parallel, it is possible to eliminate the difference in transfer speed. Transfer is possible, and there is an effect that data can be transferred with a smaller buffer memory capacity than before. Further, since the entire data transfer can be managed by program control, there is an effect that the system is downsized and the reliability of the transferred data is increased.

〔The invention's effect〕

By providing a transmission speed converter that changes the number of parallel signals between the buffer memory and the parallel / serial converter of the composite printer system, an external device connected to the parallel / serial converter with a buffer memory having a smaller capacity than before is provided. There is an excellent effect that a reasonable signal transmission speed corresponding to the device can be obtained.

[Brief description of drawings]

FIG. 1 is a block diagram of a speed conversion buffer showing a first embodiment according to the present invention, FIG. 2 is a block diagram showing a conventional buffer system, and FIG. 3 is an optical printer showing the second embodiment.
FIG. 4 is a block diagram of an embodiment of speed conversion with a CPU, FIG. 4 is a control sequence of FIG. 3, and FIG. 5 is an image of an embodiment of FIG. Block diagram, FIG. 6 is a control sequence of FIG. 5, FIG. 7 is a block diagram of an embodiment of speed conversion between the image scanner, the optical printer and the CPU showing the embodiment of FIG. 4, and FIG. FIG. 8 is a block diagram of the speed conversion buffer section of FIG. 7. 101 …… buffer memory (BM), 102 …… conversion control circuit,
103 …… Latch, 104 …… Parallel signal output circuit, 105 …… Parallel / serial conversion (P / S), 106 …… Write speed (D _W ), 10
7 ... Reading speed 108 ...... parallel data transfer rate (D _L), 109 ...... parallel bits 110 ...... external clock, 111 ...... serial signal transmission speed (D _S), 112 ...... parallel bit number converter 113 ...... external device.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Kunio Sato 4026 Kuji Town, Hitachi City, Hitachi City, Ibaraki Hitachi Research Laboratory, Hitachi, Ltd. (56) References JP-A-62-106560 (JP, A)

Claims (2)

(57) [Claims] 1. A data transfer rate converter comprising a buffer memory and a parallel / serial converter as an interface of a composite printer system, wherein the number of parallel signals is changed between the buffer memory and the parallel / serial converter. A data transfer rate conversion device comprising a transfer rate converter for changing the transfer rate. 2. The data transfer rate conversion device according to claim 1, wherein the buffer memory is a first-in first-out memory.