JPH01130650A - Data transfer speed converter - Google Patents

Abstract

PURPOSE:To obtain a rational transmission speed of a signal corresponding to an external device with a small-capacity buffer memory by providing a transmission speed converter varying the number of parallel signals between a buffer memory and a parallel/serial converter. CONSTITUTION:Data sent at a data transmission speed 106 by a program from a CPU 301 is stored in a buffer memory 103. After data outputted based on a read address outputted from a conversion control circuit 102 synchronously with an external clock 110 is latched by a latch 103, the result is sent to a parallel signal output circuit 104. After it is confirmed that data sent to the parallel signal output circuit 104 reaches a value NB or over set by an NB setting signal 113 from the CPU 301, an output of the parallel signal output circuit 104 is set. Thus, the data transfer with an external device is attained by the program control at the CPU side and the data is transferred by less buffer memory capacity.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to data transfer between a serial signal processing device and a parallel signal processing device having different transmission speeds, and is directed to highly efficient and reliable data transfer. The present invention relates to a speed conversion device.

[Conventional technology]

In the conventional multifunction printer system,
As described in Publication No. 42, an image scanner (hereinafter referred to as I
Serial signals such as image data read in S) or video data printed on an optical printer cannot be stopped midway once signal transfer is started. In addition, a central processing unit (hereinafter referred to as CPU) is used to process data for such serial signals.
) handles data in 8-bit or 16-bit units, so serial/parallel conversion of data is required. Among them, regarding parallel/serial conversion (hereinafter referred to as P/S).

Dp: Transfer rate of parallel signals per word sent by the CPU (7 seconds per word) NB: Number of parallel bits (bits/word) Ds: Transfer rate of serial signals sent to the outside (bits/second) Tps: To P/S The time required (seconds/word) is C
When data is sent directly from the PU to the outside without any intervention, NB TPS must hold true. However, in a multifunction printer system, the transmission speeds of the two systems are significantly different, so equation (1) does not hold true. Therefore, conventionally, as shown in Figure 2, a buffer memory (hereinafter referred to as BM) 101 is provided between the CPU and the external device, and data is stored there temporally, thereby eliminating the difference in transmission speed between the two. I am taking a method to do so. This B
For M, a first-in, first-out (hereinafter referred to as FIF○) memory or alternate buffer memory is used.

When this BM is used, Dw: Speed of writing to BM (1f seconds) DR: Speed of reading from BM (1f seconds) - NB Tps must hold true for boat fishing. When Dw=DR, BM is not required, but as described above, this is generally not true in multifunction printer systems. However, when Dw>DR, the external
It becomes possible to send continuous serial signals. At this time, the memory capacity M (words) of the BM is determined in consideration of the least common multiple of Dw and DR and the data editing time T p (seconds) by the program.

That is.

M=a-Dw=b-DR-(3) (a and b are relatively prime, and the unit corresponds to time) and ILDw to find M.

Such data input to the BM is performed by data transfer by a program or by direct memory access (hereinafter referred to as DMA) control.

[Problem that the invention seeks to solve]

Since data transfer under software control is determined by the CPU machine cycle, there is a limit to Dw. Therefore, when sending serial signals to the outside at high speed and continuously,
The BM requires a memory capacity per job, that is, a minimum memory capacity to perform a given job. This is 1
In equation (3), increasing DR corresponds to increasing the value of M calculated from the least common multiple of Dw and DR. An increase in memory capacity cannot meet the demand for system miniaturization. Furthermore, when DMA transfer is used, there is a problem that Dw cannot be freely controlled because it is determined by hardware.

An object of the present invention is to provide a CP printer in a multifunction printer system.
On the U side, even if the data transfer rate is determined by the program, a buffer memory (BM) is used that uses a data transfer rate conversion device that enables rational and highly reliable serial signal transfer to the outside and requires a small capacity. ).

[Means for solving problems]

The above problem can be solved by changing the number of parallel signals between the buffer memory and the parallel/serial converter in a data transfer rate converter that is used as an interface for a multifunction printer system and consists of a buffer memory and a parallel/serial converter. This is solved by providing a transmission speed converter that changes the transmission speed of the transmission speed.

[Effect]

A transmission speed converter for changing the number of parallel signals is provided between the buffer memory and the parallel/serial converter of the composite printer system, and the transmission speed of the signal to the parallel/serial converter is changed.

〔Example〕

An embodiment of the present invention will be described below with reference to FIGS. 1 and 3 to 8.

Example 1 FIG. 1 shows one embodiment of data rate conversion.

The data transfer rate (D
w) The data sent in 106 is temporarily stored in the buffer memory (BM) 101 of FIF○. Thereafter, in synchronization with the external clock 110, the data output based on the read address output from the conversion control circuit 102 is temporarily latched in the latch 103, and then parallelized in a predetermined manner to satisfy NB TPS. Number of bits (
N B) or more, the signals are sent to the parallel signal output circuit 104 in byte units. The value of this NB is set in advance by CPU3.
01 to the conversion control circuit 102 by the NB setting signal 113.
is set to .

After confirming that the data sent to the parallel signal output circuit 104 is equal to or greater than N8, the conversion control circuit 102 sets the output of the parallel signal output circuit 104 to the pin 109. and,
The parallel signal output circuit 104 sends the signal of the leprosy 109 to the parallel/serial converter (P/5) 105. Thereafter, the parallel signal output circuit 104 shifts the remaining signals exceeding Na1.09 to the upper bits. Further, the remaining number of signals exceeding 109 is sent to the conversion control circuit 102 and becomes the initial value for bit number control.

On the other hand, P/S 105 converts parallel signals to serial signals,
It is transmitted externally at a transmission rate (Ds) of 111.

In this way, connect BMIOI and P/5105 to the serial signal number.
Transfer rate conversion efficiency when converting can be controlled.

Next, conditions for data transfer rate conversion will be described using FIG.

The transfer speed of parallel data in the parallel bit number converter 112 is (DL) 108 (word 7 seconds), and BMIOI
α5i) 107(
word 7 seconds) then DIl, DR.

Between D.

The formula holds true. Also, compared to the conventional method, this method has N
B) By increasing the number of signals sent in parallel (bits/word) so that N 'gL (word) is M>wealth
...(7).

In this way, the number of parallel bits in equation (6) controls the data transfer rate of parallel signals and serial signals. As a result, as shown in equation (7), the memory capacity of BMlol can be reduced.

This also leads to miniaturization of the multifunction printer system.

The above relationship applies when data is transferred from the CPU side to the outside, but it also holds true when data is transferred from the outside to the CPU side. Also, the word shown in units means the number of signals (number of bits) when sent in parallel, which is determined by the work unit.

Embodiment 2 FIG. 3 shows a first
A speed conversion buffer 308 having the configuration shown in the figure is provided,
This is an example of transferring information on the system side to the printer side.

The CPU 301 issues a print request signal to the optical printer 309, and if printing is ready, the optical printer 309 sends a print request signal to the optical printer 309.
A print ready signal is sent back to 01. After receiving this signal, CPU 301 starts sending data to speed conversion buffer 308 through data bus 303.

Writing parallel data to the speed conversion buffer 308 is as follows:
When the decode signal 304 becomes valid, it is performed in synchronization with the system clock 305 of the CPU 301. On the other hand 1. Reading is executed in synchronization with the clock of the optical printer 309, regardless of the write timing 307.

The above timing is shown in FIG. Vertical sync, signal 31
When FI becomes valid, reset signal 32 causes FI
Initialize the FO memory write and read pointers. Writing is performed by writing one block of data By like parallel video data 33 based on a write enable signal 34 created based on a horizontal synchronization signal 35. On the other hand, reading is performed in synchronization with the signal 35 and the clock signal 36 of the optical printer 309, and after parallel/serial conversion, the data is output as serial video data 37.

In this way, the data transfer from the CPU 301 to the optical printer 309 uses the signals 31 and 35 as reference signals, but the writing/writing and reading timings are performed at independent transfer speeds.

Embodiment 3 FIG. 5 shows an image scanner (Is) 501 and a CPU 30.
An example applied to data transfer between 1 and 1 is shown below.

The basic operation is almost the same as in Figure 3, from CPU301 to l5.
In response, the l5501 sends a transmission start signal and a serial signal of image data to the CPU 301. Writing to the speed conversion buffer 308 is executed after serial/parallel conversion is performed based on the clock signal of the l5501.

On the other hand, read data is output to the data bus 303 in synchronization with the system clock 305, regardless of the write timing.

The above timing is shown in FIG. Upon receiving the transmission request from the CPU 301, the l5501 enables the ready signal 51 and transmits the image data 53 in a serial signal in synchronization with the line synchronization signal 52.

Due to the relationship between the capacity of the FIFO memory and the transfer speed of serial signals and parallel signals, the image data is processed in such a way that 16 lines of the signal 52 are treated as one block. l5
A serial signal 53 that is continuously sent from 501 is converted into a parallel signal by this method, and is then written into the FIFO memory like a data signal 55. After that, the CPU
Based on the processing sequence 301, the image data signal 57 is transferred to the main memory of the CPU 301. The write pointer of the FIFO memory is initialized for each block by a reset signal 54, and the read pointer is initialized by a reset signal 56, respectively.

Conventionally, when performing data transfer as shown in Figures 3 and 5, a pair of memories with capacities determined from equations (3) and (4) was prepared, and data was written to one BM under software control. It has been common practice to use a so-called alternating buffer system in which data is read from the other BM under hardware control.

In contrast, by using this method in combination with one FIFO memory having the capacity determined from equations (3) and (4), it is possible to achieve data transfer equivalent to the alternating buffer as described above. In other words, compared to the alternating buffer method, this method requires less than half the memory capacity of the BMIO1. This is also clear from equation (7). Furthermore, since the address control of the speed conversion buffer 308 is simplified, the size of the buffer device can be reduced.

Embodiment 4 Figure 7 shows l5501, optical printer 309, and CPU3.
This is an example in which 01 is integrated. The speed conversion buffer 308 is composed of the following five parts.

■FIFO memory 703° ■Parallel bit converter 704° that performs parallel/serial conversion to change the number of signals sent in parallel and control data transfer speed ■Parallel/serial converter that performs parallel/serial or serial/parallel conversion of data Conversion section 705゜■FIF
A signal control unit 702 that controls hardware and software write and read operations to the O memory 703
Decoder 701 for selecting a signal from CPU 301 An example of data processing using this device is shown below.

(1) When receiving an image signal from the image scanner (IS) 501 The signal speed and CP of the serial signal sent from the 15501
Considering the processing speed of U301 and the size of PIFO memory 703, the number of signals to be parallelized (corresponding to the bit hostility in equation (6)) is calculated from equations (3), (4), and (6). and set the number in the parallel bit conversion unit 704. Furthermore, the parallel/serial converter 705 is set to serial/parallel conversion. Thereafter, the image data of 15501 is transferred to the main memory through the speed conversion buffer 308 based on the program using the method described in FIG. 5.6.

(2) When printing a document created with a multifunction printer system using the optical printer 309 Determine the number of signals to be subjected to parallel/serial conversion in the same way as in case (1), and set that number in the parallel bit conversion unit 704 do. Furthermore, the parallel/serial converter 705 is set to perform parallel/serial conversion. Thereafter, the text data in the main memory is transferred to the optical printer 309 through the speed conversion buffer 308 based on the program using the method described in FIGS.

By using this device as described above, serial data can be sent and received arbitrarily between the CPU and external devices (optical printers and IS), and the optical printer buffer and ZS buffer can be set separately. There will be no need. Therefore, the device also becomes smaller.

FIG. 8 is a detailed example of the speed conversion buffer 308 of FIG. 7. Signal control unit 702 and parallel bit conversion unit 70 in FIG.
4 are the R/W permission signal generation circuits 801.
This is a bit control circuit 803. CPU301 is FIFO
It controls the reset of the memory 703, R/W permission, parallel data loading to the parallel/serial conversion circuit 805, setting of serial/parallel or parallel/serial conversion, etc. Furthermore, the formula (6
) In order to realize speed conversion using the bit number (C) 109 shown in ), a floor 109 is set in the bit control circuit 803.

This bit control circuit 803 is connected to the FIFO memory 7 as explained in the principle diagram of the speed conversion buffer in FIG.
The data read out in units of 1 byte (8 bits) from 03 is set to an arbitrary number of bits Na and output. Frequency divider circuit 8
02 is based on the transmission/reception clock of the external device control bus 806 according to instructions from the CPU 301.
A timing signal 804 is generated for reading and writing from the IFO memory 703 and for loading parallel data into the parallel/serial conversion circuit 805. In this way, by manipulating the number of signals sent in parallel (No in equation (6)), the seventh
The effects described in the figure can be obtained.

As described in detail in the first to fourth embodiments, according to the present invention, data transfer from software control to hardware control or vice versa.

When performing serial/parallel conversion, it is possible to eliminate the difference in transfer speed by varying the number of signals sent in parallel, making it possible to transfer data to and from the outside through program control on the CPU side, which is faster than before. It also has the effect of being able to transfer data with a small buffer memory capacity. Furthermore, since the entire data transfer can be managed under program control, the system can be made smaller and the reliability of the transferred data can be increased.

〔Effect of the invention〕

By providing a transmission speed converter that changes the number of parallel signals between the buffer memory and the parallel/serial converter of a multifunction printer system, it is possible to connect the parallel/serial converter with a smaller capacity buffer memory than before. This has the excellent effect of being able to obtain a reasonable signal transmission speed that is compatible with external equipment.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a speed conversion buffer showing a first embodiment of the present invention, FIG. 2 is a block diagram showing a conventional buffer system, and FIG. 3 is a block diagram of an optical printer and a CPU showing a second embodiment. 4 is a block diagram of an embodiment of speed conversion between the image scanner and the CPU, FIG. 4 is a block diagram of the control sequence of FIG. 3, and FIG. 5 is a block diagram of an embodiment of speed conversion between the image scanner and the CPU, 6 is a control sequence of FIG. 5, FIG. 7 is a block diagram of an embodiment of speed conversion between an image scanner, an optical printer, and a CPU showing the embodiment of FIG. 4, and FIG. 8 is a block diagram of a speed conversion embodiment of the embodiment of FIG. FIG. 3 is a block diagram of a speed conversion buffer section. 101... Buffer memory (BM), 102... Conversion control circuit, 103... Latch, 104... Parallel signal output circuit, 105... Parallel/serial conversion (P/S),
106... Write speed (Dw), 107... Read speed (DR), 108... Parallel data transfer rate (DL), 109... Parallel bit (Na), 11
0...External clock, 111...Serial signal transmission speed (Ds), l'l 2...Parallel bit number converter,
113...External device.

Claims (1)

[Scope of Claims] 1. In a data transfer rate conversion device serving as an interface for a multifunction printer system and comprising a buffer memory and a parallel/serial converter, the buffer memory and the parallel/serial converter
1. A data transfer rate conversion device comprising a transmission rate converter that changes the number of parallel signals between serial converters to change the signal transmission rate. 2. The data transfer rate conversion device according to claim 1, wherein the buffer memory is a first-in, first-out memory.