JPH02307151A - Processor system - Google Patents

Abstract

PURPOSE:To attain a fast and highly reliable data transfer system having the high expansion properties by transferring each transmission/reception signal of the data transfer cycle in a frame form and in a synchronous way and secur ing an asynchronous way for an entire cycle. CONSTITUTION:A master 1, a slave 21 and a slave 22 are connected to a bus B and a control line L. Then a control frame and an address frame are sent from the master 1 in a synchronizing transfer system where the rise of a strobe signal is sent to the slave together with each frame. At the same time, the slave received a frame from the master 1 transmits an answer signal after the end of the corresponding process to complete a cycle. Thus an entire data transfer cycle is equal to an asynchronous transfer system. In such a way, the advantages are mixed together between the synchronous and asynchronous systems. As a result, the high speed properties, the high reliability, and the expansion properties are improved in a processor system.

Description

[Detailed Description of the Invention] <Industrial Application Field> The present invention relates to a processor system in which a plurality of master CPU cards, slave I10 cards, etc. are connected to a system bus, and particularly relates to a processor system in which a plurality of master CPU cards, slave I10 cards, etc. are connected to a system bus. Master,
This improves the data transfer method between slaves.

<Prior art> The data transfer method on the system bus in which the master and slave are connected is one of the following two methods: (a) synchronous transfer method and (b) asynchronous transfer method. It is common to use

(a) Synchronous transfer method The master side reads and writes data unilaterally to the slave side according to the master's transfer sequence.The system has a simple circuit configuration and can operate at high speed.

(b) Asynchronous transfer method When reading or writing data from the master side, an access request is issued to the slave side, the slave side returns a response signal, and data transfer is executed between the master and slave. Data transfer can be performed reliably, high reliability can be ensured, and it is also possible to support slaves with different response speeds.

These synchronous transfer methods and asynchronous transfer methods are used depending on the system specifications.

<Problems to be Solved by the Invention> The above-mentioned synchronous transfer method and asynchronous transfer method have the following problems.

(b) Synchronous transfer method Synchronous transfer is based on the fact that the master reads and writes data unilaterally regardless of whether the slave is in normal or abnormal state.
There is a problem that even if a slave side is malfunctioning, processing continues as it is, causing malfunctions in the entire system.In addition, when multiple slaves with different response speeds are installed, each slave has to transfer data at a different speed. There is a problem that the design at this time is complicated.

(b) Asynchronous transfer method The asynchronous transfer method transmits and receives signals between the master and slave at each stage of data transfer, such as when starting data transfer, during data transfer, and when ending data transfer. Since data is transferred while checking the response, there is a problem in that the operating speed cannot be improved. Furthermore, when this asynchronous transfer method is adopted, the status of the destination device and the transfer status are often notified to the source device, but as the number of information to be notified increases, the number of cables and bus There is also the problem that the number of pieces increases and the cost increases.

As described above, the synchronous transfer method and the asynchronous transfer method each have advantages and disadvantages, and the use of these methods makes system design difficult.

The present invention aims to eliminate the drawbacks of both the synchronous transfer method and the asynchronous transfer method, as well as combine the advantages of both, and to achieve high speed, high reliability, and scalability in a processor system. The purpose is to realize a rich data transfer method.

Means for Solving the Problems> The present invention transfers each transmission/reception signal in a data transfer cycle in a frame format in a synchronous manner, making the entire cycle asynchronous.The specific configuration thereof is as follows. That's right.

That is, in a processor system in which at least one master and at least one slave are connected to each other via a system bus, the master and the slave are provided with strobe signal generating means, and various control information is provided in the processor system. A control frame containing a control frame, an address frame specifying an address, and a data frame containing data are set, and when transferring data between the master and the slave, each frame is sequentially transmitted together with the strobe signal, and the data frame is transmitted sequentially together with the strobe signal. The processor system is characterized in that upon completion of the transfer, the slave sends a reply signal to the master to complete the data transfer cycle.

Further, the reply signal may be set in a frame format, and the slave may store an internal status signal as a status in this frame and send it back to the master together with the strobe signal.

Effect〉 The processor system of the present invention operates as follows.

In a data transfer cycle (data read cycle) in which the master side reads data from the slave side, a control frame, address, etc. are transferred from the master side to the slave side.
The frame is transmitted in a synchronous manner along with a strobe signal, and the slave side transmits the data frame and reply signal to the master side together with the strobe signal when the data transmission preparation is completed, making this entire cycle an asynchronous transfer method.

In a data transfer cycle (data write cycle) in which the master side writes data to the slave side, a control frame, address frame, and data frame are sent from the master side to the slave side in a synchronous manner along with a strobe signal, and the slave side When data reception is completed, a reply signal is sent to the master side, and the entire cycle is an asynchronous transfer method.

A status frame may be set as the reply signal, and the internal state of the slave may be stored in this status frame and transmitted together with the strobe signal.

<Embodiment> FIG. 1 is a conceptual diagram of the configuration of a processor system implementing the present invention.

In this example, master 1, slave 21, slave 22
is connected to bus B and control lines.

The master 1 is a microprocessor card or the like, and includes a control diagram 1111 that includes a CPU, etc., a strobe signal generation circuit 13 that issues a strobe signal to the control line, a data multiplexer 12 that is involved in data transfer on bus B, and a slave 21. .22.

The slave 21 is an I10 card or the like, and includes a control circuit 211 that controls the operation of the slave, a data multiplexer 212, a strobe signal generation circuit 213 that issues a strobe signal to the control line, and a status output that outputs a status signal to the master 1 side. It has a register 214.

Similarly, the slave 22 includes a control circuit 221, a data multiplexer 222, and a strobe signal generation circuit 22.
3. It has a status output register 224.

It is assumed that bus B uses an 8-bit line (07-DO).

Next, details of the operation of the processor system of the present invention configured as described above will be explained using the time charts shown in FIGS. 2(a) and 2(b).

As shown in this figure, the data transfer cycle consists of a control frame FO, address frames Fl, F2,
Data frame F3. F4. Status Frame F
It consists of four types of frames: 5. Each frame is sent out on bus B (07-Do) with 1 byte (8 bits) and receives the strobe signal 5 from the master or slave.
TB-“Valid on the rising edge of LH.

Also, a frame signal rnHII, a data direction designation signal D
DIll= is a signal sent to the control line by master 1, and frame signal FR)l- is a signal that indicates the first frame at the falling edge and the last frame at the rising edge during the data transfer cycle. , the data direction designation signal [ID1n* indicates frame transfer from the master to the slave when it is "L" during a data transfer cycle, and indicates frame transfer from the slave to the master when it is "L".

Note that the access signal AC3- is a signal indicating that the slave has been accessed, and is connected to the back plane (not shown).
Wired ored on the bus.

First, the data transfer cycle (data read cycle from master 1 to slave 21 or 22) shown in FIG. 2 (a>) will be explained.

Master 1 sends out a control frame FO (1 byte) on bus B (07-00) and sends out strobe signal STB*"L" on the control line.

The control frame FO contains transfer mode bits such as read/write distinction, data size (2 bytes or 4 bytes), data type (data or control), and byte bits that enable access in byte units.
Enable bits etc. are set. This control frame FO becomes valid at the rising edge SO of strobe signal STB*"L'".

Master 1 then sends address frame 1.2 (Fl,
F2) is sent. Address frame 1.2 (Ft
, F2) consists of a 2-byte frame, guaranteeing an address space of 128 bytes.

This address frame 1.2 (Fl, F2) is the rising edge S1°S of the strobe signal STB*“L”.
2 becomes valid.

The operation in period T1 up to this point is master 1fl! This is the first action.

The slave that received these frames FO, Fl, and F2 determines whether or not it has been selected during period T2.
If you are selected, perform data transmission preparation processing, etc.

The selected slave sends data frame 1.2 (F3.F4) containing data to be sent on bus B in period T3.
Send out. These data frames 1.2 are each made valid by the rising edge S3.34 of the strobe signal 5TB-L'' sent from the slave. In this example, the data sent to the master is 2 bytes (1
6 bits), and in the case of 4 bytes (32 bits), the number of data frames to be sent is four.

Finally, this slave sends a reply signal indicating the end of data transmission to the master 1 side, but this reply signal may be the rising edge S5 of the strobe signal sTBm, or the newly set status frame. F5
It may also be the rising edge S5 of the strobe signal 5TBII "L".

In this example, a status frame F5 is sent as a reply signal, and this 1-byte frame contains the internal status of the slave. B signal, for example, error status, card failure status, online/offline for data transfer to printer.

Various status information such as presence or absence of paper, operation in progress, presence or absence of toner, and normal completion of transfer can be set.

Master 1, which receives and receives such a reply signal, knows that the data transfer has ended and completes this cycle.

If a transfer cycle error is set in the status signal, the master performs a retry data transfer cycle, and if a card operation error is set, performs processing such as command reset. .

As described above, from master 1 to control frame F
O, when sending address frames Fl and F2,
This is a synchronous transfer method in which each of these frames and the strobe signal 5TB-"L" are transmitted to the slave at the rising edge. Furthermore, the slave that has received the frame from the master side transmits a reply signal after completing the corresponding processing and ends the cycle, so the entire data transfer cycle is an asynchronous transfer method.

Furthermore, when setting and using a status frame as a reply signal to master 1, various information is written in this 1 byte and sent to bus B (07-DO), so a new status frame is required for the reply signal. There is no need to install cable lines, buses, etc.

In this way, it is possible to realize a data transfer method that combines the advantages of the synchronous transfer method and the asynchronous transfer method.

FIG. 2(b) shows the connection from master 1 to slave 21 or 22.
This is a cycle (data write cycle) for transferring data to the host.

In this cycle, master 1 sends control frame FO, address frames Fl, F2, data frame F3 . F4 respectively strobe signal s'rB zero"
Transfer to the slave side at the rise of “L” (period 'I
'4) L, the selected slave performs the necessary processing (period T5) and then sends a return signal (strobe signal STB* "L" or status frame F5 and strobe signal "14'") to the master 1 side. The data transfer cycle is completed by sending the data (period T6).

In this way, when each frame is sent out, synchronous transfer is performed using the strobe signal from the master or slave, and the entire data transfer cycle is an asynchronous transfer method, making it possible to combine the advantages of both methods.

In the example shown in FIG. 1, two slaves are connected to one master, but two or more slaves may be connected to one master.

<Effects of the Invention> According to the processor system of the present invention, the following effects can be obtained.

Since each frame is transferred synchronously, high-speed transfer is possible, and during the entire transfer cycle, the response between the master and slave can be checked for each cycle by asynchronous transfer, which improves system reliability. can. Furthermore, by using the asynchronous transfer method, a system can be constructed even if slaves with different response speeds are installed.

Furthermore, since a status frame is sent on the bus when a response signal is returned, there is no need to newly install a signal line for the response signal, which can reduce costs. Additionally, this status frame can be expanded to include data width, further improving system reliability.

[Brief explanation of the drawing]

FIG. 1 is an example of a processor system embodying the present invention, and FIGS. 2(a) and 2(b) are time charts showing the operation of the processor system of the present invention. 1...Master, 21.22...Slave, 11, 2
11, 221...control circuit, 12, 212, 22
2...Data multiplexer, 13, 213, 2
23...Slobe signal generation circuit, 14...Status input register,

Claims (2)

[Claims] (1) In a processor system in which at least one master and at least one slave are interconnected via a system bus, the master and the slave are provided with strobe signal generating means, and various controls are provided. setting a control frame containing information, an address frame specifying an address, and a data frame containing data, and sequentially transmitting each frame together with the strobe signal when transferring data between the master and the slave; A processor system characterized in that upon completion of data transfer, the slave sends a reply signal to the master to complete the data transfer cycle. (2) The processor according to claim (1), wherein the reply signal is set in a frame format, and the slave stores an internal state signal as a status in the frame and sends it back to the master together with a strobe signal. ·system.