JPH06266605A - Storage device - Google Patents

Abstract

PURPOSE:To transfer data of one group where addresses are discontinuous at high speed. CONSTITUTION:A memory board 1 is provided with FIFO for address 2 which accumulates write addresses AW or read addresses AR received from an address bus Ba and sequentially outputs them to the address port of a memory 4 and bidirectional FIFO for data 3 which accumulates write data DW received from a data bus Bd in accordance with the write addresses DW and sequentially output them to the data port of the memory 4 or accumulates read data DR which are read from the memory 4 in accordance with the read addresses AR and sequentially transmits them to the data bus Bd.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a storage device, and more particularly to a storage device capable of performing high-speed writing and reading to and from a memory even when addresses of a group of data are discontinuous.

[0002]

2. Description of the Related Art FIG. 7 is a general configuration diagram for transferring a group of data stored in a first memory 72 to a second memory 73. The CPU 71 supplies the read address AR to the address port of the first memory 72 via the address bus Ba, and reads the read data DR from the first memory 72 via the data bus Bd. Next, the CPU 71 applies the write address AW to the address port of the second memory 73 via the address bus Ba, and writes the write data DW (= previous read data D to the second memory 73 via the data bus Bd).
R) is written. This is repeated for all the groups of data.

FIG. 8 is a block diagram showing a case where, when addresses of a group of data stored in the first memory 72 are consecutive, the addresses are transferred to the second memory 73 at high speed.
The CPU 71 uses the continuous address generator 8 of the first memory 72.
The first address of the read address and the data amount are given to 1,
On the other hand, the start address of the write address and the data amount are given to the continuous address generator 83 of the second memory 73. The continuous address generator 81 of the first memory 72 sequentially generates the read address AR from the top address of the read address and supplies it to the address port of the first memory 72. The read data DR read from the first memory 72 correspondingly is
It is stored in the FIFO 82 of the first memory 72. The FIFO 82 of the first memory 72 sends the accumulated read data DR to the data bus Bd. FIFO8 of the second memory 73
Reference numeral 4 stores the read data DR received from the data bus Bd. Continuous address generator 83 of the second memory 73
Generates a write address AW sequentially from the start address of the write address and supplies it to the address port of the second memory 73. In response to this, the write data DW (= previous read data D fetched from the FIFO 84 of the second memory 73)
R) is written in the second memory 73.

Another conventional example of this type of high-speed transfer is as follows.
For example, SSBLT in VMEbus and Futur
There is a packet mode in ebus +, and the data itself to be transferred has a synchronization bit, which enables data transfer up to 100 MTr / s (transfer / sec) without a synchronization clock common to each board.

[0005]

In the configuration of FIG. 7, since the procedure for acquiring and releasing the bus is performed for each data, the ratio of this procedure time becomes large, which is not suitable for high-speed transfer. There is. On the other hand, the configuration of FIG.
In BLT and the like, high-speed transfer is possible because the procedure for acquiring and releasing the bus is performed for multiple data.
Since the address of a group of data needs to be continuous, for example, cutting out a part of data from a two-dimensional image or cutting out a two-dimensional image from a three-dimensional image,
There is a problem that it cannot be applied when the addresses of a group of data are discontinuous. SUMMARY OF THE INVENTION An object of the present invention is to provide a storage device capable of high speed writing and reading even for a group of data having discontinuous addresses.

[0006]

SUMMARY OF THE INVENTION In a first aspect, the present invention provides a storage device comprising a memory which is connected to an address bus and a data bus and which can be randomly accessed,
Address F for accumulating the write address or read address received from the address bus and sequentially outputting the write address or read address to the address port of the memory
The IFO and the write data received from the data bus corresponding to the write address are accumulated and sequentially output to the data port of the memory, or the read data read from the memory corresponding to the read address is accumulated. There is provided a storage device including a data FIFO that is sequentially output to a data bus.

According to a second aspect, the present invention relates to an address generator for generating a transfer source address or a transfer destination address in a storage device having a randomly accessible memory, which is connected to an address bus and a data bus, and an address generator thereof. An address FIFO for accumulating the transfer source address or the transfer destination address input from the address generator and transmitting them to the address bus in order, and a write received from the data bus corresponding to the transfer source address transmitted to the address bus A data FIFO for accumulating data and sequentially outputting the data to a data port of the memory, or accumulating read data read from the memory and sequentially transmitting the data to the address bus of the transfer destination address. A storage device characterized by the above.

[0008]

In the memory device of the present invention according to the first aspect, the address FIFO is added to the data transfer FIFO.
Is equipped with. This address FIFO receives write addresses or read addresses from the address bus, accumulates them, and outputs them to the address port of the memory in order. That is, a plurality of random addresses can be received collectively and given to the memory in order. Therefore, even a group of data having discontinuous addresses can be collectively transferred on the bus, which enables high-speed transfer.

In the memory device of the present invention according to the second aspect, an address generator and an address FIFO are provided in addition to the data transfer FIFO. The address generator generates a transfer source address or a transfer destination address,
The address FIFO receives the transfer source address or the transfer destination address from the address generator, accumulates them, and outputs them in order to the address bus. That is, a plurality of random addresses can be collectively sent to the address bus. Therefore, even a group of data having discontinuous addresses can be collectively transferred on the bus, which enables high-speed transfer.

[0010]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to the embodiments shown in the drawings. The present invention is not limited to this.

First Embodiment FIG. 1 is a block diagram of a main part of a bus system 101 including a memory board 1 which realizes a storage device according to a first embodiment of the present invention. In this bus system 101, the bus B is
The bus master M and the memory board 1 are connected. The bus B is composed of a data bus Bd, an address bus Ba, and a control bus Bc. The bus master M sends the data to be transferred to the memory board 1 to the data bus Bd and the write address of the data to the address bus Ba. Further, the bus master M takes in the data sent from the memory board 1 to the data bus Bd.

The memory board 1 has an address FIFO 2
The data bidirectional FIFO 3, the memory 4, and the protocol controller 5 are provided. FI for address
The FO 2 accumulates the write address AW or the read address AR received from the address bus Ba and sequentially outputs them to the address port of the memory 4. The data bidirectional FIFO 3 accumulates the write data received from the data bus Bd, and sequentially outputs the data as write data DW to the data port of the memory 4. This output is performed in synchronization with the output of the write address AW from the address FIFO 2. Further, the data bidirectional FIFO 3 accumulates the read data DR read from the data port of the memory 4 in response to the output of the read address AR from the address FIFO 2, and the read data DR is stored in the data bus B.
It is sent to d in order. The protocol controller 5 controls the operation of each unit based on the control signal received from the control bus Bc.

In FIG. 2, the bus master M stores a group of data "D1", "D3", "D5", "D7" on the memory board 1.
3 is a timing chart when writing is performed. The bus master M, as shown in FIG.
Address bus B for "1", "A3", "A5", "A7"
In addition to outputting to a, write data “D1”, “D3”, “D5”, and “D7” are output to the data bus Bd as shown in FIG. The write address is "A1",
“A3”, “A5”, and “A7” are used to indicate that the write addresses may be discontinuous. In the memory board 1, the address FIFO 2 uses the write addresses “A1” and “A” received from the address bus Ba.
3 ”,“ A5 ”, and“ A7 ”are accumulated. Also, the data bidirectional FIFO 3 stores the write data “D1”, “D3”, “D5”, “D7” received from the data bus Bd. Then, the address FIFO 2 has the write addresses “A1”, “A3”, as shown in FIG.
“A5” and “A7” are sequentially output to the address port of the memory 4. In addition, the data bidirectional FIFO 3 has the write data “D1”, “D3”, as shown in FIG.
“D5” and “D7” are sequentially output to the data port of the memory 4.

In FIG. 3, the bus master M reads the read addresses "A2", "A4", "A6", "A" from the memory board 1.
8 is a timing chart when reading a group of data of "8". The bus master M reads the read addresses "A2", "A4", "A6", "A8" as shown in FIG.
Is transmitted to the address bus Ba. The read addresses are "A2", "A4", "A6", and "A8".
This is because it indicates that the read addresses may be discontinuous. In the memory board 1, the address FIFO 2 is
The read address “A received from the address bus Ba
2 ”,“ A4 ”,“ A6 ”, and“ A8 ”are accumulated. Then, as shown in FIG. 3B, the read address “A2”,
“A4”, “A6”, and “A8” are output to the address port of the memory 4. The bidirectional data FIFO 3 for data reads the read data “A2”, “A4”, “A6”, and “A8” from the data port of the memory 4 as shown in FIG. "D2", "D4", "D
6 ”and“ D8 ”are accumulated. Then, as shown in (d) of FIG. 3, read data “D2”, “D4”, “D6”,
"D8" is sequentially transmitted to the data bus Bd. The bus master M reads the read data “D2”, “D” on the data bus Bd.
4 ”,“ D6 ”, and“ D8 ”are fetched.

As described above, even a group of data having discontinuous addresses can be collectively transferred on the bus B, which enables high-speed transfer.

-Second Embodiment- FIG. 4 is a block diagram of a main part of a bus system 201 including a memory board 11A which realizes a storage device according to a second embodiment of the present invention. In the bus system 201, the bus B is connected to the memory boards 11A, 11B and 11C. The bus B is a data bus Bd and an address bus Ba.
And a control bus Bc. Memory board 11
A is operable as both a bus slave and a bus master, and has an address generator 16 and an address bidirectional F.
The IFO 12, the data bidirectional FIFO 13, the memory 4, the protocol controller 15, and the address switch 17 are provided.

The address generator 16 is used for the memory board 11
When A operates as a bus slave, it is stopped. On the other hand, the address generator 16 uses the memory board 11A.
Operate as a bus master, the address AS on the address bus Ba of the other device that is the transfer source of the group of write data or the address AS on the address bus Ba of the other device that is the transfer destination of the group of read data. Is generated and output to the address bidirectional FIFO 12. Further, a write address AW on the memory 4 to write the group of write data or a read address AR on the memory 4 to read the group of read data is generated and output to the address switcher 17.

When the memory board 11A operates as a bus slave, the address bidirectional FIFO 12 accumulates the write address AW or the read address AR received from the address bus Ba, and stores them in the address switcher 1.
Output to 7 in order. On the other hand, address bidirectional FIFO1
When the memory board 11A operates as a bus master, 2 stores the transfer source address AS or the transfer destination address AS input from the address generator 16 and sends it out to the address bus Ba in order.

The address switch 17 is used for the memory board 11
When A operates as a bus slave, the address output from the address bidirectional FIFO 12 is input to the address port of the memory 4. On the other hand, the address switch 17
When the memory board 11A operates as a bus master, the address output from the address generator 16 is stored in the memory 4
Enter the address port of.

When the memory board 11A operates as a bus slave, the data bidirectional FIFO 13 accumulates the write data received from the data bus Bd and sequentially outputs it as the write data DW to the data port of the memory 4. . This output is a bidirectional FIFO for address 12
Is performed in synchronization with the output of the write address AW from. The data bidirectional FIFO 13 is an address FIFO.
The read data DR read from the data port of the memory 4 corresponding to the output of the read address AR from O12 is accumulated, and the read data DR is sequentially sent to the data bus Bd. On the other hand, when the memory board 11A operates as a bus master, the data bidirectional FIFO 13 is sent from another device to the data bus Bb in response to the transfer source address AS sent to the address bus Ba by the address bidirectional FIFO 12. The received data is received and accumulated, and is sequentially output to the data port of the memory 4 as the write data DW. This output is performed in synchronization with the output of the write address AW from the address generator 16. Further, the data bidirectional FIFO 13 accumulates the read data DR read from the data port of the memory 4 in response to the output of the read address AR from the address generator 16, and transfers the read data DR to the data bus Bd. Send in order. This output is performed in synchronization with the output of the transfer destination address AS from the address bidirectional FIFO 12.

The protocol controller 15 controls the operation of each part based on the control signal received from the control bus Bc.

The memory boards 11B and 11C take in the read data sent from the memory board 11A to the data bus Bd in correspondence with the transfer destination address sent from the memory board 11A to the address bus Ba. Further, the memory boards 11B and 11C send the data corresponding to the transfer source address sent from the memory board 11A to the address bus Ba to the data bus Bd.

When the memory board 11A operates as a bus slave, the timing chart is the same as that of the first embodiment shown in FIGS. On the other hand, when the memory board 11A operates as a bus master, the timing charts of FIGS.

In FIG. 5, the memory board 11A transfers source addresses "A1 '", "A3'", "A5 '", "A7'".
A group of write data “D” from another device corresponding to
It is a timing chart at the time of writing "1", "D3", "D5", and "D7" in write address "A1", "A3", "A5", and "A7". As shown in FIG. 5A, the address generator 16 of the memory board 11A has transfer source addresses "A1 '", "A3'", "A5 '", "A".
7 ′ ”is generated and output to the address bidirectional FIFO 12. The address bidirectional FIFO 12 accumulates the transfer source addresses “A1 ′”, “A3 ′”, “A5 ′”, and “A7 ′”, and sequentially sends them to the address bus Ba as shown in FIG. 5B. . The data bidirectional FIFO 13 has the transfer source addresses “A1 ′”, “A3 ′”, “A5 ′”,
Data "D" sent from the other device onto the data bus Bd as shown in FIG. 5C corresponding to "A7 '".
1 ”,“ D3 ”,“ D5 ”, and“ D7 ”are accumulated. Next, the address generator 16 causes the write addresses "A1", "A3", "A5", "A" as shown in FIG.
7 ”is generated and input to the address port of the memory 4 via the address switch 17. In synchronism with this, the data bidirectional FIFO 13 causes the write data "D1", "D3", "D5", "D" as shown in (e) of FIG.
7 ”are sequentially input to the data ports of the memory 4.

In FIG. 6, the memory board 11A transfers a group of read data "D2", "D4", "D6", "D8" of the read addresses "A2", "A4", "A6", "A8". Destination address "A2 '", "A4'", "A6 '",
It is a timing chart at the time of transferring to another device corresponding to "A8 '". First, the address generator 16 of the memory board 11A generates read addresses "A2", "A4", "A6", and "A8" as shown in FIG. Input to the address port of the memory 4. Data bidirectional FIFO 13
Are read addresses “A2”, “A4”, “A6”,
Corresponding to "A8", read data "D" read from the data port of the memory 4 as shown in (b) of FIG.
2 ”,“ D4 ”,“ D6 ”, and“ D8 ”are accumulated. Next, as shown in FIG. 6C, the address generator 16 sends the transfer destination addresses “A2 ′”, “A4 ′”, “A”.
6 '"and"A8'"are generated, and the bidirectional FIFO for address is generated.
Output to O12. The address bidirectional FIFO 12 is
The transfer destination addresses "A2 '", "A4'", "A"
6 '"and"A8'"are accumulated and sequentially sent to the address bus Ba as shown in FIG. In synchronization with this, the data bidirectional FIFO 13 reads the read data "D2", "D4", "D6", as shown in (e) of FIG.
"D8" is sent to the data bus Bd.

As described above, even a group of data having discontinuous addresses can be collectively transferred on the bus B, which enables high-speed transfer.

[0027]

According to the storage device of the present invention, since the address FIFO is provided in addition to the data transfer FIFO, even a group of data having discontinuous addresses can be collectively transferred on the bus B. Therefore, high-speed transfer becomes possible.

[Brief description of drawings]

FIG. 1 is a configuration diagram of a main part of a bus system including a memory board that realizes a storage device according to a first embodiment of the present invention.

FIG. 2 is a time chart showing an operation of writing data to a memory board in the bus system of FIG.

3 is a time chart showing an operation of reading data from a memory board in the bus system of FIG.

FIG. 4 is a main part configuration diagram of a bus system including a memory board that realizes a storage device according to a second embodiment of the present invention.

5 is a time chart showing the operation of writing data to a memory board in the bus system of FIG.

FIG. 6 is a time chart showing an operation of reading data from a memory board in the bus system of FIG.

FIG. 7 is an explanatory diagram of general data transfer.

FIG. 8 is an explanatory diagram of transfer of a group of data having continuous addresses.

[Explanation of symbols]

 101,201 Bus system 1,11A Memory board 2 Address FIFO 12 Address bidirectional FIFO 3,13 Data bidirectional FIFO 4 Memory 5,15 Protocol controller 16 Address generator 17 Address switcher M Bus master Ba Address bus Bd data Bus Bc Control Bus B Bus

Claims (2)

[Claims] 1. A storage device, which is connected to an address bus and a data bus and comprises a randomly accessible memory, stores write addresses or read addresses received from the address bus and stores the write addresses or read addresses in the memory. An address FIFO for sequentially outputting to the address port and write data received from the data bus corresponding to the write address are accumulated and sequentially output to the data port of the memory, or read from the memory corresponding to the read address. A storage device, comprising: a data FIFO for accumulating read data that has been output and sequentially sending the data to a data bus. 2. An address generator for generating a transfer source address or a transfer destination address in a storage device connected to an address bus and a data bus and provided with a randomly accessible memory, and a transfer input from the address generator. Address FIFO for accumulating the original address or the transfer destination address and sending them to the address bus in order
And write data received from the data bus corresponding to the transfer source address sent to the address bus and sequentially output to the data port of the memory, or read data read from the memory and stored at the transfer destination. A storage device, comprising: a data FIFO for sequentially sending an address to a data bus in correspondence with sending of an address to an address bus.