JP3309560B2 - Image processing device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image processing apparatus such as a memory used in a video printer.

[0002]

2. Description of the Related Art Video printers are known which take in image data of a desired scene into a memory and print out the image data on photographic paper. For example, it is convenient for this video printer to take in a scene in which ingredients and the like are introduced in a cooking program, and utilize it so as to save photographic paper on which the data is printed.

A video printer is provided with a memory for storing desired image data. The memory stores, for example, video data for one frame. Then, the video data is read from the memory and printed out on photographic paper.

[0004]

By the way, the bus of this memory is managed by one bus master. Therefore, two data cannot be transferred at the same time. Therefore, input / output of the video rate is considerably restricted, and other devices can be accessed only during the blanking period. In addition, access to the memory storing data is also limited to the blanking period, so that processing such as data processing requires time.

SUMMARY OF THE INVENTION It is therefore an object of the present invention to provide an image processing apparatus which can access other devices without being limited by a video rate, and can improve utilization efficiency as a whole.

[0006]

The present invention comprises a bus master for managing a bus to which an image processing device is connected, a memory for storing image data, and switching means for switching between the bus master and the memory. An image processing apparatus in which a bus master and a memory are switched by switching means between an image data period of image data and a blanking period.

[0007]

The sub bus master 1 is controlled so that the main bus master 3 can manage the memory 2 only during the blanking period. Also, during periods other than the blanking period,
The sub-bus master 1 manages the memory 2, and the main bus master 3 manages the memory 4 and the memory 5.

[0008]

An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram when an image processing apparatus according to the present invention is applied to a memory of a video printer. The memory of the video printer shown in FIG. 1 is managed by a main bus master and a sub bus master. As a bus master, for example, a DMAC (Direct Memory Access Controller) or a DMA
A built-in CPU can be applied.

An image signal supplied from the outside is subjected to A / D conversion and then passed through a sub bus master 1. The image data output from the sub bus master 1 is supplied to a monitor (not shown) after D / A conversion. Further, the image data is supplied to the terminal 1a of the sub bus master 1.
The memory 2 is connected to the terminal 1c of the sub bus master 1. The memory 2 is, for example, a frame memory. The image data is stored in the memory 2 by connecting the terminal 1a to the terminal 1c. The image data stored in the memory 2 is output to a monitor. The main bus master 3 is connected to the sub bus master 1b via a bus. Further, the memories 4, 5... Are connected to the main bus master 3. For example, the memory 4 does not perform any processing on the supplied image data. Therefore, the image signal is output from the memory 4 as it is. In the memory 5, predetermined processing is performed on the supplied image data. For example, an image signal for printing is stored in a memory provided together with the memory 4 and the memory 5. The main bus master 3 is connected to a device such as a printing head (not shown) for printing.

The terminal 1c of the sub-bus master 1 is switched to the terminal 1b only during a blanking period of image data. In a period other than the blanking period, the terminal 1
c is switched to terminal 1a. That is, the image data stored in the memory 2 is stored in the memory 4 during the blanking period.
And sent to the memory 5. In the memories 4 and 5 connected to the main bus master 3, each processing is performed regardless of the blanking period of the image data. As described above, since the terminal 1b is connected to the terminal 1c during the blanking period, the image signal subjected to the predetermined processing in each of the memories 4 and 5 is stored in the memory 2 during the blanking period.

FIGS. 2 and 3 are diagrams relating to bus switching as viewed from the main bus master 3. FIG. FIG.
FIG. 3 is a connection diagram of a bus during a period other than a blanking period. Also,
FIG. 3 is a bus connection diagram during the blanking period. As can be seen from FIG. 2, the bus is disconnected except during the blanking period. At this time, each memory is managed by each bus master as two independent buses. Therefore, the main bus master 3 cannot access the memory 2. Further, as can be seen from FIG. 3, the bus is open during the blanking period.
At this time, the memory 2 is managed by the main bus master 3, and the sub bus master 1 does not operate. For this reason,
The main bus master 3 can access the memory 2. Bus switching is managed by the sub-bus master 1, and a signal indicating a bus switching state is transmitted from the sub-bus master 1 to the main bus master 3.

FIG. 4 is a detailed block diagram of the sub-bus master 1. The bus is divided into a data bus system and a control bus system. The control bus system includes signals necessary for memory control such as an address, RAS, CAS, WE, and OE. An image signal is supplied to an A / D conversion circuit 12 via an input terminal 11. Digital image data output from the A / D conversion circuit 12 is supplied to a write-side terminal 13 a of the switch 13. Also,
The image signal passed through the input terminal 11 is supplied to a synchronization signal separation circuit 14. In the synchronization signal separation circuit 14, a synchronization signal is separated from the image signal. This synchronization signal is AFC
/ Sent to the timing generation circuit 15. The AFC / timing generation circuit 15 generates a control reference signal such as a write clock and a blanking period signal.
The AFC / timing generation circuit 15 is connected to the write-side terminal 16a of the switch 16 so that the terminal 16
a is supplied with a control reference signal. Also, AFC
The / timing generation circuit 15 is connected to the write-side terminal 17a of the switch 17, whereby a blanking period signal is supplied to the terminal 17a.

The terminal 16c of the switch 16 is connected to a memory control system generation circuit 18. The memory control system generation circuit 18 generates signals such as addresses necessary for memory control based on the control reference signal. Memory control system generation circuit 1
The output signal of No. 8 is supplied to a terminal 19b outside the blanking period of the switch 19 (hereinafter referred to as * BLK).
Further, a blanking period signal via the terminal 17c of the switch 17 is a control signal for switching the switch 19 and the switch 20. A control system of a main bus master is connected to a blanking period (hereinafter, referred to as BLK) side terminal 19 a of the switch 19. The data system of the main bus master is connected to the BLK side terminal 20a of the switch 20. As described above, various memories are connected to the main bus master. The terminal 19c of the switch 19 is connected to the control system of the memory 2, and the terminal 20c of the switch 20 is connected to the data system of the memory 2. Switch 20
The * BLK side terminal 20b is a terminal 13c of the switch 13.
Connected to.

The read side terminal 17b of the switch 17 and the read side terminal 16b of the switch 16 are connected to the timing generation circuit 21. The timing generation circuit 21 generates a blanking period signal and a control reference signal using a built-in timing generator. These signals are supplied to the synchronization signal generation circuit 22. The synchronization signal generation circuit 22 generates a synchronization signal based on the supplied signal. This synchronization signal is supplied to the adding circuit 23. The read-side terminal 13b of the switch 13 is connected to the D / A conversion circuit 24. The digital image data supplied to the D / A conversion circuit 24 is converted into an analog image signal and supplied to the adder 23. In the adder 23, the synchronizing signal is inserted into a predetermined position of the image signal and output.

In such a circuit, when data is written, the switches 13, 16 and 17 are switched to the respective write-side terminals during V blanking.
The image data digitized by the A / D converter 12 is
The data is written to the memory 2 via the switch 20. The terminal 20c of the switch 20 is switched to the terminal 20a during a blanking period. In the blanking period, the memory 2 is connected to the control system of the main bus master. On the other hand, the control system signal generated by the memory control system generation circuit 18 is supplied to the memory 2 outside the blanking period. With this signal,
The memory 2 is controlled.

At the time of reading data, the switches 13, 16 and 17 are switched to respective reading terminals during V blanking. The subsequent operation is the same as in the data writing. However, at the time of reading, since there is no reference signal such as a synchronization signal, the timing generation circuit 21 generates a blanking period signal and a control system reference signal.

As described above, the bus is released during the blanking period, and the memory 2 is managed by the main bus master. When the bus is released, data processed by the memory 5 and the like is transferred to the memory 2. After that, the next data stored in the memory 2 is transferred to the memory 5 in an amount required for processing. By configuring the sub-bus master 1 as described above, the utilization efficiency of the bus and other devices can be improved.

In the sub-bus master 1 shown in FIG. 4, on the input side, the synchronizing signal is separated at a stage preceding the A / D conversion circuit 12, but the synchronizing signal is separated from the A / D converted image data. You may do so. Alternatively, on the output side, a digital synchronization signal may be internally generated, and the D / A conversion may be performed after adding the synchronization signal to the data read from the memory.

In the above-described embodiment, an example is shown in which the image processing apparatus according to the present invention is applied to a memory of a video printer. However, the present invention is not limited to this. The same effect as that of the above-described embodiment can be obtained also in the device described above.

[0020]

According to the present invention, by switching the bus during the blanking period, it becomes possible to write the image signal to the memory and to output the data in the memory to a monitor or the like. Also, while the bus is disconnected, the bus of the main bus master is not restricted by the access during the blanking period, so that other devices can be accessed. Furthermore, by placing a memory having a certain capacity on the main bus and transferring image signals during the blanking period, the amount of data obtained during the blanking period is increased, and the restriction of the blanking period is not felt. can do.

[Brief description of the drawings]

FIG. 1 is a block diagram when an image processing apparatus according to the present invention is applied to a memory of a video printer.

FIG. 2 is a diagram relating to bus switching as viewed from a main bus master.

FIG. 3 is a diagram relating to bus switching as viewed from a main bus master.

FIG. 4 is a detailed block diagram of a sub bus master.

[Explanation of symbols]

 1 Sub bus master 2, 4, 5 Memory 3 Main bus master

Claims (2)

(57) [Claims] An image processing apparatus comprising: a bus master that manages a bus to which an image processing device is connected; a memory that stores image data; and a switching unit that switches between the bus master and the memory. An image processing device in which the bus master and the memory are switched by the switching unit during a data period and a blanking period. 2. A plurality of image processing devices are connected to the bus master, and the bus master can access the devices regardless of the image data period and the blanking period. The image processing device according to claim 1.