JPH05159042A - Picture processor - Google Patents

Abstract

PURPOSE:To process picture data at high speed without taking much time for the transfer of picture data. CONSTITUTION:Plural bus switches 21-24 and 26-29 which selectively connect plural picture processing parts 17 and 18 to a bus and plural control registers 19 and 20 which are provided in accordance with the plural picture processing parts 17 and 18, store an instruction from a micro computer 11, selectively connect the plural picture processing parts 17 and 18 by controlling the corresponding picture processing by the instruction, parts 17 and 18 and the plural bus switches 21-24 and 26-29 make the plural picture processing parts 17 and 18 read/process picture data on a processing source from opposite memories 33 and 34 and store it in its own memories 33 and 34 are provided.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image processing apparatus having a plurality of image processing units.

[0002]

2. Description of the Related Art Conventionally, there is an image processing apparatus that sequentially transfers image data to a plurality of image processing sections while dividing each processing of the image data by each image processing section.
In this image processing device, for example, a plurality of image processing units perform processing such as binarization processing of image data, filtering processing, and coordinate conversion processing. When performing high-speed image data processing, a memory is usually provided in each image processing unit, and the image data of the processing source (before processing) and the image data after processing are stored in this memory.

[0003]

In the image processing apparatus described above, while the image data is sequentially transferred to the plurality of image processing units, each processing of the image data is divided and sequentially performed by each image processing unit. When the image data processed by the processing unit and stored in the memory is processed by the next image processing unit, the image data must be transferred from the memory in the former image processing unit to the latter image processing unit. It takes time to transfer the data, which slows down the image data processing.

SUMMARY OF THE INVENTION It is an object of the present invention to provide an image processing apparatus which solves the above-mentioned drawbacks and can perform high-speed image data processing in a short time for transferring image data.

[0005]

In order to achieve the above object, the invention according to claim 1 has a plurality of image processing units each having a memory for storing image data of a processing source and image data after processing, In an image processing apparatus including a microcomputer that causes the plurality of image processing units to sequentially process image data, a plurality of bus switches that selectively connect the plurality of image processing units to a bus, and the plurality of image processing units. By storing commands from the microcomputer and controlling the plurality of image processing units and the plurality of bus switches corresponding to each other by the commands, the plurality of image processing units are mutually connected. Selectively connected to allow the plurality of image processing units to read the image data of the processing source from the memory of the other party, process the image data, and then store the image data in the own memory. It is obtained by a number of control registers.

[0006]

A plurality of control registers store an instruction from the microcomputer, and the plurality of image processing sections and the plurality of bus switches respectively corresponding to the instructions are controlled by these instructions to selectively connect the plurality of image processing sections to each other. Then, each of the plurality of image processing units reads the image data of the processing source from the memory of the other party, processes the image data, and then stores the image data in its own memory.

[0007]

FIG. 1 shows an embodiment of the present invention. In this embodiment, a microcomputer (hereinafter referred to as CPU) 11,
A plurality of buses 12 to 14, a plurality of image processing circuits 15 and 16
The image processing circuits 15 and 16 include image processing units 17 and 18 and control registers 19 and 20, respectively.
And bus switches 21 to 25 and 26 to 30. The image processing units 17 and 18 are composed of image processing arithmetic circuits 31 and 32, frame memories 33 and 34, source address generation circuits 35 and 36, and destination address generation circuits 37 and 38, respectively. Bus 1
Reference numeral 2 denotes a control bus used by the CPU 11 for issuing commands to the image processing units 17 and 18 and reading the values of the control registers 19 and 20.
And control registers 19 and 20 are connected. The bus 13 receives the image data from the CPU 11 and the image processing unit 1.
It is a bus used for exchanging data between 7 and 18, and is equivalent to the bus 14. The bus 14 is a bus used for exchanging image data between the CPU 11 and the image processing units 17 and 18, and is used when the bus 13 is being used.

The bus 13 is connected to the CPU 11, the image processing operation circuit 31 and the source address generation circuit 35 are connected via the bus switch 21, and the frame memory 33 is connected via the bus switch 23.
Further, the bus 13 is connected to the image processing arithmetic circuit 32 and the source address generating circuit 36 via the bus switch 26, and is connected to the frame memory 34 via the bus switch 28. The CPU 14 is connected to the bus 14, the image processing arithmetic circuit 31 and the source address generating circuit 35 are connected via the bus switch 22, and the frame memory 33 is connected via the bus switch 24. Further, the bus 14 is connected to the image processing arithmetic circuit 32 and the source address generating circuit 36 via the bus switch 27, and the frame memory 34 via the bus switch 29.
Are connected.

The CPU 11 controls the entire system and the bus 1.
2 to 14 are arbitrated, and the image processing units 17 and 18 divide processing such as binarization processing, filtering processing, and coordinate conversion processing of the image data into a plurality of processings, and each processing is performed by a command from the CPU 11. It has a function to perform each process individually.
The control registers 19 and 20 store an instruction from the CPU 11 and control the image processing units 17 and 18 and the bus switches 21 to 25 and 26 to 30 by this instruction. The source address generation circuits 35 and 36 are frame memories 33 and 34 of image data of a processing source (before processing) to be processed, for example, image data input from a camera.
Is an address generation circuit for designating an address of a storage destination for the destination address generation circuits 37 and 38.
An address generation circuit for designating a storage destination address for 3, 34. The image processing arithmetic circuits 31 and 32 individually have a function of dividing processing such as binarization processing of image data, filtering processing, and coordinate conversion processing into a plurality of processings, and performing each processing one by one by an instruction from the CPU 11. Have,
The frame memories 33 and 34 are memories for storing image data.

The bus switches 21 and 26 output the address signal and the bus control signal generated from the source address generation circuits 35 and 36 to the bus 13, and input the data signal from the bus 13 to the image processing arithmetic circuits 31 and 32. It is a bus switch. The bus switches 25 and 30 input the address signal and the bus control signal generated from the destination address generating circuits 37 and 38 to the frame memories 33 and 34, and the image processing arithmetic circuit 31,
A bus switch for inputting the image data of the processing result output from 32 to the frame memories 33 and 34.
The bus switches 23 and 28 are bus switches for inputting the address data control signals from the bus 13 to the frame memories 33 and 34 and outputting the address data control signals from the frame memories 33 and 34 to the bus 13. is there.

The bus switches 22 and 27 output the address signal and the bus control signal generated from the source address generation circuits 35 and 36 to the bus 14 and input the data signal from the bus 14 to the image processing arithmetic circuits 31 and 32. It is a bus switch. The bus switches 24 and 29 input the address / data control signal from the bus 14 to the frame memories 33 and 34, respectively.
A bus switch for outputting the address / data control signal from 3, 34 to the bus 14.

Next, the operation of this embodiment will be described.
The CPU 11 outputs an instruction to the control registers 19 and 20 in each of the image processing circuits 15 and 16 via the bus 12 to store it. In each of the image processing circuits 15 and 16, the control registers 19 and 20 turn on / off the bus switches 21 to 25 and 26 to 30 according to an instruction stored by the CPU 11, and the source address generating circuits 35 and 36 receive an address signal and a bus. Generates control signals and destination address generation circuit 3
An address signal and a bus control signal are generated at 7, 38, and the image processing arithmetic circuits 31, 32 are caused to perform arithmetic processing of image data.

In this case, the bus switches 22 and 2 are usually used.
4, 27 and 29 are off and the source address generating circuits 35 and 36, the image processing arithmetic circuits 31 and 32, and the frame memories 33 and 34 are not connected to the bus 13. Then, for example, the bus switch 21 is turned on by an instruction from the control register 19, and the image processing arithmetic circuit 31 processes the image data input from the CPU 11 via the bus 13 and the bus switch 21 by an instruction from the control register 19. do. Further, the bus switch 25 is turned on by an instruction from the control register 19, and the image processing arithmetic circuit 31 outputs the image data of the processing result to the frame memory 33 via the bus switch 25 to the address signal from the destination address generating circuit 37 and Store according to the bus control signal.

Similarly, the bus switch 26 is turned on by an instruction from the control register 20, and the image processing arithmetic circuit 32 is input by the instruction from the control register 20 from the CPU 11 via the bus 13 and the bus switch 26. Process. Further, the bus switch 30 is turned on by an instruction from the control register 20, and the image processing arithmetic circuit 32 outputs the image data of the processing result to the frame memory 34 via the bus switch 30 to the address signal from the destination address generating circuit 38 and Store according to the bus control signal.

As shown in FIG. 2, the CPU 11 outputs an instruction to the control register 19 via the bus 12 to turn on the bus switch 21 and outputs an instruction to the control register 20 via the bus 12. The bus switch 28 is turned on. Next, the CPU 11 controls an instruction via the bus 12 to cause the image processing arithmetic circuit 31 to arithmetically process the image data from the frame memory 34 in the image processing unit 18 and store the result in the frame memory 33. Output instruction to register 19
An instruction is output to the control register 19 via 2 to turn on the bus switch 25. Then, the source address generation circuit 35 generates an address signal and a bus control signal according to an instruction from the control register 19, and the address signal and the bus control signal are sent to the frame memory 34 via the bus switch 21, the bus 13, and the bus switch 28. It is output and the address of the frame memory 34 is designated.

The frame memory 34 reads the image data from the designated address, and this image data is input to the image processing arithmetic circuit 31 via the bus switch 28, the bus 13 and the bus switch 21. Image processing arithmetic circuit 3
1 processes the input image data according to an instruction from the control register 19. The destination address generation circuit 37 generates an address signal and a bus control signal according to an instruction from the control register 19, and the address signal and the bus control signal are transmitted via the bus switch 25 to the frame memory 33.
And the address of the frame memory 33 is designated. The image processing arithmetic circuit 31 stores the processed image data in the frame memory 33 via the bus switch 25 in accordance with the address signal and the bus control signal from the destination address generating circuit 37.

Similarly, the CPU 11 outputs an instruction to the control register 20 via the bus 12 to turn on the bus switch 26, and outputs an instruction to the control register 20 via the bus 12 to turn on the bus switch 23. Let Next, the CPU 11 causes the image processing arithmetic circuit 32 to perform arithmetic processing on the image data from the frame memory 33 in the image processing unit 17, and the result thereof is stored in the frame memory 34.
Command to output to the control register 20 via the bus 12 and output to the control register 20 via the bus 12 to store the command in the bus switch 3
Turn 0 on. Then, the source address generation circuit 36
Generates an address signal and a bus control signal according to an instruction from the control register 20, and the address signal and the bus control signal are transmitted via the bus switch 26, the bus 13, and the bus switch 23 to the frame memory 33.
And the address of the frame memory 33 is designated.

The frame memory 33 reads the image data from the designated address, and this image data is input to the image processing arithmetic circuit 32 via the bus switch 23, the bus 13 and the bus switch 26. Image processing arithmetic circuit 3
2 processes the input image data according to an instruction from the control register 20. The destination address generation circuit 38 generates an address signal and a bus control signal according to an instruction from the control register 20, and the address signal and the bus control signal are transmitted via the bus switch 30 to the frame memory 34.
And the address of the frame memory 34 is designated. The image processing arithmetic circuit 32 stores the processed image data in the frame memory 34 via the bus switch 30 in accordance with the address signal and the bus control signal from the destination address generating circuit 38.

When the image processing circuit 15 or the image processing circuit 16 is using the bus 13, the CPU 11 causes another image processing circuit 16 or the image processing circuit 15 to use the bus 14. That is, the CPU 11 causes the image processing circuit 15 to turn on the bus switches 21 and 23 to use the bus 13 while the image processing circuit 16 causes the bus switch 2 to operate.
7, 29 are turned on to use the bus 14, and when the image processing circuit 16 turns on the bus switches 26 and 28 to use the bus 13, the image processing circuit 15 turns on the bus switches 22 and 24. Turn on to use bus 14.

In this embodiment, the image processing circuits 15 and 16 are
Directly access each other's frame memories 33, 34 to read image data, the image processing circuit 1
It is possible to eliminate the time for transferring the image data between 5 and 16. Moreover, the bus switches 21-24, 26-
Since only one frame memory 33 or 34 is connected to each of the two buses 13 and 14 at a time by 29, the upper bits of the address signal are not required, and not only two image processing circuits 15 and 16 but three Even if the number is increased above, it is not necessary to expand the address space of the frame memories 33 and 34, and it becomes easy to arbitrarily add an image processing circuit.

[0021]

As described above, according to the first aspect of the invention, a plurality of image processing units each having a memory for storing the image data of the processing source and the image data after the processing, and the plurality of image processing units. In an image processing apparatus including a CPU that sequentially processes image data in a unit, a plurality of bus switches that selectively connect the plurality of image processing units to a bus, and a plurality of bus switches provided corresponding to the plurality of image processing units By storing a command from the CPU and controlling the plurality of image processing units and the plurality of bus switches respectively corresponding to the command, the plurality of image processing units are selectively connected to each other and the Since each of the plurality of image processing units is provided with a plurality of control registers that cause the image data of the processing source to be read from the other party's memory and processed, and then stored in its own memory, It is possible to perform high-speed image data processing taking less time to transfer the data. Moreover, by selectively connecting a plurality of image processing units to the bus, it becomes easy to arbitrarily add image processing units.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.

FIG. 2 is a flowchart showing a part of an operation flow of the embodiment.

[Explanation of symbols]

 11 CPU 13, 14 Bus 17, 18 Image processing unit 19, 20 Control register 21-24, 26-29 Bus switch

Claims (1)

[Claims] 1. A plurality of image processing units each having a memory for storing image data of a processing source and image data after processing,
In an image processing apparatus including a microcomputer that sequentially processes image data in the plurality of image processing units, a plurality of bus switches that selectively connect the plurality of image processing units to a bus, and the plurality of image processing units. By storing commands from the microcomputer and controlling the plurality of image processing units and the plurality of bus switches corresponding to each other by the commands, the plurality of image processing units are mutually connected. A plurality of control registers that are selectively connected to cause the plurality of image processing units to read the image data of the processing source from the memory of the other party, process the image data, and store the processed image data in the memory of the image processing unit. Image processing device.