JP2510219B2 - Image processing device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image processing apparatus, and more particularly to a bus structure for realizing high speed processing.

[Conventional technology]

As an image processing apparatus, there is a conventional one shown in FIG. 4, for example. In the figure, 1, 2 and 3 are image memories, 4 is a common bus consisting of five address buses X and Y and data buses A, B and C, and 5 is a predetermined bus based on the image data input from one image memory. , And write the result to another image memory, 6,7,8,9 are output buffers, 10 is an address control unit that outputs address data to each image memory 1,2,3, and 11 is A controller for controlling the processor 5, the address control unit 10 and the like, 12 is a VR for controlling the image memories VRAM1 to VRAMm
It is an AM controller.

In such a device, for example, when the image data of the image memories 1 and 2 are added and written in the image memory 3, the processor 5 adds the data of the image memories 1 and 2 input from the data buses A and B. After that, the result may be output to the data bus C, and the output data of the processor 5 may be written in the image memory 3 via the bus C. At this time, the address control unit 10 scans the addresses of the image memories 1, 2, and 3 in one screen (see, for example, JP-A-61-153774).

[Problems to be solved by the invention]

By the way, in such a conventional image processing apparatus, since the address of the image memory is input from a fixed bus and the input of the processor is also performed from the fixed bus, for example, affine transformation (graphic rotation There is a problem in that it is impossible to execute a process that requires calculating the address of the image memory. Further, even if the number of image memories or processors is increased or the number of buses is increased, there is a problem in that processing flexibility and versatility are lacking due to connection restrictions, and processing cannot be speeded up.

Therefore, an object of the present invention is to enable address calculation under a small number of common buses, facilitate addition of an image memory or a processor, and provide versatility of processing.

[Means for solving problems]

In order to achieve the above object and solve the problems of the prior art, an image processing apparatus according to the present invention includes a plurality of image memories connected to a common bus and one image memory input via the common bus. In an image processing apparatus including a processor for writing a calculation result based on image data to another image memory via the common bus, a horizontal address, a vertical address, and a data input of each image memory are independently output from the common bus. A plurality of selectors for input selection are provided for each image memory, and a plurality of processors are provided for each processor so that the input of each processor can be independently selected from the common bus.

〔Example〕

Embodiments of the present invention will be described below with reference to the accompanying drawings. FIG. 1 shows an example of an image processing apparatus according to the present invention.

In the figure, 20 is a common bus composed of data buses A, B and C and address buses X and Y, and VRAM1 to VRAMm are plural (m
Image memory, S _{1 to} S _m are each image memory VRAM _{1 to} VRAMm
It is a selector provided corresponding to. This selector S ₁ ~ S _m
Is at least the address bus X for the X address
And one of the data buses A, B, C, and the Y address is also at least the address bus Y and the data buses A, B, C.
Select one from the back of C, data input is data bus A,
Select one from B and C. Regarding image output (out), output buffers B _{1 to} B _m are provided so that they can be output to any of the data buses A, B, and C. In addition, P _{1 to} P _n are a plurality (n) of processors that execute a predetermined calculation regarding image data,
Each of the processors P _{1 to} P _n has at least two inputs, and the input can be selected from any of the data buses A, B and C and the address buses X and Y via the selectors SP _{1 to} SP _n . . The outputs of the processors P _{1 to} P _n can be output to any of the data buses A, B and C via the output buffers BP _{1 to} BP _n . The processors P _{1 to} P _n are
For example, as shown in FIG. 2, input is made to an ALU (arithmetic processing unit) that performs addition / subtraction and logical operation via a LUT (lookup table) that performs constant multiplication, function conversion of sin, cos, and the like. . Writing to the LUT (initial setting) is performed by a host computer or the like. Returning to FIG. 1, 21
Is a VRAM controller that controls the selectors S _{1 to} S _{m in} addition to the read / write control of the image memories VRAM 1 to VRAMm. This VRAM controller 21 controls each image memory
Perform this independently for each VRAM1 to VRAMm. Further, 22 and 23 are an address control unit and a controller, respectively, which are similar to those of the conventional device. Although the whole of these is controlled by the host computer, illustration is omitted for simplicity.

Next, the operation of this apparatus will be described with reference to FIG. 3 by taking affine transformation (image rotation) as an example.

Now, it is assumed that affine transformation is performed based on the data of the image memory VRAM1 in which the original image is stored, and the transformed data is stored in the image memory VRAMm. In this case, to set the image memory VRAM1 to reading, data bus A is the X address via the selector S _1, to select the data bus B to Y address, the processor P _1, P _n, each data bus A Image memory VRAM1 for p and q addresses to be output to B
To output the image data stored in the image data VRAM1 to the data bus C. On the other hand, image memory VR
AMm sets the write state, X address via the selector S _m is Y address an address bus X to select the address bus Y, x sent from the address control unit 22, while to input y address, the image data For the input of, the common bus C is selected and the data of the image memory VRAM1 is input.

The inputs of the processors P ₁ and P _n are selector S
The address bus X and the address bus Y are selected via P ₁ and SP _n, and the x and y addresses transmitted from the address control unit 22 are input. Further, each processor P ₁ , P _n has its L
Assuming that UT performs constant multiplication and ALU performs addition and calculation, p = ax + by q = cx + dy is calculated. Here, the constants a, b, c, d are constants corresponding to the rotation angle. Further, x and y are addresses after the image rotation output by the address control unit 22 and are addresses of the image memory VRAMm. Further, p and q are the addresses of the original images, that is, the addresses of the image memory VRAM1. The output of the processor P ₁ , that is, the P address is input to the image memory VRAM 1 through the data bus A, and the output of the processor P _n , that is, the q address is input through the data bus B to the image memory VRAM.
Entered in 1. Then, the image memory VRAM1 outputs the image data to the data bus C by these p and q addresses,
Since this is stored in the image memory VRAMm, this device enables data transfer between different addresses. If the address control unit 22 controls to scan one screen, one rotation image is stored in the image memory VRAMm, and the process ends.

The affine transformation has been described above. However, if such a bus configuration is adopted, it is easy to add processors and image memories, and if the number of common buses is increased, complicated parallel processing is possible and the processing speed is increased. be able to.

〔The invention's effect〕

As described above, the image processing device according to the present invention is
A selector for independently selecting input from the common bus for horizontal address, vertical address, and data input of each image memory is provided corresponding to the image memory, and a selector capable of independently selecting the input of each processor from the common bus is provided. Since it is provided corresponding to, it is possible to transfer data between different addresses, facilitate addition of an image memory and a processor, improve the versatility of the device, and speed up processing. is there.

[Brief description of drawings]

FIG. 1 is a diagram showing an example of an image processing apparatus according to the present invention, FIG. 2 is a block section showing an example of a processor according to the present invention, and FIG. 3 is a diagram showing an operation example of the image processing apparatus according to the present invention. FIG. 4 is a diagram showing an example of a conventional image processing apparatus. 20 …… Common bus 21 …… VRAM controller 22 …… Address controller 23 …… Controller VRAM1 to VRAMm …… Image memory S _{1 to} S _m , SP _{1 to} SP _n …… Selector

Claims (1)

(57) [Claims] 1. A plurality of image memories connected to a common bus, and an operation result based on image data from one image memory input via the common bus is written to another image memory via the common bus. In an image processing device including a processor, a horizontal address, a vertical address of each image memory,
And a plurality of selectors for independently selecting an input from the common bus for each data input and a plurality of selectors corresponding to each image memory are provided, and a plurality of processors are provided so that the input of each processor can be independently selected from the common bus. An image processing apparatus comprising a plurality of processors corresponding to the processors.