JPS623379A - Document picture processor - Google Patents

Abstract

PURPOSE:To improve the system throughput and also to simplify the constitution of a document picture processor by providing the picture buses of two systems which can be actuated independently of each other and a 2-dimensional address generating circuit for accessing and controlling a picture buffer memory and a display memory between both picture buses respectively. CONSTITUTION:Information is transferred among a picture buffer memory 5, a display memory 6 and each processing circuit via the picture buses I and II of two systems which can be actuated independently of each other. The 2-dimensional address generating circuit 7 and 8 produce addresses to give access to a 2-dimensional rectangular area for both memories 5 and 6 respectively. The connection between both picture buses is controlled by a picture bus switching control circuit 17.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a document image processing device that electronically performs input, output, display, editing, etc. of document images.

(Technical background of the invention and its problems) As typified by facsimiles and electronic files,
Document image processing devices that electronically process document images are being actively developed. The purpose of developing these devices is to improve work efficiency by digitizing conventional paper-based general work, especially office work, and to make it easier to handle complex work as work becomes more sophisticated. It's about doing. These devices scan a document image with a scanner, convert it into an electrical signal, compress it and transmit it, or store it in an image memory, process it, and then output it to an image printer. Information processing is performed.

In such a document image processing apparatus, in order for a user to operate it arbitrarily to truly improve work and improve work efficiency, the following points must be fully considered. First, it is easy and flexible to transfer document image information between the various means that make up the system. If transfer between certain means is not possible, or if it is possible but requires many steps, the scope for improvement will be limited. The second is that the processing speed is high.

In this type of device, the operability of the device as well as the functions it can process are important factors that determine the performance of the device. Among these, processing speed is one of the decisive points for the device's man-machine interface, and unless it satisfies a certain level or higher, work efficiency may be adversely reduced.

However, in conventional document image processing devices, these two points are not necessarily satisfied.

For example, information can be transferred flexibly between each means but the transfer speed is extremely slow, or high-speed information transfer is possible but the transfer destination is limited, or flexible transfer can be performed relatively quickly. However, the hardware mechanism and procedure to start the transfer are extremely complicated. ! It was always sloppy. This does not allow for sufficient improvement in work efficiency.

Furthermore, in conventional devices, each means that needs to access the image buffer memory and display memory, such as a scanner, printer, enlargement/reduction circuit, etc., has an access control circuit. There is a problem in that in order to be able to perform the same operations, the hardware of each of these means and the program for controlling the access control row circuit thereof must become complicated.

[Purpose of the invention]

The present invention has been made in view of the above points, and it greatly facilitates the simultaneous transfer of document image information between multiple means constituting the system, improving system throughput and processing efficiency.
It is an object of the present invention to provide a document image processing device that is capable of linking devices and performing sophisticated image editing processing with a simple configuration.

[Summary of the invention]

The present invention provides at least an image buffer memory for temporarily storing document image information, a display memory for displaying document images, an input/output means for document image information, an image bus used for transferring document image information, and management of these. In a document image processing apparatus having a control device for controlling the image data, two image buses capable of operating independently as image buses are provided, and the image buffer memory 1: r'.

between the memory and display memory and the two image buses mentioned above.
1. An image bus switching control circuit is provided to control connections between the two, and two two-dimensional address generation circuits are connected to the image bus and control access to the image buffer memory and the display memory, respectively. do.

〔Effect of the invention〕

Since the document image processing apparatus according to the present invention has two image buses that can operate independently, it is possible to simultaneously access the image buffer memory and the display memory, thereby improving the throughput of the system. In addition, by connecting circuits that perform scaling, image reversal, etc. to two image buses, advanced document image processing can be achieved, such as writing image information from a scanner to the image buffer memory and simultaneously writing a reduced image to the display memory. processing becomes possible. In addition, a two-dimensional address generation circuit that controls access to the image buffer memory and display memory is provided between the image buses, making it easy to use programs and hardware for memory access in each means that needs to access these memories. become.

Moreover, each of these means gives an address to memory.
1. No need, just an image read/write control signal 1. :.

It is only necessary to supply the address to the address generation circuit, so the address
;.

'4 Access control becomes easier and faster, resulting in arbitrary
□゛. . ,□□□□7, っ□, go ・;:1
, it becomes possible to do so. Furthermore, the address from CPLI
゛: Just change the parameters given to the generator circuit.

The access direction of the harpoon can be changed, rotation, tt
tsR@゛J″1″ to″e * o 71F 91 c
im * s * i m '), : can be executed quickly and easily. Two dimensions ,.

Address data and character pattern from address generation circuit
-1. Combining the outputs of graphic processing circuits that generate patterns, etc.
By adjusting the angle by 4 degrees, simple graphic processing such as filling in straight lines, diagonal lines, or rectangular areas becomes faster.
(, °1 can be done.
j+.

夷 [Embodiments of the invention]・.

The present invention will be described in detail below with reference to the drawings.
1".

FIG. 1 is a schematic diagram of a document image processing device according to an embodiment.
:°□. Oh, s-c. 1o device □ilJ Ill
t□□ Unique information processing unit (hereinafter referred to as CPU),
``...2 is a CPU program memory that stores a program that describes this control procedure, and 3 is an interface for connecting CPtJ 1 to other input/output devices such as a CRT terminal. A control signal from the CPU 1 is applied via the CPU bus 4 to a memory for storing document image information and a document image processing handle to execute desired processing.

5 is an image buffer memory for temporarily storing document image information;
6 is a display memory that temporarily stores document image information to be displayed, and 7 and 8 are two-dimensional address generation circuits that generate addresses for accessing two-dimensional rectangular areas in these memories. 9 is a display controller that takes in data from the display memory 6 according to the display cycle and controls displaying it on the display. 10 is a vertical/horizontal conversion circuit that rotates the orientation of the document image every 90"; 11 is the vertical/horizontal conversion circuit that rotates the orientation of the document image 12 is a graphic processing circuit that generates a character pattern and draws it on the display memory 6 and image buffer memory 5; 13 and 14 are scanners and printers that are document image input/output means; 15;
A scanner having a function of capturing document image information read by the scanner 13 and a function of capturing document image information stored in the memories 5 and 6 and sending it to the printer 15 is also a printer interface.

16 demodulates and decompresses compressed document image information transferred from an external communication system 8m device and imports it, or memory 5.6
This is a compression/expansion circuit that compresses and modulates document image information and sends it to the outside.

In order to transfer information between the image buffer memory 5, display memory 6, and each processing circuit, the present invention uses two independently operable systems 1iii! Buses ■ and ■ are available. Here, the image bus includes an address bus 18 for the image buffer memory 5, a data bus 22 to which the image buffer memory 5 and the vertical/horizontal conversion circuit 10 are connected, and a scaling circuit 1.
12 is a general term for the data bus 24 to which the graphic processing circuit 12, the scanner/printer interface 15, and the compression/expansion circuit 16 are connected, and the control bus 19.25. , a data bus 23 to which the display memory 6 and the vertical/horizontal conversion circuit 10 are connected, a data bus 26 to which the scaling circuit 11 and the graphic processing circuit 12 are connected, and a control bus 21.
．． 27 collectively. In this embodiment, the image buffer memory 5 is connected only to one data bus 22, and the display memory 6 is connected only to the other data bus 23.

Therefore, the data bus 22 on the image buffer memory 5 side and the data bus 24 to which the scaling circuit 111, graphic processing circuit 12, etc. are connected are divided, and the data bus 20 on the display memory 6 side and the scaling circuit 11° graphic The data bus 26 to which the processing circuit 12 and the like are connected is divided, and the connection therebetween is controlled by the image bus switching control circuit 17.

Some processing operations performed by the document image processing apparatus configured as described above will be described below.

(1) When transferring data between the scanner 13 or printer 14 and the image buffer memory 5, j! Data buses 22 and 24 and control buses 19 and 25 are connected by i-image bus switching control circuit 17, and data transfer is executed via data buses 22 and 24. During this time, if it is desired to output graphic data or the like to the display memory 6, this is done via the data buses 23 and 26.

(2) When the data in the image buffer memory 5 is rotated and printed out, the data bus 22 and the aspect conversion circuit 10 are connected, and the data from the image buffer memory 5 enters the aspect conversion circuit 10 and is converted into a 90 After being rotated by .degree., it is outputted to the printer 14 via the bus switching control circuit 17 and the data bus 24. During this time, access to display memory 6 via data buses 23 and 26 is possible.

(3) When writing the input from the scanner 13 to the image buffer memory 5 and simultaneously reducing it and rotating it and writing it to the display memory 6, the data flowing through the data bus 24 is reduced while being taken in by the enlarging/reducing circuit 11. and output to the data bus 26. The vertical/horizontal conversion circuit 10 is connected to the data bus 23
The reduced image data is rotated by 90 degrees and written into the display memory 6.

(4) When image data is being transferred between the scanner 13 or printer 14 and the image buffer memory 5 on the image bus, when a character pattern etc. is enlarged or reduced and written to the display memory 6, the clock from the enlargement/reduction circuit 11 is used to The character pattern in the processing circuit 12 is once taken into the enlarging/reducing circuit 11 via the data bus 26. After the enlargement/reduction process, the data is again written to the display memory 6 via the data buses 26 and 23. In this case, on the image bus (2), the transfer of image data is controlled in synchronization with the read clock and write clock of the enlargement/reduction circuit 11.

(5> When the data in the image buffer memory 5 is enlarged or reduced and written to the display memory 6, the data in the image buffer memory 5 is sent to the enlargement/reduction circuit 1 via the data buses 22 and 24.
1, and its output data is transferred to data bus 26.2.
3 to the display memory 6. In this case, read data runs on the image bus (2), write data runs on the image bus (2), and high-speed data transfer is performed by the pipeline operation of the enlargement/reduction circuit 11.

Further, the image bus ■ is passed through the vertical/horizontal conversion circuit 10.

If the data is connected between 2 and 3, advanced data processing such as rotating and scaling the data will be performed at extremely high speed.

(6) By connecting the data buses 24 and 23, data transfer between the display memory 6 and the scanner 13 or printer 14 is possible.

In the above image information processing operation, two image buses I
In order to perform flexible and high-speed processing using data transfer between the image bus ■ and ■.

■The mediating means for transferring image information between the two plays an important role.

That is, this information transfer mediating means is capable of flexible and sophisticated information processing by providing an active operating mechanism and a passive operating mechanism in the information importing section and the transmitting section, respectively. In this embodiment, the information mediating means having such a function is integrated into the enlarging/reducing circuit 11.

Figure 2 shows an enlargement/reduction circuit 1 equipped with such information mediating means.
This is an example of configuration 1. In the figure, 31 is an enlargement/reduction calculation mechanism, 32 is an input data latch circuit, and 33 is an output data latch circuit. The data acquisition section includes an active input operating mechanism 34 and a passive input operating mechanism 35, and 36 is a selector for a latch signal of input data outputted from these.

The data sending section similarly includes an active output operating mechanism 37 and a passive output operating mechanism 38, and 39 is an end signal selector for the data output sequence outputted from these. Reference numeral 40 denotes a control circuit that performs the sequence subsection by these input/output operation mechanisms.

41 to 5o indicate input/output buffers. Although not shown in the figure, input data, output data, and control signals such as transfer lock can be selectively connected to image bus (2) and image bus (2).

In the image information capture section, during active operation, the active input operation mechanism 34 outputs a data read control signal @PRDC, and input data is captured in response to the response signal PACK, and during passive operation, an external data write control signal PW is output.
The passive operating mechanism 35 is operated by the TC to take in input data. FIG. 3 shows a specific example of the configuration of this image information importing section. The active input operating mechanism 34 includes a PRDC generator 341 that generates a data read control signal PRDC and an AND gate 342. The passive input operating mechanism 35 is constituted by an AND gate 351. Sequence control circuit 4oka16. ) Ika, yo, ekaka81. 1AND gate 351 is in the inhibited state, and the data lines j, l.

・j.

Even if it receives the light control signal PWTC, there is no response signal.
, 5.1. Don't return I PACK and make external means wait.
1. .

It's t.
...9) The image information sending unit outputs active output during active operation.

The operating mechanism 37 receives the data write control signal PWTC.
'11; Output and data transmission is performed, and the response to it is
□7. :・ A procedure that ends the sending operation with the response signal PACK.
°:j1,゛.

Take Kensu. When operating passively, the passive output operating machine
.

The structure 38 is a data read control signal from the outside.
The data sending operation is terminated upon receiving ++PRDC. FIG. 4 shows a specific example of the configuration of this image information sending section. The active output operating mechanism 37 includes a PWT C generator 3 that generates a data write control signal PWTC.
71 and an AND gate 372. The passive output operating mechanism 35 is composed of an AND gate 351.

Enlargement/reduction circuit 1 equipped with image information mediating means as described above
1, a concrete example of the operation of the mediating transfer of image information between the image bus and the image bus will be described below.

The specific bus configuration in this embodiment is as shown in FIG. 5, for example. The address buses 18 and 19 for accessing the image buffer memory 5 and the display memory 6 are Ao=
There are 26 data buses for A2s, and 16 data buses for data buses 22, 23, 24, and 26 from port D to D1s. Control signal bus 1
9, 21° 25.27 is a data read control signal PRDC as a clock for image information transfer, a data write control signal PWTC1, a response signal PACK for these, a horizontal line end signal HEND, and a vertical direction end signal VEND. and one for the selection signal ADSEL of the two sets of address generation circuits 7 and 8, six in total.

First, the operation of displaying a document image stored in the image buffer memory 5 on the display will be explained. In the case of this image processing operation, the image buffer memory 5 is connected to the image bus, and the display memory 6 is connected to the image bus . Connection relationships are selected so that they are respectively connected to bus ■. First, the enlargement/reduction circuit 11 having an image information mediating means has an active input operation mechanism 34 at an image information take-in section and a send-out section, respectively.
, is activated to activate the active output operating mechanism 37. When the enlargement/reduction circuit 11 starts operating, the active input operation mechanism 34 outputs a data read control signal PRDC to the image buffer memory 5 in which document image information is stored. One of the two sets of address generation circuits 7.8 is assigned to the address generation circuit that accesses the image buffer memory 5, and the address is sequentially updated in accordance with the data read control signal PRDC from the enlargement/reduction circuit 11. Response signal P to data read control signal PRDC
ACK is returned on the PACK line from both edge buffer memory 5, and the scaling circuit 11 uses its active input operation mechanism 3.
4 takes in the image information from the image buffer memory 5 into the input data latch 32. The image information captured in this way is subjected to predetermined enlargement or reduction processing by the enlargement/reduction calculation mechanism 31.

The enlarged or reduced image information is sent out by the data write control signal PWTC output from the active output mechanism 37 of the same enlargement/reduction circuit 11 to the display memory 6. In this case as well, one of the address generation circuits 7.8 is assigned to access the display memory 6, and the addresses are sequentially updated in accordance with the data write control signal PWTC. A response signal PACK to this data write control signal PWTC is outputted from the display memory 6 onto the PACK line, and is sent to the active output mechanism 37 of the enlargement/reduction circuit 11.
be taken into account. As a result, the enlarging/reducing circuit 11 moves to the next sequence.

The timing of the above image information transfer is as shown in FIG.

Next, a case will be described in which document image information is taken in from an external device via the image input/output means, written into the display memory 6, and displayed. The compression/expansion circuit 16 will be taken as an example of image input means.

When displaying document image information imported from an external device, if you want to display it at the same size as when it was imported,
The compression/expansion circuit 16 operates as an active operation means, sends out the transfer control signal by itself, and writes it into the display memory. However, especially in the case of display, the display size of a document image is limited due to various displays that interact with the system, and there are many cases where it is desired to display the document image in a reduced size. Conventionally, the method taken to meet this request is to separate only the display portion from the rest and perform scaling processing only when writing to the display memory. According to this method, flexible scaling is possible for display, but scaling processing is limited to display, and for example, it is possible to scale a part of the document image information stored in the image buffer memory and use it for other purposes. It becomes impossible to perform processes such as copying to the image buffer memory, or enlarging or reducing the document image stored in the image buffer memory and printing it out.

In this embodiment, there are two image buses 1. II, and by providing the enlargement/reduction circuit 11 with the above-mentioned transfer mediating means, it is possible to write the document image information taken in from the outside into the display memory 6 or the image buffer memory 5 as it is; It is also possible to perform enlargement or reduction processing via the enlargement/reduction circuit 11 before writing. In the former case,
The captured information is directly written into the display memory 6 by the data write control signal PWTC output from the compression/expansion circuit 16. At this time, the image information is transferred from the data bus 24 via the image bus switching control circuit 17. The data is transferred via the data bus 23. In the latter case, the passive input operation mechanism 35 of the enlarging/reducing circuit 11 is activated, and the enlarging/reducing circuit 11 is operated according to the data write control signal PWTC from the compression/expansion circuit 16.
The image information is taken in, subjected to enlargement or reduction processing, and then written to the display memory 6 by the data write control signal PWTC output from the active output operation mechanism 37 of the enlargement/reduction circuit 11. That is, at this time, the compression/expansion circuit 1
The image information taken in by 6 enters the data bus 26 from the data bus 24 through the enlargement/reduction circuit 11, is sent to the data bus 23 via the image bus switching circuit 17, and is written into the display memory 6. , follow this route.

As described above, according to the present embodiment, extremely flexible image processing is possible in terms of image information transfer between the image buffer memory 5 and display memory 6, writing of image information from the outside into the display memory 6, and the like. Moreover, as is clear from FIGS. 2 to 4, there are two image buses 1. The image information transfer mediating means between IIs is realized by extremely simple hardware.

By the way, as seen in the previous explanation, it is often necessary to perform enlargement/reduction processing on the document image information imported from the image input/output means before displaying it, but at the same time, it is necessary to perform some kind of processing on the document image information imported. For example, it may be necessary to copy a portion or overlay a thin rain edge. Alternatively, it may be necessary to successively change the reduction ratio of the same document image in order to set it in a state that is most easily viewed by the user. In this case, it is necessary to store the document image being displayed in the image buffer memory and read it out for display or image editing processing as needed. Conventionally, this processing requires two phases: first, storing the document image information in the image buffer memory, and then displaying it, and therefore, sufficient processing speed cannot be obtained.

In the present invention, as already mentioned, two image buses 1 and n are provided, and these can operate independently.
The means for transmitting document images can simultaneously transfer images to a plurality of means.

In the above operation example, 1. The document image information sent from the image input/output means can be transferred to the image buffer memory and the display memory at the same time. A problem with such simultaneous transfer is the difference in the capture speeds of the plurality of capture sides. In the present invention, this problem can be solved by configuring the respective response signals to the transfer lock to be logically ANDed on the image bus.

FIG. 7 is a diagram for explaining such an embodiment. In the figure, 61 is the PACK line on the control signal bus, 621.622.

623 respectively send a response signal P to this PACK line 61.
This is a PACK output stage of each means that outputs ACK. Each output stage is comprised of an oven collector gate 63 and its movable control gate 64, and becomes movable when the -enable signal EN is high.

With such a configuration, the response signal PAC issued by the plurality of means
The PACK line 61 does not go high while any one of K1 to PACK3 is low, and PAC is not activated until the outputs of all PACK output stages 621 to 623 become high.
K line 61 becomes high. This makes it possible to maintain complete synchronization of image information transfer, allowing simultaneous transfer to multiple means.

Note that, instead of adopting the configuration of calculating logical product using a gate circuit as shown in FIG. 7, it is also possible to adopt a method in which, for example, only the response signal PACK of the means with the slowest response is returned to the PACK line. .

This is also substantially the same as performing logical AND on the same bus, and the same effect can be obtained.

Next, the configuration and operation of the memory access control circuit portion in the device of the present invention will be explained in more detail.

As shown in FIG. 1, this device uses two two-dimensional address generation circuits 7 in order to simultaneously control access to the image buffer memory 5 and the display memory 6.
and 8 are provided between the two image buses ■ and ■.

Considering only the image information transfer between the image buffer memory 5 and the display memory 6 and the information transfer between these memories and other means, the two-dimensional address generation circuits 7 and 8 have one for the image buffer memory 5 and the other for the image buffer memory 5. is for display memory 6,
Although they may be fixedly connected to different image buses, in the embodiment of FIG. 1 both two-dimensional address generating circuits 7.8 are connected to different image buses.

■It can be connected to any of the following. This is so that image information can be transferred only within the image buffer memory 5 and only within the display memory 6. When performing image information transfer as described above, the image bus switching control circuit 17, enlargement/reduction circuit 11, graphic processing circuit 12, scanner/printer interface 15, compression/expansion circuit 16, etc. perform writing and reading of image information. It is sufficient to input and output only the control clock and image information to the image bus or n, and there is no need to control access to the image buffer memory 5 or display memory 6.

FIG. 8 shows a schematic configuration of the two-dimensional address generation circuits 7 and 8. 71 connects this address generation circuit to CPU1.
72 is a register selected by CPLJl and set with a command CMD necessary for access control; 73x, 74x,
75x, 73y, 74y, and 75Y are the same.<The start address X5TA, YSTA related to X and Y coordinates selected by CPU1, the number of steps X5TP, YSTP which is the minimum unit for calculating the address, and the number of repetitions XN, YN of address calculation are set. This is the register that will be used. Counters 76x, 76y, timing control circuit 77, multiplexer 78x.

78Y, 7'j-79x, 79y are parts for calculating the X, Yf)7 dress. Multiplexer 78X.

Address data obtained from 78y is interface 8
It is designed to be output to address bus 18 or 2o via 0x and 80y. 81x.

Reference numeral 81Y is an interface for controlling the timing of outputting or stopping address data, which is taken into this address generation circuit by a control signal sent from another device via the control buses 19, 21.

In a device in which such two two-dimensional address generation circuits 7 and 8 are connected between image buses I and II, the most basic operation is to extract an image from a certain area in one document and paste it into another area. The operation when performing editing processing will be described next.

FIG. 9 shows the extracted area in the document at this time with a solid line, the transfer destination area with a broken line, and shows the address relationship of each area. When performing image editing like this,
For example, one two-dimensional address generation circuit 7 is selected by the CPU 1 to access the transfer source area, and the other two-dimensional address generation circuit 8 is selected to access the transfer destination, and the commands, X and Y coordinates necessary for access control, The start address, number of steps, number of repetitions, etc. related to the process are set in each register to enable access control. Next, for example, from the image bus switching control circuit 17, the data read fl1
m-sign @PRDC is the control bus 19 on the image bus I side.
When the two-dimensional address generation circuit 7 selected as the transfer source starts operating, it calculates a predetermined address and outputs it to the address bus 18 on the image bus side.

As a result, the image buffer memory 5 connected to the image bus I side is accessed, and the image information in the transfer source area is read out and output to the data bus 22.

When the image bus switching control circuit 17 finishes taking in the transfer source image information from the data bus 22, it then outputs the data write control signal PWC and the previously read image information to the control bus 19 and data bus 22, respectively. do. Control signal P for data write to control bus 19
When the WTC is output, the two-dimensional address generation circuit 7 stops outputting address data of the transfer source, and the other two-dimensional address generation circuit 8 selected as the transfer destination starts operating. The two-dimensional address generation circuit 8 generates a transfer destination address and outputs it to the address bus 18, thereby writing image information into the transfer destination area of the image buffer memory 5. When this write process is completed, the image bus switching control 11 circuit 17 outputs the data read control signal PRDC to the control bus 19 in order to read the next image information from the transfer source again, and performs the read process in the same manner as described above. At this time, the two-dimensional address generation circuit 8
stops outputting the transfer destination address, and the two-dimensional address generation circuit 7 calculates and outputs the next address.

By sequentially repeating the above reading and writing process over the entire predetermined area, image information transfer within one document as shown in FIG. 9 is performed two-dimensionally and at high speed. At this time, each address generation circuit 7.8 generates an address by scanning a predetermined area two-dimensionally according to the flowchart shown in FIG. In other words, in the case of image transfer as shown in Figure 9, instructions from the CPU
Start addresses (SXo, SYa), (DXo
, DYo ), number of steps in X direction 5XSTP, DX
STP, number of steps in Y direction 5YSTP.

DYSTP, the number of repetitions in the X direction M1 the number of repetitions in the Y direction, etc. are set, and the main scanning direction is, for example, the X direction, and the X, Y
Access is performed by sequentially adding the number of steps in both directions. During this time, image transfer within the image buffer memory 5 is performed by the image bus switching control circuit 17 simply inputting and outputting image information and read and write control signals.

FIGS. 11(a) to 11(g) show that image transfer can be performed in various ways by selecting the direction in which the two two-dimensional address generation circuits 7.8 generate the transfer source and transfer destination addresses. In the image transfer shown in FIG. 9, both of the two address generation circuits use the main scanning direction as the X direction, and generate addresses by sequentially adding steps.
). As shown in the flowchart in Figure 10 of Ryuteki, the main scanning direction is selected as the X direction or the Y direction, and the number of steps for generation of the X direction address and Y direction address is added sequentially to the start address. By specifying whether to go forward or down, image editing such as 90° rotation, 180° rotation, horizontal reversal, vertical reversal, arbitrary angle rotation, etc., as illustrated in FIG. 11, becomes possible.

Furthermore, in the example of image transfer described above, it is possible to perform simple scaling processing by simply changing the number of steps set in the two-dimensional address generation circuit for the transfer source and the two-dimensional address generation circuit for the transfer destination.

In other words, if the number of steps at the source and destination are the same, an image of the same size will be transferred, but if the number of steps at the destination is set to 172, the image at the destination will be the same as the source image. /2
It will be reduced. In this case, there is no need to use the scaling function of the scaling circuit 11 shown in FIG.

Similar to image transfer within the image buffer memory 5, image transfer within the display memory 6 is also possible. Access control by the address generation circuits 7 and 8 in this case is performed using the address bus 20 and control bus 21 on the image bus ■ side, and image information is also transferred via the data bus 23 on the image bus ■ side. Ru.

In addition, at the same time as transferring image information between the image buffer memory 5 and the display memory 6 as described above, for example, writing an image from the scanner 13 to the image buffer memory 5, the graphic processing circuit 1
Image processing such as writing a character pattern from 2 to the display memory 6 and displaying it on the display is also easily possible by access control by the two two-dimensional address generation circuits 7 and 8. In these image processes as well, the image bus switching control circuit 17, scanner/printer interface 15, graphic processing circuit 12, etc. simply handle reading and writing control signals and image information without being conscious of controlling access to each memory. Image information can be two-dimensionally stored in a predetermined area of each memory by simply transferring the image information to the necessary bus. Since the two two-dimensional address generation circuits 7.8 can each operate independently, they do not affect each other, and the direction and unit of address generation can be set independently. For example, when inputting an image from the scanner 13 to the image buffer memory 5 in units of 16 bits, the number of steps of the two-dimensional address generation circuit 7 selected for the image buffer memory 5 side is set to 16, while the number of steps of the graphic processing circuit 12 is set to 16. When writing image information in units of 8 bits from the display memory 6 to the display memory 6, the number of steps of the two-dimensional address generation circuit 8 selected on the display memory 6 side may be set to eight.

Also, the screen size in each memory (the vertical and horizontal width of the area)
may also be different.

By providing the two two-dimensional address generation circuits 7 and 8 between the two image buses and (1) as described above, it is necessary to provide access control means for each of the various means for transferring information to the image buffer memory and display memory. disappears. Moreover, as mentioned above, since the two address generation circuits 7 and 8 are configured as exactly the same hardware, the control program and the scale of the hardware can be reduced, and the development period can also be shortened. can. Further, by simply changing the commands and parameters for each of the two-dimensional address generation circuits 7 and 8, it is possible to perform various types of access control and execute various image editing processes as described above.

By the way, in Figure 8, the addresses of the output X and Y coordinates are output as they are as two-dimensional addresses, but in reality, the X addresses corresponding to the X and Y coordinates of the two-dimensional area of the image are output. and Y address are given to the memory as a one-dimensional address as a lower address and an upper address of the memory, respectively. For example, as shown in FIG. 12(a), the memory space of 211 X 21 Z (-2048 dots x 4096 dots) is usually 8 bits (
A one-dimensional continuous memory space is constructed in units of 16 bits or 16 bits, etc., as shown in FIG. 12(b). In this case, if the address is a bit address, AIO~ARO (AII is on the LSB side) is the X address, A22~A11
(A22 is MSB side) as Y address and A22 to An
can be given to memory. In such a memory space, for example, 1728 dots x as shown by diagonal lines in Fig. 12(C)
When an image of 2,400 dots (e.g., equivalent to an A4 size image of 8 dots/M) is stored in memory, a part of the continuous memory space is actually stored discretely as shown by diagonal lines in Fig. 12(d). The memory will be used in an exclusive manner, resulting in poor memory usage efficiency.

Additionally, when editing images of various sizes, the development of editing programs would require direct handling of physical addresses that depend on the implemented memory configuration.

It is inconvenient to improve, and flexible management of document images is difficult.

The present invention performs address control that solves these problems.

FIG. 13 shows an embodiment of an address generation circuit that solves this problem and allows the memory space expressed by -dimensional addresses to correspond to various image sizes so that it can always be used efficiently.

In this configuration, in addition to the basic configuration shown in FIG. 8, an xW register 83 set by the CPU 1 for weighting the Y address in accordance with the image size is provided, and this xW register 83 and multiplexers 78x, 78y An address conversion circuit 82 is provided for generating continuous one-dimensional addresses using the output of the address converter 82.

FIG. 14 shows a specific configuration example of this address conversion circuit 82. The multiplier 821 multiplies the value xW set in the xW register 83 by (XW)X(Y) by the Y address from the multiplexer 78y. Adder 822 is
The multiplication result of the multiplier 821 and the X address of the multiplexer 78x are added to calculate A=(XW)x(Y)+(X), thereby converting the two-dimensional address into a one-dimensional address. If the output A of this adder 822 is directly output to the address bus 18 or 20, the logical address of the memory becomes the physical address and the image buffer memory 5
Alternatively, it is given to the display memory 6 as a one-dimensional address. Since the above-mentioned value of XW is arbitrarily set depending on the image size at the time of editing, image information of an arbitrary-sized area can be continuously stored in a one-dimensional memory space using the above formula. That is, it is possible to eliminate unnecessary memory areas as shown in FIGS. 12(C) and 12(d). Furthermore, by performing address conversion on the output A of the adder 822 using the conversion table 823, images of various sizes can be managed flexibly.

A specific example of image management using this address conversion will be described next. For example, as shown in FIG. 15, three types of component images A, B, and C of different sizes are stored in an image buffer memory 5, and their physical addresses, logical addresses, component numbers, etc. are managed. The part with number 1 has physical address oooo
It is stored in a continuous area from o to 01FFFu (hexadecimal number), and the part with number 2 has physical address 0200008.
It is stored in a continuous area from ~037FFFH,
The part with number 2 is logically located at logical address 00000H ~
It is managed as being stored in 017FFFH. The same applies to the part numbered 3. Let us now consider the case where image B of part number 2 is deleted and part surface l1lD is registered. When part number 2 is deleted, the physical address of image buffer memory 5 is 020000H to 037FFFH.
The area below 070000H becomes a free area. However, since the physical addresses necessary for registering a new part image are not consecutive, it has not been possible to register this using the deleted address area of part image B in the past. In the present invention, by rewriting the contents of the conversion table 823 in FIG. 14, discrete areas can be treated as if they were continuous areas. That is, in this case, the conversion table 823 is converted to physical address 03 by CPU.
8000H~06FFFFH 050000H~087
FFFH, 070000u~087FFFuJlr0
Change it so that it becomes 38000H to 04FFFFH. As a result, as shown in FIG. 16, a continuous address area can be secured for the component image, and component image information with component number 4 is newly added.

By rewriting the contents of the conversion table 823 in this way, parts and documents of various sizes can be managed and handled consistently, and the image buffer memory 5 and display memory 6 can be used effectively. In addition, conversion between logical addresses and physical addresses can be done flexibly, and complex parts management, memory management, etc. can be processed using logical addresses in the management program, and development efficiency and reliability of the management program can be improved.

FIG. 17 shows a schematic configuration of the conversion table 823 of the address conversion circuit 82 as described above. The RAM 8231 is a core memory of the conversion table 823 and stores conversion data. The write data port 8232, the write address port 8233, and the read address port 8234 are each three-state ports, and are turned on only when writing or reading conversion data. When writing conversion data, enable the write address port 8233 from the CPU interface 71 and write R.
Set the write address of AM8231 and write the write data from the write data port 8232. At the initial stage, conversion data is written so that the read address from the adder 822 is outputted from the RAM 8231 without being passed through. For example, if the read address from the adder 822 is 0000H to 07FFH, the RA
Conversion data is also written so that the output of M8231 becomes 0000H to 07FFH. Next, as shown in FIG. 16, when handling various parts, the contents of the RAM 8231 are rewritten as described above to output the necessary physical addresses in accordance with the management of each part. For example, leave AO to A14 as is among addresses AO to A25, and
If IS~A25 can be mapped through the conversion table 823, in order to change the physical address 038000n of part number 3 in FIG. 15 to the physical address 050000H of part number 3 in FIG. Address 0007u of RAM8231 is set to 00
Just rewrite it to OAH. If other data are sequentially rewritten in the same way, they will be mapped to physical addresses as shown in FIG.

In the concrete prototype example of the present inventors, the X address,
The Y address and
6-64 Mbits, i.e., 8 dots/M, which can handle images up to AO), and then the upper 1
One bit is converted from a logical address to a physical address using a conversion table 823. This makes it possible to map addresses in units of 4 bytes (1 byte - 8 bits), 8 dots/11 Il! In the case of I, it is possible to logically handle images of various sizes using 22° 6 #l 111 square images as a unit, and to flexibly occupy and release memory areas of various sizes, including 9 divisions and 1 addition. Became.

The address conversion circuit 82 is not limited to that shown in FIG. For example, the entire address conversion circuit 82 is stored in RAM or RO.
It can be configured with a memory such as M. In this case, the value of address conversion according to various image sizes is
U1 etc. are calculated using the above formula, the value is written to RAM or ROM, and the multiplexer 78x, 78
Address conversion is performed with reference to the X address and Y address of y and the set value XW of the XW register 83, and the results are provided to the interfaces 80X and 80Y. Further, the multiplier 821 in the address conversion circuit 82 may also be a multiplier-dedicated LSI, or may be configured by combining adders.

FIG. 18 shows the operation flow of the address conversion circuit 82 when the function of the multiplier 821 is realized using an adder. In this case, when the Y address is ±1, ±XW
After adding up and performing the multiplication process of (XW) x (Y),
Addition of (XW)x (Y)+(X) is performed. Furthermore, the conversion table 823 can be written at any time, during or before or after operation. Naturally, the units to be converted using the conversion table 823 are appropriately set depending on the performance, specifications, purpose, etc. of the device.

The invention is not limited to the embodiments described above. For example, as shown in FIG. 19, the scanner/printer interface 15 and the compression/expansion circuit 16 may also be connected to the image bus (2).

With this configuration, the enlargement/reduction circuit 111, the graphic processing circuit 12. Scanner/printer interface 15. All the compression/decompression circuits 16 are connected to two image buses and (1), and each of them can access the image buffer memory 51 and display memory 6 using a free bus, increasing the flexibility of the entire system. The speed is further increased.

Furthermore, the two two-dimensional address generation circuits 7 and 8 are integrated into one module, and internally there are two systems of memory (an image buffer memory and a display memo 1, or a transfer source and a transfer destination in one memory). ) Access control may be performed. In this case, one two-dimensional address generation circuit should be configured to output addresses for the image buffer memory 51 and display memory 6 in a time-sharing manner (XoAlso, when transferring images between memories, the transfer source and transfer destination addresses may be output in a time-sharing manner. Similarly, the data may be output to each memory in a time-division manner.

As a method for this time division, two systems are installed (1) including an output stage from the address conversion circuit 82 and a latch.

The latched address can be output-enabled at each output time and output to the address bus.

Conversely, the two-dimensional address generation circuit may be configured with three or more modules to increase A speed and flexibility.

Further, when the image buffer memory 5 and display memory 6 are not IC memories but disk memories such as magnetic disks or optical disks, the addresses generated from the two-dimensional address generation circuit 7.8 are track numbers, sector numbers, disk memories, etc. It will be composed of information such as numbers. In this case as well, memory access control can be performed in the same manner as in the above-described embodiment. The same applies when other memories such as magnetic bubble memory and hologram memory are used.

Furthermore, by operating one of the two-dimensional address generation circuits 7.8 in combination with the image bus switching control circuit 10, simple graphic processing such as straight lines, diagonal lines, and filling in rectangular areas can be performed quickly and easily. can. For example, data "FO" (hexadecimal number) is set in the image bus switching control circuit 10, and the image bus switching control circuit 10 is set to "FO" (hexadecimal number).
FO" data and a data write control signal are output to the data bus 22 and control bus 19, respectively, and the two-dimensional address generation circuit 8 sequentially outputs addresses to the address bus 20. Then, the display memory 6 has a line width of 4. Bit straight lines can be drawn.

When data "s o" is set in the image bus switching control circuit 10, a straight line with a line width of 1 bit can be drawn. Furthermore, when data of 'FF' is set, the specified area can be filled in with white or black.

[Brief explanation of drawings]

Figure M1 shows the overall configuration of an embodiment of the document image processing device according to the present invention, Figure 2 shows the configuration of its enlargement/reduction circuit, and Figure 3 shows how the enlargement/reduction circuit captures image concessions. FIG. 4 is a diagram showing an example of the configuration of the image information sending section, FIG. 5 is a diagram showing an example of the bus configuration in the configuration of FIG. 1, and FIG. 6 is a diagram showing the timing of control signals. FIG. 7 is a diagram showing a configuration example of a response signal sending unit for a control signal from another device using a plurality of means, FIG. 8 is a diagram showing a basic configuration example of a two-dimensional address generation circuit, and FIG. 9 is a diagram showing a chart. is a diagram for explaining the operation of image transfer, and FIG. 10 is a diagram showing the flow of address generation in the address generation circuit. ! 11 <a> to (Q) are diagrams showing various access control examples for image editing, and FIGS. 12 (a) to (d) are diagrams for explaining the operation of normal one-dimensional address generation. FIG. 13 is a diagram showing a specific example of the configuration of a two-dimensional address generation circuit according to an embodiment of the present invention, FIG. 14 is a diagram showing an example of the configuration of the address conversion circuit section, and FIGS. FIG. 17 is a diagram illustrating an example of the configuration of the conversion table of FIG. 14, and FIG. 18 is a diagram illustrating the flow of one-dimensional address generation in the address conversion circuit. , FIG. 19 is a diagram showing the configuration of a document image processing apparatus according to another embodiment. 1... CPU, 2... CPU memory, 3... Interface, 4... CPU bus, 5... Image buffer memory, 6... Display memory, 7, 8... Two-dimensional address Generation circuit, 10... Vertical/horizontal conversion circuit, 11...
Enlargement/reduction circuit (including information transfer mediating means), 12... Graphic processing circuit, 13... Scanner, 14... Printer, 15... Scanner/printer interface, 16
. . . Compression/expansion circuit, 17 . . . Image bus switching control circuit, 18° 20 . . . Address bus, 22, 23. 24.
26...Data bus, 19.21, 25.27...
Control bus, 34... Active input operating mechanism, 35
...passive input operation mechanism, 37...active output operation ms
, 38... Passive output operation mechanism, 82... Address conversion circuit, 823... Conversion table. Applicant's Representative Patent Attorney Takehiko Suzue λ1'Jgj Request No. 11 Figure 3 Figure 4 Figure 7 Figure 11 l. ,' @Transfer L Transfer Probation License Figure 11 (C) Figure 12

Claims (1)

[Claims] An image buffer memory that temporarily stores document image information, a display memory that temporarily stores document image information to be displayed, an input/output means for document image information, an image bus used for transferring document image information, and manages and controls these. an image bus switching control circuit that controls connections between the image buffer memory and display memory and the image bus; and an image bus switching control circuit that is connected to the image bus and controls the image buffer memory and display memory. A document image processing device comprising two two-dimensional address generation circuits each controlling access.