JPS623378A - Document picture processor - Google Patents

Abstract

PURPOSE:To increase the document picture processing speed by using the picture buses of two systems which can be actuated independently of each other. CONSTITUTION:Information is transferred among a picture buffer memory 5, a display memory 6 and each processing circuit via the picture buses I and II which can be actuated independently of each other. In addition, two 2-dimensional address generating circuits 7 and 8 are provided between both buses I and II for simultaneous access control to both memories 5 and 6. These two memories 5 and 6 are connected only to data buses 22 and 23 respectively. The part between the bus 22 and a data bus 24 connected with a magnification/ reduction circuit 11, a graphic processing circuit 12, etc. At the same time, the part between a data bus 20 at the side of the memory 6 and a data bus 26 connected with the circuit 11, the circuit 12, etc. is also divided. Then the connection among those divided parts is controlled by a picture bus switch control circuit 17.

Description

DETAILED DESCRIPTION OF THE INVENTION (Technical Field of the Invention) The present invention relates to a document image processing device that electronically performs input, output, display, editing, etc. of document images.

(Technical background of the invention and its problems) As typified by facsimiles and electronic files,
Document image processing devices that electronically process document images are being actively developed. The purpose of developing these devices is to improve work efficiency by digitizing conventional paper-based general work, especially office work, and to make it easier to handle complex work as work becomes more sophisticated. It's about doing. These devices scan a document image with a scanner, convert it into an electrical signal, compress it and transmit it, or store it in an image memory, process it, and then output it to an image printer. Information processing is performed.

In such a document image processing apparatus, in order for a user to operate it arbitrarily to truly improve work and improve work efficiency, the following points must be fully considered. First, it is easy and flexible to transfer document image information between the various means that make up the system. If transfer between certain means is not possible, or if it is possible but requires many steps, the scope for improvement will be limited. The second is that the processing speed is high.

In this type of device, the operability of the device as well as the functions it can process are important factors that determine the performance of the device. Among these, processing speed is one of the decisive points for the device's man-machine interface, and unless it satisfies a certain level or higher, work efficiency may be adversely reduced.

However, in conventional document image processing devices, these two points are not necessarily satisfied.

For example, information can be transferred flexibly between each means but the transfer speed is extremely slow, or high-speed information transfer is possible but the transfer destination is limited, or flexible transfer can be performed relatively quickly. However, the hardware mechanism and procedures up to the start of transfer were usually extremely complicated. This does not allow for sufficient improvement in work efficiency.

Furthermore, in conventional devices, each means that needs to access the image buffer memory and display memory, such as scanners, printers, scaling circuits, etc., each has an access control circuit, making it possible to perform advanced image editing processing. In order to do this, there is a problem in that the hardware of each of these means and the program that controls the access control circuit thereof become complicated.

[Purpose of the invention]

The present invention has been devised in view of the above-mentioned points, and it extremely facilitates the simultaneous transfer of document image information between multiple means constituting the system, improves system throughput and speeds up processing, and achieves high performance with a simple configuration. An object of the present invention is to provide a document image processing device that can perform image editing processing.

[Summary of the invention]

The present invention provides at least an image buffer memory for temporarily storing document image information, a display memory for displaying document images, an input/output means for document image information, an image bus used for transferring document image information, and management of these. In a document image processing device having a control device for controlling the image bus, two image buses capable of operating independently as image buses are provided, and the connection between the image buffer memory and the display memory and the two image buses is controlled. an access control circuit connected to the image bus and providing continuous one-dimensional addresses corresponding to a plurality of two-dimensional areas of different sizes to the image buffer memory and display memory; It is characterized by having the following.

〔Effect of the invention〕

Since the document image processing apparatus according to the present invention has two image buses that can operate independently, it is possible to access the image buffer memory and the display memory simultaneously, thereby improving the throughput of the system. In addition, by connecting the access control circuit to two image buses, there is no need to be aware of the size of the two-dimensional image area when storing images in the memory space, and images of various sizes can be stored. Memory space can be used without wastage, and various image editing can be performed with the minimum memory size. Furthermore, by equipping the access control circuit with a conversion table that converts the physical address and logical address of the memory, it becomes possible to develop various editing processing programs independently of the device-dependent physical addresses, reducing the program development period. This enables shortening of time and easy porting. In addition, editing processing for various image sizes can be performed flexibly using logical addresses, allowing sophisticated management of document images.

(Example of the invention) The present invention will be described in detail below with reference to the drawings.

FIG. 1 is a schematic block diagram of a document image processing apparatus according to an embodiment. 1 is an information processing unit (hereinafter referred to as CPU) that is a device that manages and controls this device; 2 is a CPU program memory that stores a program that describes this control procedure;
3 is an interface for connecting the CPU 1 with other input/output devices such as a CRT terminal. In the present document image processing apparatus, a control signal from the CPU 1 is applied via the CPU bus 4 to a memory that stores document image information and to a document image processing means to execute desired processing.

5 is an image buffer memory for temporarily storing document image information;
6 is a display memory that temporarily stores document image information to be displayed, and 7 and 8 are two-dimensional address generation circuits that generate addresses for accessing two-dimensional rectangular areas in these memories. Reference numeral 9 denotes a display controller that takes in data from the display memory 6 according to the display cycle and controls the data to be displayed on the display. 10 is a vertical/horizontal conversion circuit that rotates the orientation of the document image every 90 degrees; 11 is a document image enlargement/reduction circuit; 12 is a graphic processing circuit that generates a character pattern and draws it in the display memory 6 and image buffer 7 memory 5. It is. 13 and 14 are scanners and printers that are input/output means for document images; 15;
is a scanner-printer interface having a function of importing document image information read by the scanner 13 and a function of importing document image information stored in the memories 5 and 6 and sending it to the printer 15.

16 demodulates and decompresses compressed document image information transferred from an external communication control device and imports it, or the memories 5 and 6
This is a compression/expansion circuit that compresses and modulates document image information and sends it to the outside.

In order to transfer information between the above image buffer memory 5 and display memory 6 and each processing circuit, the present invention provides two systems of image buses and (2) that can operate independently. Here, the image bus includes an address bus 18 for the image buffer memory 5, a data bus 22 to which the image buffer 7 memory 5 and the vertical/horizontal conversion circuit 10 are connected, an enlargement/reduction circuit 111, a graphic processing circuit 12, a scanner/printer interface 15, and a compression circuit. It collectively refers to the data bus 24 to which the decompression circuit 16 is connected, and the control bus 19.25, and the image bus (■) is the address bus 20 for the display memory 6, to which the display memory 6 and the vertical/horizontal conversion circuit 10 are connected. data bus 2
3. It collectively refers to the data bus 26 to which the enlargement/reduction circuit 11 and the graphic processing circuit 12 are connected, and the control buses 21 and 27. In this embodiment, the image buffer memory 5
is connected to only one data bus 22, and the display memory 6
is connected only to the other data bus 23.

Therefore, the data bus 22 on the image buffer memory 5 side and the data bus 24 to which the scaling circuit 111, graphic processing circuit 12, etc. are connected are divided, and the data bus 20 on the display memory 6 side and the scaling circuit 11° graphic The data bus 26 to which the processing circuit 12 and the like are connected is divided, and the connection therebetween is controlled by the image bus switching control circuit 17.

Some processing operations performed by the document image processing apparatus configured as described above will be described below.

(1) When transferring data between the scanner 13 or printer 14 and the image buffer memory 5, the image bus switching control circuit 17 connects the data buses 22 and 24 and the control buses 19 and 25. 2
Data transfer is performed via 4. During this time, if it is desired to output graphic data or the like to the display memory 6, this is done via the data buses 23 and 26.

(2) When the data in the image buffer memory 5 is rotated and printed out, the data bus 22 and the aspect conversion circuit 10 are connected, and the data from the image buffer memory 5 enters the aspect conversion circuit 10 and is converted into a 90 After being rotated, it is output to the printer 14 via the data bus 24 via the bus switching control circuit 17. During this time, access to the display memory 6 via the data buses 23 and 26 is possible.

(3) When writing the input from the scanner 13 to the image buffer memory 5 while simultaneously reducing it and rotating it and writing it to the display memory 6, the data flowing through the data bus 24 is reduced while being taken in by the enlarging/reducing circuit 17. and output to the data bus 26. The vertical/horizontal conversion circuit 10 is connected to the data bus 23
The reduced image data is rotated by 90' and written into the display memory 6.

(4) 'Scanner 13 or printer 14 on the image bus
When image data is being transferred between the image buffer 7 memory 5 and the image buffer 7 memory 5, when a character pattern or the like is enlarged or reduced and written to the display memory 6, the character pattern in the graphic processing circuit 12 is transferred to the data bus 26 by the clock from the enlargement/reduction circuit 11. The image is once taken into the enlarging/reducing circuit 11 via. After the enlargement/reduction process, the data is again written to the display memory 6 via the data buses 26 and 23. In this case, the transfer of image data is controlled on the image bus π in synchronization with the read clock and write clock of the enlargement/reduction circuit 11.

(5) When the data in the image buffer memory 5 is enlarged or reduced and written to the display memory 6, the data in the image buffer 7 memory 5 is sent to the enlargement/reduction circuit 1 via the data bus 22, 24.
1, and its output data is transferred to data bus 26.2.
3 to the display memory 6. In this case, read data runs on the image bus (2) and write data runs on the image bus (2), and high-speed data transfer is performed by the vibrating operation of the enlargement/reduction circuit 11.

Furthermore, the image is converted into a bus via an aspect/horizontal conversion circuit 10.

■If darkness is connected, advanced data processing that rotates and scales data will be performed at extremely high speed.

(6) By connecting the data buses 24 and 23, data transfer between the display memory 6 and the scanner 13 or printer 14 is possible.

In the above image information processing operation, two image buses ■
In order to perform flexible and high-speed processing using data transfer between

Image information transfer media between π plays an important role.

That is, this information transfer mediating means is capable of flexible and sophisticated information processing by providing an active operating mechanism and a passive operating mechanism in the information importing section and the transmitting section, respectively. In this embodiment, the information mediating means having such a function is integrated into the enlarging/reducing circuit 11.

Figure 2 shows an enlargement/reduction circuit 1 equipped with such information mediating means.
This is an example of configuration 1. In the figure, 31 is an enlargement/reduction calculation mechanism, 32 is an input data latch circuit, and 33 is an output data latch circuit. The data acquisition section includes an active input operating mechanism 34 and a passive input operating mechanism 35, and 36 is a selector for a latch signal of input data outputted from these.

The data sending section similarly includes an active output operating mechanism 37 and a passive output operating mechanism 38, and 39 is an end signal selector for the data output sequence outputted from these. A control circuit 40 performs sequence control using these input/output operation mechanisms.

41 to 50 indicate input/output buffers. Although not shown in the figure, input data, output data, and control signals such as transfer lock can be selectively connected to image bus (2) and image bus (2).

In the image information capture section, during active operation, the active input operation mechanism 34 outputs a data read control signal PRDC, and input data is captured in response to the response signal PACK, and during passive operation, an external data write control signal PW is output.
The passive operating mechanism 35 is operated by the TC to take in input data. FIG. 3 shows a specific example of the configuration of this image information importing section. The active input operating mechanism 34 includes a PRDC generator 341 that generates a data read control signal PRDC and an AND gate 342. The passive input operating mechanism 35 is composed of an AN[) gate 351. When the input request signal from the sequence control circuit 40 is not output, the AND gate 351 is in a prohibited state, and even if it receives the data write control signal PWTC, it does not return the response signal PACK and makes the external means stand by. It has become.

In the image information sending section, during active operation, the active output operating mechanism 37 outputs the data write control signal PWTC to send out data, and the sending operation is completed in response to a response signal PACK. During passive operation, the passive output operation mechanism 38 receives an external data read control signal PRDC and ends the data sending operation. FIG. 4 shows a specific example of the configuration of this image information sending section. The active output operation mechanism 37 includes a PWTC generator 371 that generates a data write control signal PWTC.
and an AND gate 372. The passive output operating mechanism 35 is composed of an AND gate 351.

Enlargement/reduction circuit 1 equipped with image information mediating means as described above
1, the image bus 1. A specific operational example of mediated transfer of image information between I will be described next.

The specific bus configuration in this embodiment is as shown in FIG. 5, for example. Address buses 18 and 19 for accessing the image buffer memory 5 and display memory 6 are A11.
=26 A2s, data bus 22, 23.24.26
There are 16 lines of Do=Dxs. Control signal buses 19, 21° 25, 27 include a data read control signal PRDC as a clock for image information transfer, a data write control signal PWTC, and a response signal PA for these.
In addition to CK, there is also a horizontal line end signal HEND.

There are six in total, one for each control signal of the vertical end signal VEND, and one for the selection signal ADSEL of the two sets of address generation circuits 7.8.

First, the sentence stored in the image buffer memory 5! The operation of displaying an image on the display will be explained. In the case of this image processing operation, the image buffer 7 memory 5 is connected to the image bus, and the display memory 6 is connected to the image bus. Connection relationships are selected so that they are respectively connected to bus ■. First, the enlargement/reduction circuit 11 having an image information mediating means has an active input operation mechanism 34 at an image information take-in section and a send-out section, respectively.
, is activated to activate the active output operating mechanism 37. When the enlargement/reduction circuit 11 starts operating, an image pamphlet containing document image information is displayed. A data read control signal PRDC is output from the active input operation mechanism 34 to the memory 5. One of the two sets of address generation circuits 7 and 8 is assigned to the address generation circuit that accesses the image buffer memory 5, and the address is sequentially updated in accordance with the data read control signal PRDC from the enlargement/reduction circuit 11. Response signal P to data read control signal PRDC
ACK is returned from the image buffer memory 5 on the PACK line, and the enlargement/reduction circuit 11 uses its active input operation mechanism 3.
4 receives this, the image information from the image buffer 7 memory 5 is taken into the input data latch 32. The image information captured in this way is subjected to predetermined enlargement or reduction processing by the enlargement/reduction calculation mechanism 31.

The enlarged or reduced image information is sent by a data write control signal PWTC outputted from the active output mechanism 37 of the same enlargement/reduction circuit 11 to the display memory 6. In this case as well, one of the address generation circuits 7 and 8 is assigned to access the display memory 6, and the address is sequentially updated in accordance with the data write frJqII7 signal PWTC. This data write control signal PWT
The response signal PACK to C is sent from the display memory 6 to PAC.
The signal is output onto the K line and taken into the active output mechanism 37 of the enlarging/reducing circuit 11. As a result, the enlarging/reducing circuit 11 moves to the next sequence.

The timing of the above image information transfer is as shown in FIG.

Next, a case will be described in which document image information is taken in from an external device via the image input/output means, written into the display memory 6, and displayed. The compression/expansion circuit 16 will be taken as an example of image input means.

When displaying document image information imported from an external device, if you want to display it at the same size as when it was imported,
The compression/expansion circuit 16 operates as an active operation means, sends out the transfer control signal by itself, and writes it into the display memory. However, especially in the case of display, the display size of a document image is limited due to various displays that interact with the system, and there are many cases where it is desired to display the document image in a reduced size. Conventionally, the method taken to meet this request is to separate only the display portion from the rest and perform scaling processing only when writing to the display memory. According to this method, flexible scaling is possible for display, but scaling processing is limited to display, and for example, it is possible to scale a part of the document image information stored in the image buffer memory and use it for other purposes. It becomes impossible to perform processes such as copying to the image buffer memory, or enlarging or reducing the document image stored in the image buffer memory and printing it out.

In this embodiment, there are two image buses 1. ff, and by providing the enlargement/reduction circuit 11 with the above-mentioned transfer mediating means, it is possible to write the document image information taken in from the outside into the display memory 6 or the image buffer memory 5 as is, or It is also possible to perform enlargement or reduction processing via the enlargement/reduction circuit 11 before writing. In the former case,
The captured information is directly written into the display memory 6 by the data write control signal PWTC output from the compression/expansion circuit 16. At this time, the image information is transferred from the data bus 24 via the image bus switching control circuit 17. The data is transferred via the data bus 23. In the latter case, the passive input operation mechanism 35 of the enlarging/reducing circuit 11 is operated, and the enlarging/reducing circuit 11 is operated according to the data write control signal PWTC from the compression/expansion circuit 16.
The image information is taken in, subjected to enlargement or reduction processing, and then written to the display memory 6 by the data write control signal PWTC output from the active output operation mechanism 37 of the enlargement/reduction circuit 11. That is, at this time, the compression/expansion circuit 1
The image information taken in by 6 enters the data bus 26 from the data bus 24 through the enlargement/reduction circuit 11, is sent to the data bus 23 via the image bus switching circuit 17, and is written into the display memory 6. , follow this route.

As described above, according to the present embodiment, extremely flexible image processing is possible in terms of image information transfer between the image buffer 7 memory 5 and display memory 6, external writing of image information to the display memory 6, etc. . Moreover, as is clear from FIGS. 2 to 4, the image information transfer mediating means between the two image buses I and IF is realized by extremely simple hardware.

By the way, as seen in the previous explanation, it is often necessary to perform enlargement/reduction processing on the document image information imported from the image input/output means before displaying it, but it is also necessary to perform some kind of processing on the text image information imported at the same time. For example, it may be necessary to copy a portion or overlay other edges. Alternatively, it may be necessary to successively change the reduction ratio of the same document image in order to set it in a state that is most easily viewed by the user. In this case, it is necessary to store the document image being displayed in the image buffer memory and read it out for display or image editing processing as needed. Conventionally, this processing requires two phases: first, storing the document image information in the image buffer memory, and then displaying it, and therefore, sufficient processing speed cannot be obtained.

In the present invention, as already mentioned, two systems of image buses I and [ are provided, and these can operate independently.
The means for sending document images can simultaneously transfer images to a plurality of other means.

In the above operation example, 1. The document image information sent from the image input/output means can be transferred to the image buffer memory and the display memory at the same time. A problem with such simultaneous transfer is the difference in the capture speeds of the plurality of capture sides. In the present invention, this problem can be solved by configuring the respective response signals to the transfer lock to be logically ANDed on the image bus.

FIG. 7 is a diagram for explaining such an embodiment. In the figure, 61 is the PACK line on the control signal bus, 62+, 622.

623 respectively send a response signal P to this PACK line 61.
This is a PACK output stage of each means that outputs ACK. Each output stage consists of an oven collector 1-63 and its movable control gate 64, and is movable when the enable signal EN is high.

With such a configuration, the response signal PAC issued by the plurality of means
The PACK line 61 does not go high while any one of KI-PACK3 is low, and the PAC does not start until the outputs of all the PACK output stages 621 to 62 go high.
K line 61 becomes high. This makes it possible to maintain complete synchronization of image information transfer, allowing simultaneous transfer to multiple means.

Note that, instead of adopting the configuration of calculating logical product using a gate circuit as shown in FIG. 7, it is also possible to adopt a method in which, for example, only the response signal PACK of the means with the slowest response is returned to the PACK line. .

This is also substantially the same as performing logical AND on the same bus, and the same effect can be obtained.

Next, the configuration and operation of the memory access control circuit portion in the device of the present invention will be explained in more detail.

As shown in FIG. 1, this device uses two two-dimensional address generation circuits 7 in order to simultaneously control access to the image buffer memory 5 and the display memory 6.
and 8 are provided between the two image buses ■ and ■.

Considering only the image information transfer between the image buffer memory 5 and the display memory 6 and the information transfer between these memories and other means, the two-dimensional address generation circuits 7 and 8 have one for the image buffer memory 5 and the other for the image buffer memory 5. is for display memory 6,
Although they may be fixedly connected to different image buses 1 or 2, in the embodiment shown in FIG. It has become. This is image buffer memory 5
This is so that image information can be transferred only within the display memory 6 and only within the display memory 6. When performing image information transfer as described above, the image bus switching control circuit 17
, the enlargement/reduction circuit 11, the graphic processing circuit 12, the scanner/printer interface 15, the compression/decompression circuit 16, etc., simply input and output only the control clock for writing and reading image information and image information to the image bus ■ or ■. In many cases, there is no need to control access to the image buffer memory 5 or the display memory 6.

FIG. 8 shows a schematic configuration of the two-dimensional address generation circuits 7 and 8. 71 connects this address generation circuit to the CPUI
72 is a register selected by the CPU 1 and set with a command CMD necessary for access control; 73x, 74x, 7
5.x, 73y, 74Y, and 75Y are the same <Start address X5TA, YSTA related to X and Y coordinates selected by CPU1, number of steps that are the minimum unit for calculating the address X5TP, YSTP, number of repetitions of address calculation XN, YN is the register that is set. Counters 76x, 76y, timing control circuit 77, multiplexer 78X.

78Y1 adders 79x and 79y are parts for calculating the X and Y addresses. Multiplexer 78x.

Address data obtained from 78y is interface 8
It is designed to be output to address bus 18 or 20 via 0X and 80Y. 81X.

Reference numeral 81y is an interface for controlling the timing of outputting or stopping address data taken into this address generation circuit by a control signal sent from another device via the control bus 19.21.

These two two-dimensional address generation circuits 7 and 8 are connected to the image bus 1. The following describes the operation of the most basic editing process, such as handling an image in a certain area of a document and pasting it to another area, in a device connected to the I[Q].

FIG. 9 shows the extracted area in the document at this time with a solid line, the transfer destination area with a broken line, and shows the address relationship of each area. When performing image editing like this,
For example, one two-dimensional address generation circuit 7 is selected by the CPU 1 to access the transfer source area, and the other two-dimensional address generation circuit 8 is selected to access the transfer destination, and the commands, X and Y coordinates necessary for access control, The start address, number of steps, number of repetitions, etc. regarding ° are set in each register to enable access control. Next, for example, when the data read control signal PRDC is output from the image bus switching control circuit 17 to the control bus 19 on the image bus T side, the two-dimensional address generation circuit 7 selected as the transfer source starts operating. A predetermined address is calculated and output to the address bus 18 on the image bus side. As a result, the image buffer 7 memory 5 connected to the image bus side is accessed, and the image information in the transfer source area is read out and output to the data bus 22.

When the image bus switching control circuit 17 finishes taking in the transfer source image information from the data bus 22, it then outputs the data write control signal PWTC and the previously read image information to the control bus 19 and the data bus 22, respectively. Control signal P for data writing is sent to control bus 19.
When the WTC is output, the two-dimensional address generation circuit 7 stops outputting address data of the transfer source, and the other two-dimensional address generation circuit 8 selected as the transfer destination starts operating. The two-dimensional address generation circuit 8 generates a transfer destination address and outputs it to the address bus 18, thereby writing image information into the transfer destination area of the image buffer memory 5. When this write process is completed, the image bus switching control circuit 17 outputs the data read control signal PRDC to the control bus 19 in order to read the next image information from the transfer source again, and performs the read process in the same manner as described above. At this time, the two-dimensional address generation circuit 8 stops outputting the transfer destination address, and the two-dimensional address generation circuit 7 calculates and outputs the next address.

By sequentially repeating the above reading and writing process over the entire predetermined area, image information transfer within one document as shown in FIG. 9 is performed two-dimensionally and at high speed. At this time, each address generation circuit 7.8 generates an address by scanning a predetermined area two-dimensionally according to the flowchart shown in FIG. In other words, in the case of image transfer as shown in FIG.
Along with the commands necessary for each address generation circuit, start addresses (SXa, SYo), (DXs
, DY port), number of steps in the X direction 5XSTP, DXST
P, the number of steps in the Y direction 5YSTP, DYSTP, the number of repetitions in the X direction M, the number of repetitions in the Y direction N, etc. are set, and the main scanning direction is set as the X direction, and the step numbers are sequentially added in both the X and Y directions. Access is performed. During this time, image transfer within the image buffer 7 memory 5 is performed by simply inputting and outputting image information and read and write control signals to the image bus switching control circuit 17.

FIGS. 11(a) to (Q) show that image transfer can be performed in various ways by selecting the direction in which the two two-dimensional address generation circuits 7.8 generate the transfer source and transfer destination addresses. In the image transfer shown in FIG. 9, both of the two address generation circuits use the main scanning direction as the X direction, and generate addresses by sequentially adding steps.
). As shown in the flowchart in Figure 10, the main scanning direction is selected as the X direction or the Y direction, and the generation of addresses in the X direction and Y direction is performed by sequentially adding the number of steps to the start address. By specifying whether to increase or decrease the image, image editing such as 90' rotation, 18o rotation, left/right flip, top/bottom flip, arbitrary angle rotation, etc., as illustrated in FIG. 11, becomes possible.

Furthermore, in the example of image transfer described above, it is possible to perform simple scaling processing by simply changing the number of steps set in the two-dimensional address generation circuit for the transfer source and the two-dimensional address generation circuit for the transfer destination.

In other words, if the number of steps at the source and destination is the same, an image of the same size will be transferred, but if the number of steps at the destination is set to 1/2 that of the source, the image at the destination will be the same as the source image. is 1/2
It will be reduced. In this case, there is no need to use the scaling function of the scaling circuit 11 shown in FIG.

Similar to image transfer within the image buffer memory 5, image transfer within the display memory 6 is also possible. In this case, access control by the address generation circuit 7.8 is performed using the address bus 20 and control bus 21 on the image bus ■ side, and image information is also transferred via the data bus 23 on the image bus ■ side. Ru.

In addition, at the same time as transferring image information between the image buffer memory 5 and the display memory 6 as described above, for example, writing an image from the scanner 13 to the image buffer memory 5, the graphic processing circuit 1
Image processing such as writing a character pattern from 2 to the display memory 6 and displaying it on the display can also be easily performed by access control by the two two-dimensional address generation circuits 7 and 8. In these image processing operations, the image bus switching control circuit 17, scanner/printer interface 15, graphic processing circuit 12, etc. simply read data without being aware of access control to each memory.
Image information can be two-dimensionally stored in a predetermined area of each memory by simply transferring the included control signals and image information to the necessary buses. Since the two two-dimensional address generation circuits 7.8 can each operate independently, they do not affect each other, and the direction and unit of address generation can be set independently. For example, when inputting an image from the scanner 13 to the image buffer memory 5 in units of 16 bits, the number of steps of the two-dimensional address generation circuit 7 selected for the image buffer memory 5 side is set to 16, while the number of steps of the graphic processing circuit 12 is set to 16. When writing image information in units of 8 bits from the display memory 6 to the display memory 6, the number of steps of the two-dimensional address generation circuit 8 selected on the display memory 6 side may be set to eight.

Also, the screen size in each memory (the vertical and horizontal width of the area)
may also be different.

As described above, by providing the two two-dimensional address generation circuits 7 and 8 in the two image bus areas and in the background, it is necessary to provide access control means for each of the image buffer memory, display memory, and various means to transfer information. disappears. Furthermore, as mentioned above, since the two address generation circuits 7 and 8 are configured as exactly the same hardware, the scale of the control program and hardware can be reduced, and the development period can also be shortened. Further, by simply changing the commands and parameters for each of the two-dimensional address generation circuits 7 and 8, it is possible to perform various types of access control and execute various image editing processes as described above.

By the way, in Figure 8, the addresses of the output X and Y coordinates are output as they are as two-dimensional addresses, but in reality, the X addresses corresponding to the X and Y coordinates of the two-dimensional area of the image are output. and Y address are given to the memory as a one-dimensional address as a lower address and an upper address of the memory, respectively. For example, as shown in FIG. 12(a), the memory space of 2" I x 2" 2 (=2048 dots
A one-dimensional continuous memory space is constructed in units of 16 bits or 16 bits, etc., as shown in FIG. 12(b). In this case, if the address is a bit address, A22 to An
(80 is the LSB side) is the X address, A22 to A11 (
A22 to An may be given to the memory with A22 as the MSB side) as the Y address. In such a memory space, for example, 1728 dots
When an image of 2,400 dots (e.g., equivalent to an A4 size image of 8 dots per square) is stored in memory, the first
As shown by diagonal lines in FIG. 2(d), a portion of the continuous memory space is occupied in a discrete manner, resulting in poor memory usage efficiency.

Additionally, when editing images of various sizes, the development of editing programs would require direct handling of physical addresses that depend on the implemented memory configuration.

It is inconvenient to improve, and flexible management of document images is difficult.

The present invention performs address control that solves these problems.

Figure 13 shows an address generation circuit that solves this problem and allows the memory space expressed by -dimensional addresses to be used for various image sizes without any waste. This is an example.
This configuration differs from the basic configuration shown in Figure 8 in that it weights the Y address in accordance with the image size.
J"・:,・j XW register 83 set by CPU1
, 1. (← Provide this XW register 83 and multiplexer
1.

:' Continuous one-dimensional aperture using the outputs of 78x and 78y.
.

An address conversion circuit 82 for generating addresses is provided. j
゛,゛(Figure 14 shows a specific example of this address conversion circuit 82.
1. 'I゛.

This is an example of a configuration. Multiplier 821 is an XW register
1f゛, - set to 83 (IXW and multiplexer
:・78yka, 13(7)Y7do,yu,,yo Vr
(XW) If the output A of the adder 822 is directly output to the address bus 18 or 20, the logical address of the memory becomes the physical address and the image buffer memory 5
Alternatively, it is given to the display memory 6 as a one-dimensional address. Since the value of xW mentioned above is arbitrarily set depending on the image size at the time of editing, image information of an arbitrary size area can be continuously stored in a one-dimensional memory space using the above formula. That is, it is possible to eliminate unnecessary memory areas as shown in FIGS. 12(C) and 12(d). Furthermore, by performing address conversion on the output A of the adder 822 using the conversion table 823, images of various sizes can be managed flexibly.

A specific example of image management using this address conversion will be described next. For example, as shown in FIG. 15, three types of component images A, B, and C of different sizes are stored in an image buffer memory 5, and their physical addresses, logical addresses, component numbers, etc. are managed. The part with number 1 is stored in a continuous area from physical address 00000 to 01 FFFH (hexadecimal), and the part with number 2 is stored in a continuous area from physical address 020000H to 037FFFH. The parts logically have logical addresses oooo “OH~017FFF
It is managed as if it were stored in H. The same applies to the part numbered 3. Let us now consider the case where image B of part number 2 is deleted and a part image is registered. When part number 2 is deleted, the physical address of image buffer 7 memory 5 is 020000)1-037FFFH and 070000
The area below H becomes a free area. However, since the physical addresses necessary for registering a new part image are not consecutive, it has not been possible to register this using the deleted address area of part image B in the past. In the present invention, by rewriting the contents of the conversion table 823 in FIG. 14, discrete areas can be treated as if they were continuous areas. In other words, in this case, the conversion table 823
is set to physical address 03800011 by CPU 1.
~06FFFH to 050000H ~087FFFH,
070000H~087FFFH 038000H~0
Change it so that it becomes 4FFFFH.

As a result, as shown in FIG. 16, a continuous address area can be secured for the component image, and component image information with component number 4 is newly added.

By rewriting the contents of the conversion table 823 in this way, parts and documents of various sizes can be managed and handled consistently, and the image buffer memory 5 and display memory 6 can be used effectively. In addition, conversion between logical addresses and physical addresses can be done flexibly, and complex parts management, memory management, etc. can be processed using logical addresses in the management program, and development efficiency and reliability of the management program can be improved.

FIG. 17 shows a schematic configuration of the conversion table 823 of the address conversion circuit 82 as described above. The RAM 8231 is a core memory of the conversion table 823 and stores conversion data. Write data boat 8232,!
The write address port 8233 and the read address port 8234 are each three-state ports, and are turned on only when writing or reading conversion data. When writing conversion data, enable the write address port 8233 from the CPU interface 71 and write R.
Set the write address of AM8231 and write the write data from the write data port 8232. At the initial stage, conversion data is written so that the read address from the adder 822 is outputted from the RAM 8231 without being passed through. For example, if the read address from the adder 822 is 0OOOH~07FFH, the RA
Write the conversion data so that the output of M8231 is also 0OOOH"07FFH. Next, as shown in Figure 16, when handling various parts, write the RAM823 construction as described above in accordance with the management of each part. For example, if Ao - At 4 of addresses AO to A2S is left as is and A1s to A2S can be mapped through the conversion table 823, the parts shown in FIG. In order to change the physical address 038000H of number 3 to the physical address 050000o of part number 3 in FIG.
All you have to do is rewrite it to 0OOAH. If other data are sequentially rewritten in the same way, they will be mapped to physical addresses as shown in FIG.

In the concrete prototype example of the present inventors, the X address,
The Y address and
= 64 Mbits, i.e., can handle images up to AO at 8 dots/m), and furthermore, the upper 1
One bit is converted from a logical address to a physical address using a conversion table 823. This makes it possible to map addresses in units of 4 to 4 bytes (1 byte - 8 bits), and in the case of 8 dots/m, it is possible to logically handle images of various sizes in units of 22° 6 am square images. It is now possible to flexibly occupy and release memory areas of various sizes, including 0 divisions and 9 inclusions.

The address conversion circuit 82 is not limited to that shown in FIG. For example, the entire address conversion circuit 82 is stored in RAM or RO.
It can be configured with a memory such as M. In this case, the value of address conversion according to various image sizes is
Calculate using the above formula using U1 etc. and write the value to RAM or ROM 9. ,.

A, t'a″′・v)I′fj″″″8゛・78“08
7 ・1 do L/2. Y7 de'' and U X W L/
'2983 (7) t y ',,.

Address conversion is performed by referring to the address value XW, and the result is
;”1 Give the result to interfaces 80X and 80Y.
The multiplier 821 in the address conversion circuit 82 may also be a multiplier-dedicated LSI, or may be configured horizontally by combining adders.

FIG. 18 shows the operation flow of the address conversion circuit 82 when the function of the multiplier 821 is realized using an adder. In this case, when the Y address is ±1, ±xW
After adding up and performing the multiplication process of (XW)X (Y),
Addition of (XW)X (Y)+(X) is performed. Furthermore, the conversion table 823 can be written at any time, during or before or after operation. Naturally, the units to be converted using the conversion table 823 are appropriately set depending on the performance, specifications, purpose, etc. of the device.

The invention is not limited to the embodiments described above. For example, as shown in FIG. 19, the scanner/printer interface 15 and the compression/expansion circuit 16 may also be connected to the image bus (2).

With this configuration, the enlargement/reduction circuit 111, the graphic processing circuit 12. Scanner/printer interface 15. The compression/decompression circuits 16 are all connected to two image buses (■ and ■), and each can access the image buffer memory 51 and display memory 6 using a free bus, increasing the flexibility of the entire system.・Further increase in speed・
°: Also, the two two-dimensional address generation circuits 7 and 8 are integrated into one module, and inside it, two systems of memory (image buffer memory and display memory,
Alternatively, access control may be performed for transfer source and transfer destination within one memory. in this case
□In one two-dimensional address generation circuit, address to image buffer memory 59 display memory 6 is done in time division.
It may be configured to output padres. Also mail
When transferring images between 1 memories, the source and destination addresses should be the same and output to each memory in a time-sharing manner. This time division method uses address changes.
, 9' Two output stages and latches from the switching circuit 82 are provided; □ The output enable is latched at each output time.
;" and output it to the address bus. This further reduces the size and cost of the device.

Conversely, the secondary and original address generation circuits may be constructed of three or more modules to increase speed and flexibility.゛Also, the image buffer memory 5 and display memory 6 are not IC memories but magnetic disks or optical disks.
In the case of a disk memory such as ゛;□, the address generated from the two-dimensional address generation circuit 7.8 is composed of information such as a track number, sector number, and disk number. In this case as well, memory access control can be performed in the same manner as in the above-described embodiment. The same is true when further memory such as magnetic bubble memory or hologram memory is used.

Furthermore, by operating one of the two-dimensional address generation circuits 7.8 in combination with the image bus switching control circuit 10, simple graphic processing such as straight lines, diagonal lines, and filling in rectangular areas can be performed quickly and easily. can. For example, data "FO" (hexadecimal number) is set in the image bus switching control circuit 10, and the image bus switching control circuit 10 is set to "FO" (hexadecimal number).
O'' data and a data write control signal are output to the data bus 22 and control bus 19, respectively, and when the two-dimensional address generation circuit 8 sequentially outputs addresses to the address bus 20, the display memory 6 has a line width of 4. Bit straight lines can be drawn.

When data "80" is set in the image bus switching control circuit 1o, a straight line with a line width of 1 bit can be drawn. Furthermore, when data "' F F " is set, the specified area can be filled in with white or black.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing the overall configuration of an embodiment of a document image processing device according to the present invention, FIG. 2 is a diagram showing the configuration of its enlargement/reduction circuit, and FIG. 3 is a diagram showing image concession in the enlargement/reduction circuit. FIG. 4 is a diagram showing an example of the configuration of the image information sending section, FIG. 5 is a diagram showing an example of the bus configuration in the configuration of FIG. 1, and FIG. 6 is a diagram showing the configuration of the control signal. Figure 7 is a diagram showing a timing chart; Figure 7 is a diagram showing an example of the configuration of a response signal sending unit for a control signal from another device using a plurality of means; Figure 8 is a diagram showing an example of the basic configuration of a two-dimensional address generation circuit; The figure is a diagram for explaining the operation of image transfer, Figure 10 is a diagram showing the flow of address generation in the address generation circuit, and Figure 11 (
12(a) to 12(d) are diagrams for explaining the operation of normal one-dimensional address generation, and FIG. 13 is a diagram showing various access control examples for image editing. FIG. 14 is a diagram showing a specific configuration example of the two-dimensional address generation circuit in the embodiment of the present invention, FIG. 14 is a diagram showing a configuration example of the address translation circuit section, and FIGS. 15 and 16 are specific registration Direction (11
17 is a diagram illustrating an example of the configuration of the conversion table of FIG. 14; FIG. 18 is a diagram illustrating the flow of one-dimensional address generation in the address conversion circuit;
FIG. 19 is a diagram showing the configuration of a document image processing apparatus according to another embodiment. 1...CPU, 2...CPU memory, 3...Interface, 4...CPU bus, 5...Image buffer memory, 6...Display memory, 7.8...Two-dimensional address Generation circuit, 10... Vertical/horizontal conversion circuit, 11...
Enlargement/reduction circuit (including information transfer mediating means), 12... Graphic processing circuit, 13... Scanner, 14... Printer, 15... Scanner/printer interface, 16
. . . Compression/expansion circuit, 17 . . . Image bus switching control circuit, 18° 20 . . . Address bus, 22, 23. 24.
26...Data bus, 19,21.25.27...
Control bus, 34... Active input operating mechanism, 35
... Passive input operation mechanism, 37... Active output operation mechanism, 38... 4. Tin passive output operation mechanism, 82...address conversion circuit, ,・
823... Conversion table. Applicant's representative Patent attorney Takehiko Suzue Figure 2 Input die*'4I Figure 3 Figure 4 Figure 5 Figure 6 Figure 7 Figure 9 Figure 11 Payment receipt (a) Figure 14 Figure 17 Figure 16 Figure 18

Claims (3)

[Claims] (1) An image buffer memory that temporarily stores document image information, a display memory that temporarily stores document image information to be displayed,
In a document image processing device that includes an input/output means for document image information, an image bus used for transferring document image information, and a control device for managing and controlling these, a link between the image buffer memory and display memory and the image bus is provided. an image bus switching control circuit that controls connection; and an image bus switching control circuit that is connected to the image bus;
A document image processing apparatus comprising: an access control circuit that provides continuous one-dimensional addresses corresponding to a plurality of two-dimensional areas of different sizes to the image buffer memory and display memory. (2) The access control circuit is composed of two two-dimensional address generation circuits that have a circuit that generates a two-dimensional address corresponding to an arbitrary two-dimensional area and converts this into a continuous one-dimensional address for a plurality of areas. A document image processing device according to claim 1. (3) The document image processing apparatus according to claim 1, wherein the access control circuit includes a conversion table for converting a physical address and a logical address of the memory.