JP2945028B2 - Image processing designated area information calculation device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image processing designated area information calculation device of a digital copying machine.

2. Description of the Related Art In a copying machine, a technique of erasing or moving an image inside or outside a certain area in a document specified by a tablet or the like (that is, trimming or masking by an editor) has been used since the days of analog copying machines. It has already appeared and is widely used in various design applications.

Here, with the advent of digital copiers in recent years, it has become possible to provide an editor function at a lower price, and the accuracy of the designated area has been improved. Furthermore, the combination with the image processing capability of the digital copying machine has the potential to be used for a wider range of applications.

There are an eraser method and a counter method as an area designation method in such an editor for a digital copying machine.
The eraser system is also used in an analog copying machine, and performs masking and trimming by dropping electric charges on a photoreceptor using an array of LEDs. The counter method is a method of calculating a designated area for one designated area using one counter in each of the main scanning direction and the sub-scanning direction.

In any case, in the conventional method, as in the analog copier era, the area can be specified only in a rectangular shape such as a square or a concave linear in the main scanning and sub-scanning directions. There is no degree of freedom in the area shape. Also, the number of areas that can be specified is small.

Means for Solving the Problems At least the total number of read pixels for two lines in the main scanning direction
Area information storage means having a capacity to store 1/4 of image processing designated area information, two-stage parallel connected shift registers for alternately outputting image processing designated area information to the image processing unit, and outputs of these shift registers A selector for switching, a direct memory access controller for alternately transferring image processing designated area information from the area information storage means to these shift registers at a high speed, and the image processing designated area information stored in the area information storage means. A CPU for controlling the direct memory access controller so as to calculate an image processing area to be copied for each main scanning line and to transfer the area signal stored in the area information storage means to the shift register alternately. did.

Action CP for calculating image processing area for each main scanning line at high speed based on designated area information stored in area information storage means
U and a direct memory access controller that transfers the area data, which is the calculation result stored in the area information storage means, to the shift register at high speed, use the bus efficiently, and have a simple architecture, small capacity, and low cost. With this memory configuration, it is possible to specify an area of an arbitrary shape.

Embodiment An embodiment of the present invention will be described with reference to the drawings.

First, an outline of an image processing system in a digital copying machine to which the present invention is applied will be described with reference to a block diagram of FIG. Reference numeral 1 denotes an image processing unit IPU which processes image data read from a document. 2 is a scanner controller, which controls a scanner servomotor and an exposure fluorescent lamp,
The processing command is written into the IPU1. A main controller 3 controls the main motor and the like. Reference numeral 4 denotes an operation unit for inputting and outputting basic operations for copying. Reference numeral 5 denotes a tablet for inputting an area. Reference numeral 6 denotes a designated area calculation device (area calculation unit) ACU having a characteristic configuration of the present embodiment, which calculates a designated area and generates an area signal synchronized with the processing of the IPU1.

The outline of the flow of the area designation information in such a configuration will be described. First, an original is placed on the tablet 5, and the area to be processed is designated with a stylus pen. In response to this designation, the tablet 5 changes the marked position to XY
The data is converted into coordinate data and sent to the operation unit 4 by serial communication.
At this time, if the X and Y coordinate data from the tablet 5 is valid, the operation unit 4 returns a signal to the tablet 5 such as sounding a buzzer. The valid X, Y coordinate data is sent from the operation unit 4 to the ACU 6 via the main controller 3 and the scanner controller 2, and is temporarily stored in the ACU 6. All X and Y coordinate data for defining the specified area are A
When sent to the CU 6 (when the operator finishes specifying all the areas), the operator specifies what kind of processing is to be performed in (or out of) the specified areas in the future. This command is sent from the operation unit 4 to the scanner controller 2 via the main controller 3, and a CPU (not shown) in the scanner controller 2 codes this command and writes it into the IPU1.

Thereafter, the operation shifts to a normal copy operation. First, the image data read by the image reading unit 7 is taken into the IPU 1 in a state of a digital signal. As shown in FIG. 3, the image data undergoes shading correction, MTF correction, and the like by the correction unit 8 in the IPU 1, and undergoes necessary scaling processing in the main scanning direction by the scaling unit 9 (in the sub-scanning direction). Magnification depends on scanning speed). Thereafter, the character section 10, the photograph section 11, the hollow section 12, and the reversing section 13 perform the character mode processing, the photo mode processing, the hollow processing, and the reversing processing in parallel, respectively.
That is, all the processes are performed simultaneously, not limited to the processes actually requested. Image data that has undergone each process is a white data part
A selector provided at the output stage of IPU1 with 14 white data
15 selects only those that have actually received the requested processing. A region signal from the ACU 6 described later is gated by this select signal.

Here, for example, as shown in FIG. 4, an area indicated by hatching in the document 16 is an image processing designated area 17, the inside of the designated area 17 is a photograph mode, and the outside of the designated area 17 is white (that is, the designated area). Let us consider a case where a mode is set such that only the images in 17 are taken out in the photo mode). FIG. 4 shows a state when data is selected for the nth main scanning line. Only the part where the area signal from ACU 6 is active (within the specified area 17),
Shows that data in the data that has been uniformly subjected to the photo mode processing is selected, and the white data from the white data section 14 is selected in other portions. As a result, as a whole, an original having a photographic image as shown in FIG.
As shown in FIG. 3B, when the user designates the five points A to E on the tablet 5 with the stylus pen, the ACU 6 calculates the designated area 17 of an arbitrary shape surrounded by these designated coordinates. When stored and a copy operation is performed, a copy 18 subjected to the photograph mode processing in which only the image in the designated area 17 is extracted is obtained as shown in FIG.

In the IPU 1, a marker detecting section 19 is also provided for use in conjunction with the area specification by the marker pen. It is configured to be.

FIG. 1 shows the configuration of the ACU 6 which is a feature of this embodiment. First, the X and Y coordinate data from the tablet 5 is taken in via the serial communication driver & receiver 21.
A CPU 22 is provided. The CPU 22 calculates an image processing area and controls a DMAC described later. A static RAM (SRAM) 23 as area information storage means is connected to the CPU 22 via a 16-bit data bus and address bus. This SRAM23 is X, Y specified by tablet 5.
It stores coordinate data and data for obtaining an area signal. In this embodiment, a data having a capacity of 1 k × 16 bits is used. Further, two-stage parallel 16-bit shift registers 24 and 25 for converting the data in the SRAM 23 from 16-bit parallel data to serial data and outputting the converted data are provided. Further, a direct memory access controller DMAC 26 for alternately executing data transfer from the SRAM 23 to the shift registers 24 and 25 at a high speed is provided.
The DMAC 26 is connected to the CPU 22 by a HACK line and an HREQ line, and is also connected to the 16-bit data bus and address bus. The ROM 27 containing the system program is also connected to the same 16-bit data line and address line. Furthermore, this
A signal DMAREQ (DMA
Request) is provided. A selector 29 for alternately selecting the output is provided on the output side of the two shift registers 24 and 25, and is configured to output the output to a latch 30 for synchronizing with the area signal. Further, similar to the DMAREQ generator 28,
A sequence controller 31 that controls the operation timing of each unit based on the synchronization signals PMSYNC and CLK is provided.

In such a configuration, X, Y from the tablet 5 side
The coordinate data is input to the CPU 22 by serial communication. At this time, in this embodiment, the serial data is
Input to U22, but if the CPU does not have a serial port, the serial communication controller SC
What is necessary is just to hold C on the data bus of CPU. Upon receiving the X and Y coordinate data, the CPU 22 stores the data in the SRAM 23. When all the area coordinate data is received and stored in the SRAM 23, the CPU 22 performs an area calculation for the first main scanning line, and writes “1” to an address corresponding to the area in the SRAM 23 (for example, the fourth area). In FIG. 5 and FIG. 5, "0" is written in an address corresponding to an area outside the area.

When the copy operation starts, first, the DMAC 26
Causes the first shift register 24 to load the first word (16 bits) of the area signal in the SRAM 23. Then, this data is converted into a serial signal in synchronization with the image data, and output via the selector 29. This shift register
While the 24 is serially outputting, the DMAC 26 loads the next word of the area signal into the other shift register 25. After the previous shift register 24 finishes outputting 16 bits, serial data is subsequently output from the shift register 25 side. During this time, the next one word is loaded into the shift register 24 side. By repeating such a transfer operation, the area signal is output without interruption.

By the way, the capacity of the SRAM 23 in the present embodiment takes into account the capacity to store the image processing designation area information with a bit number of about 1/4 of the total read pixel number for two lines in the main scanning direction. . For example, an apparatus having a reading accuracy of 400 dpi (400 pixels per inch) in the main scanning direction at the same magnification (100% copy) in the main scanning direction means 297 mm in the main scanning direction. (A
(3 width size), (297 / 25.4) × 400 = 4677 is the number of pixels to be read for one line in the main scanning. Therefore, if it is 1/4 of two lines, it means a memory having a capacity of 4677 × 2 × (1/4) = 2339 bits. 1/4 is related to the accuracy of the area designation. When the area designation bitmap (memory) has a quarter of the reading accuracy of 400 dpi in the main scanning direction, the area designation accuracy is 0.25 mm. This means that the accuracy of the tablet 5, which is an area designation input device, is currently about ± 0.5 mm to ± 1.0 mm.
mm, and is determined as one appropriate value when considering an image editing request or the like to the digital copying machine. Instead of 1/4, 1/2 will give 0.125mm accuracy, and 1/8 will give 0.5mm accuracy.

Also, in the present invention, the reason why two main scanning lines are taken into consideration is that the CPU 22 specializes in outputting a region signal for one line while the CPU 22 performs the region calculation for the other line. It is to make it.

By the way, in the present embodiment, the shift registers 24, 2
As described above, the shift clock of 5 uses the image processing clock of the IPU1 in order to make the accuracy of area specification ± 0.25 mm as described above.
The frequency is reduced to 1/4. That is, the image data is processed in the main scanning direction in the order of the pixels 1, 2, 3,..., But the area signal must be processed with a clock that is frequency-divided by 1/4 while synchronizing with the pixel signal. . Therefore, as shown in FIG. 6, a 1/4 frequency divider 32 for dividing the pixel clock CLK by 1/4 is provided in the sequence controller 31, and the frequency-divided clock is supplied to the shift registers 24 and 25. Input as clock. Therefore, the image processing clock is set to, for example, 10
Assuming MHz, the shift clock is 2.5 MHz, and the time required to output all the image area signals of 1 word = 16 bits is (1 / 2.5 MHz) × 16 = 6.4 μsec. here,
The DMA cycle for data transfer from the SRAM 23 to the shift register 24 or 25 is performed during this time. . Then, in the remaining time, the CPU 22 calculates the area of the next main scanning line and executes S.
The area signal can be written in the RAM 23.

In the sequence controller 31, the 1/16 frequency divider 33 is a timing clock CLKINT for performing parallel-serial conversion on the 16-bit data of the shift registers 24 and 25.
Is to be generated. 34 is a latch.

FIG. 7 shows an example of an address map in the case where the SRAM 23 has a 2 kbyte configuration. That, 400 _H to 600 addresses _H is from the tablet 5 X, assigned to store the Y coordinate data, 0
00 addresses _H to 100 _H is assigned to store the odd-numbered lines in the region signal in the main scan lines that are calculated by the CPU 22, 20
0 address of _H to 300 _H are assigned to store the even-numbered lines of the area signal in the main scan lines that are calculated by the CPU 22.

Also, the shift register in the configuration shown in FIGS.
FIG. 8 shows a timing chart of an example of the operation control of the 24 and 25 and the DMA cycle.

Effect of the Invention The present invention is configured as described above, so that a CPU that performs high-speed area calculation based on designated area information stored in the area information storage means, and an area signal that is a calculation result stored in the area information storage means Direct memory access controller that transfers data to the shift register at high speed, uses the bus efficiently, and stores a simple architecture and image processing designated area information of the total number of read pixels for at least two lines in the main scanning direction. With a small-capacity and low-cost memory configuration, it is possible to specify an arbitrary number of areas in an arbitrary shape.

[Brief description of the drawings]

1 is a block diagram, FIG. 2 is a block diagram showing an outline of the overall configuration, and FIG.
FIG. 4 is a block diagram showing an IPU configuration, FIG. 4 is a timing chart showing an example of image processing, FIG. 5 is an explanatory diagram showing an example of image processing, FIG. 6 is a block diagram showing a sequence controller configuration, and FIG. FIG. 8 is a timing chart. 22 ... CPU, 23 ... area information storage means, 24, 25 ... shift register, 26 ... direct memory access controller, 29 ... selector

Claims (1)

(57) [Claims] 1. An area information storage means having a capacity for storing image processing designated area information of a total number of read pixels of at least two lines in the main scanning direction, and alternately outputting the image processing designated area information to the image processing unit. A stage-parallel connected shift register, a selector for switching output of these shift registers, a direct memory access controller for alternately transferring image processing designated area information from the area information storage means to these shift registers at high speed, and Calculation of an image processing area to be copied for each main scanning line based on the image processing designated area information stored in the information storage means and area signals stored in the area information storage means are alternately transferred to the shift register. An image characterized by comprising a CPU that controls the direct memory access controller Management designated area information computing device.