JPH0612368A - High-definition image processor - Google Patents

Abstract

PURPOSE:To transfer a large amount of image data in the processor from a necessary part at a transfer source to a necessary part at a transfer destination by performing the transfer of data in a transfer area by a data bus and instruction transfer on a system bus independently on or in parallel to other instruction transfer. CONSTITUTION:For the data transfer, transfer parameters are set in registers 27 and 28 in data transfer control parts 23 on the source side and destination side and the transfer is started by using the system bus 20. A data transfer control part 23 which is actuated requests a right to use a data transfer bus 21 of a data transfer bus arbitration part 18, which arbitrates the request with other bus requests and releases the bus 21 to the data transfer control part which has top priority. The data transfer control part 23 which is given the right to use the bus transfers the data by using the data bus 21 while shaking hands with the data transfer control part at the transfer destination.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image processing and communication system, and more particularly to a high definition image processing apparatus for processing a high definition image and displaying it on a high definition monitor.

[0002]

2. Description of the Related Art The prior art will be described below. Conventionally, a display having a resolution of about 1280 pixels × 1024 lines has been generally used as a man-machine interface for displaying images such as computer graphics. This largely depends on the performance of the CRT, which is the basic component of the display. However, recently, there is an increasing demand for higher resolution image display in the fields of medical care, printing, aerospace, remote sensing of terrain and weather, and the like. In these fields, a resolution of 2048 pixels × 2048 lines or more is required as a man-machine interface. Such a high-definition image has a remarkably large amount of information contained in the image as compared with an image used in a conventional computer system. For example, taking image transfer, which is often used in conventional systems,
The transfer amount required to transfer an image having a resolution of 280 pixels × 1024 lines × 8 bits from the frame memory to the display memory is 1.2 Mbytes.

The bus configuration of a conventional image processing apparatus is, for example, a single bus configuration shown in FIG. In the figure, 41 to 43 are processing units, 51 to 53 are bus interface units, and 61 is a system bus (S bus). In the image processing apparatus, the processing unit is specifically a disk controller, a CRT controller, or an image processor unit.

This operation will be described. Processing unit U ₀
It is assumed that the 1.2-Mbyte image data is transferred from (in this case, a memory) 42 to a processing unit U _n-2 (in this case, an image processor unit) 43. As shown in the timing chart of FIG. 6B, the start T ₀
When the bus monopolization is permitted, the memory U ₀ executes the task to prepare the data and sends the data to the bus. By the way, the image used in this device, 2048 pixels x 2
The amount of data transfer required to perform the same transfer of an image having a resolution of 048 lines × 24 bits is 12 Mbytes, which is 10 times the 1.2 Mbytes of the conventional example. With the conventional configuration and operation shown in FIG. 6A, it takes a lot of time for transfer. If only one type of data to be transferred, for example, NTSC format image data, it is decided to assemble the image data.
Therefore, even when transferring a partial image in a certain screen frame, no special consideration is required for the transfer area. However, if HDTV and NTSC are mixed, or if the shape of the screen area changes from screen to screen, the transfer is performed for each small-scale line, or the shape of the transfer destination is changed before sending. Operation was required.

[0005]

Since the conventional image processing apparatus is configured as described above and is not configured to transfer a large amount of data, a large amount of image data of various types can be generated. There is a problem that it takes time to select and transfer the data of the target method in the mixed devices and the operation precision is bad.

The present invention has been made in order to solve the above problems, and it is possible to store a large amount of image data in the apparatus.
An object of the present invention is to obtain a high-definition image processing device that transfers at high speed from a required part of a transfer source to a predetermined part of a transfer destination.

[0007]

A high-definition image processing apparatus according to the present invention has a second start address and a second start address in a first logical area indicated by a first start address and a first vertical and horizontal size. A source-side processing unit that continuously transfers data in the transfer area indicated by the vertical and horizontal sizes, a third start address, a fourth start address in the second logical area indicated by the third vertical and horizontal sizes, and a fourth vertical and horizontal directions. Destination-side processing unit that continuously writes data in the transfer area to a storage area indicated by size, system bus that transfers the source-side parameter, destination-side parameter and instruction, and transfer-data in the transfer area The data transfer of the data in the transfer area is performed by the data bus independently of the instruction transfer on the system bus or by another command. It was to be performed in parallel with the transfer.

[0008]

In the high-definition image processing apparatus according to the present invention, the data in the necessary area of the transfer source is continuously read,
Data is continuously transferred at high speed via the data bus, and continuous writing is performed in a predetermined storage area at the transfer destination.

[0009]

EXAMPLES Examples of the present invention will be shown below. As a device suitable for applying the present invention, there is a workstation that handles high-definition images. Further, as another application, there is an apparatus for transferring data handled inside the image display terminal. Further, the present invention can be applied to an apparatus that holds a large amount of data inside the apparatus and frequently transfers data between internal memories even if the medium to be handled is not a high-definition image. . Therefore, the application of the present invention is not limited to a specific device, and the connected functional unit may be any unit that transfers a large amount of data.

FIG. 1 is a diagram showing the construction of a workstation which is an embodiment of the present invention. In the figure, a display interface unit 10, a frame memory unit 11, a transmission control unit 12, a disk interface unit 13, and a video input interface unit 1
Eight functional units including a scanner interface unit 15, an image processor unit 16, and a CPU unit 17 are connected to the system bus 20 and the data transfer bus 21. Further, the data transfer bus control unit 18 is connected to the data transfer bus. Further, a high-definition monitor 2 is connected to the display interface unit, and a disk 4 is connected to the storage media interface unit via, for example, SCSI. A device for generating a video signal such as HDTV or NTSC is connected to the video input interface unit, the scanner 5 is connected to the scanner interface unit, and the keyboard 6 is connected to the CPU unit. Furthermore, this device is connected to a LAN (Ethernet) 3 through a transmission control unit. The structural feature is that the system bus and the data transfer bus are separate.

Next, the internal structure of each unit will be described. FIG. 2 is an internal configuration diagram common to each functional unit. A data cache memory 22, which is an element for high-speed processing, is provided in each of the units 10 to 16, and the data cache memory is instructed by the data transfer control unit 23 to connect the internal processing unit 24 of each functional unit to the buses 20 and 21. Has become a buffer. The data cache memory has a capacity required to perform a certain unit of processing in each functional unit. For example, in a graphic processor unit, one high-definition image frame serves as a processing unit, and thus has a capacity of at least 12 Mbytes. . In order to perform processing in each processing unit, data to be processed is transferred to the data cache memory in advance using the data transfer bus 21 or the system bus 20. The structure of the data transfer control unit is shown in FIG. When the user tries to cause the functional module to perform some processing, or when transferring a small amount of data, the other functional module is accessed via the system bus. In this case, the data cache memory is not always necessary.

Next, the operation of the processing unit, which is an important component of the present invention, will be described. This processing unit is particularly characterized in that the data in the designated transfer area of the designated logical area is converted into a continuous data string and loaded into the cache memory. Further, the processing unit at the transfer destination is characterized in that the data string continuously transferred to the receiving side cache memory is converted into a designated storage area of the receiving designated logical area and written. Although the bus structure described above can be realized by the VME bus configuration which is a standard bus for microprocessors, it is not used in the standard specifications of the VME bus but is operated in parallel as described later to separate addresses and data. Then use the bus.

Next, a two-dimensional transfer for transferring a large amount of two-dimensionally arranged data, which is frequently used in the present invention, to another two-dimensionally arranged area will be described. The parameters of the two-dimensional transfer are shown in FIG. In data transfer, the unit on the read side is called the source and the unit on the write side is called the destination. When transferring the two-dimensional transfer storage area 102 on the logical plane 100 defined in the memory on the source side to the two-dimensional area 103 on the destination side on the logical plane 101 on the destination side, the following parameters are required. It is a kind. In the figure, S0 is the source side logical plane start address 31, H
0 is the source side logical plane horizontal size 32, and V0 is the source side logical plane vertical size 33. In addition, s0 is the source side transfer start relative address 34, and h is the transfer lateral size 3
5 and v are the transfer vertical size 36. on the other hand. S1 is the destination side logical plane start address 37, H1
Is the destination side logical plane horizontal size 38,
V1 is the destination side logical plane vertical size 3
In step 9, s1 is the transfer start relative address 40 on the destination side.

In order to perform data transfer, these transfer parameters are set in the registers 26, 27, 28 inside the data transfer control units on the source and destination sides, and the S bus is used for activation. In this embodiment, the CPU unit sets these parameters and activates them via the VME bus. The activated data transfer control unit requests the data transfer bus arbitration unit 18 for the right to use the data transfer bus, and the data transfer bus arbitration unit arbitrates with other bus requests to transfer the highest priority data. Release the bus to the control. The data transfer control unit to which the bus use right is given executes data transfer using the T bus while performing a handshake with the data transfer control unit of the transfer destination. When the data transfer is completed, the CPU is routed through the system bus.
The end of the data transfer is notified by an interrupt.

FIG. 4A shows a bus configuration in comparison with the conventional example of this embodiment, and FIG. 4B shows a timing chart of the operation of each bus and the processing unit. FIG. 5 is a diagram showing the relationship between the control code transfer and the data transfer described above, and the relationship between the bus and time (time elapses from top to bottom). It is already known that the technique of simultaneously transferring different information using a plurality of buses is already known. However, as shown in FIG. 4 (b) and FIG. The data itself is at a high speed within the allowable processing speed of the processing units of the transfer source and the transfer destination, and it is particularly effective to transfer a high-definition image that a large amount of data is continuously sent on another parallel data bus. It is possible to transfer at a higher speed than the restriction speed of the VME standard.

Further, as shown in FIG. 4B, when the transfer source processing unit (for example, U ₀ ) receives a source side transfer parameter setting instruction from the CPU unit, the data in the transfer area of the specified screen logical area is received. And the data string is written in the cache memory C ₀ of the transfer source as described above. At the transfer destination, the destination side transfer parameter setting instruction is received, then the transfer destination cache memory C ₂ receives the data via the data bus, and when the transfer is completed, the destination side processing unit U ₂ receives the instruction at T _2. Special processing on the receiving side begins. When the receiving side is, for example, a display interface unit, the transfer data in the cache memory C ₂ is exclusively converted and written in the storage area of the screen shown by the parameter in FIG. 3B. This is also a known technology in information processing, so details will be omitted. However, by entrusting each processing unit with dedicated processing and enabling dedicated processing in parallel with transfer, particularly high-definition images can be obtained. Effective for transfer.

It should be noted that a cache memory is used to speed up the processing, and in a unit having a 2-input 2-output interface such as a transmission control unit, the buffer is divided into two and used as an input buffer and an output buffer.
Alternately switching and operating continuously is also effective for speeding up the entire system.

Next, an example of the operation of the entire system having these mechanisms will be described. First, when the image data is loaded from the disk 4 to the frame memory unit 11, the image data is managed under the control of the CPU unit 17, and the image data for the two surfaces provided in the disk interface unit 13 is transmitted from the disk via SCSI. It is loaded into one of the data caches. The unit of loading once is within a range that does not exceed the size of the image to be transferred, and the CPU unit is set so as not to exceed the capacity of one data cache memory of this unit. However, the load unit should be set as large as possible considering the subsequent processing.

Thereafter, the CPU unit uses the disk interface unit as a master and the frame memory unit as a slave, sets transfer parameters in the data transfer control units 23 of both units, and activates them. Once activated, C until the set number of transfer pixels is reached
Communication is continued only between the master and slave units that execute data transfer without the intervention of the PU unit. The activated master requests the bus right of the data transfer bus to the data transfer bus arbitration unit 18 via the data transfer bus 21. The data transfer bus arbitration unit arbitrates the same request from other units,
The right to use the data transfer bus is given to the master with the highest priority by time division. The master to which the bus use right is given sends out the slave unit ID to the data transfer bus. Each unit compares this slave ID with its own unique ID, and if they match, recognizes that it is a slave and performs the slave side operation. When the data transfer is complete,
The master notifies the CPU of the end of the data transfer via an interrupt to the CPU via the system bus. By repeating this, data transfer is sequentially performed.

[0020]

As described above, according to the present invention, the source side processing unit for continuously transferring the data in the designated transfer area, the destination side processing unit for continuously writing the data in the designated storage area, the parameter and Since it has a system bus for transferring instructions and a data bus for transferring data in parallel with the instructions on the system bus,
This has the effect of enabling high-speed transfer from the designated transfer area to the designated storage area.

[Brief description of drawings]

FIG. 1 is a configuration diagram of a high-definition image processing apparatus according to an embodiment of the present invention.

FIG. 2 is an internal configuration diagram common to each functional module of the high definition image processing apparatus according to the embodiment of the present invention.

FIG. 3 is a schematic diagram showing parameters of two-dimensional data transfer of the high-definition image processing apparatus according to the embodiment of the present invention.

FIG. 4 is a bus configuration diagram and a timing chart diagram of the present invention.

FIG. 5 is a diagram illustrating a relationship of control code data transfer.

FIG. 6 is a diagram showing a bus configuration and timing of a conventional image processing apparatus.

[Explanation of symbols]

1 high-definition image processing device 2 high-definition monitor 3 LAN line 4 disk 5 scanner 6 keyboard 10 display interface unit 11 frame memory unit 12 transmission control unit 13 disk interface unit 14 video input interface unit 15 scanner interface unit 16 image processor unit 17 CPU Unit 18 Data transfer bus arbitration unit 20 System bus 21 Data transfer bus 22 Data cache memory 23 Data transfer control unit 24 Processing unit 25 Data transfer bus controller 26 Data transfer number counter 27 Image data transfer control register 28 Image data attribute register 29 Memory Two-dimensional address generator 30 Memory controller 31 S0: Source side logical plane top address Response 32 H0: Source side logical plane horizontal size 33 V0: Source side logical plane vertical size 34 s0: Source side transfer destination start relative address 35 h: Transfer horizontal size 36 v: Transfer vertical size 37 S1: Destination side logical plane start Address 38 H1: Destination side logical plane horizontal size 39 V1: Destination side logical plane vertical size 40 s1: Destination side transfer start relative address 41 to 43 Bus interface unit 51 to 53 Processing unit 62 T bus 63 S bus 72, 73 cash memory

Claims (1)

[Claims] 1. A source for continuously transferring data in a transfer area indicated by a second start address and a second vertical / horizontal size in a first logical area indicated by a first start address and a first vertical / horizontal size. The side processing unit, the second start address and the second vertical and horizontal sizes indicated by the third
Destination side processing unit that continuously writes the data of the transfer area to the storage area indicated by the fourth start address and the fourth vertical and horizontal size in the logical area of the above, the source side parameter, and the destination side parameter. And a system bus for transferring instructions, and a data bus for transferring data in the transfer area, wherein the transfer of the data in the transfer area by the data bus is
A high-definition image processing device that performs an instruction transfer on the system bus independently or in parallel with another instruction transfer.