JPH03233780A - Bus access system - Google Patents

Abstract

PURPOSE:To execute a high speed display which is scarcely influenced by the operation performance of a system bus in the case a screen memory of a main body side is used directly by loading a processor on an option board and operating a software being separated from the main body side. CONSTITUTION:An option board 15 is provided with the same local screen memory 17 as a screen memory 12, and an FIFO buffer memory 16 for reading out successively an address for accessing the screen memory 12 and sending it out to a system bus 9, and also, reading out successively data written in the screen memory 12 and sending it out to the system bus 9. In such a way, in the case a processor 2 writes data in the screen memory 12, the data is written in the local screen memory 17, and also, in the FIFO buffer memory 16, the address and the data of the screen memory 12 are written. In such a way, whenever the right of using of the system bus 9 is given from a bus arbitrating circuit 8, the data is written in the screen memory 12, and in the case of reading out the data, it is read out of the local screen memory 17. In such a way, the screen display speed is improved.

Description

[Detailed Description of the Invention] [Summary] This invention relates to a bus access method that makes it possible to improve the display speed when a processor on an option board writes data to the screen memory on the main unit and displays it. the system processor that accesses the screen memory and the system processor that accesses the screen memory.
In a device equipped with an option board equipped with a processor and operated by proprietary software, a system bus that connects these boards, and a bus arbitration circuit that grants permission to use the system bus in response to a request from the option board to use the system bus. , a local screen memory that is the same as the screen memory on the option board, and a FIFO buffer that sequentially reads addresses for accessing the screen memory and sends them to the system bus, and sequentially reads data to be written to the screen memory and sends them to the system bus. Set up memory,
When the processor writes data to the screen memory, it writes the data to the local screen memory and also writes the address and data of the screen memory to the FIFO buffer memory. Data is written to the screen memory every time the right to use the bus is granted, and when data is read from the screen memory, the data is read from the local screen memory.

[Industrial application field]

The present invention relates to a computer that operates with an option board that is equipped with a processor and operates using proprietary software, and in particular, the processor on the option board stores data in a screen memory that stores data for display provided in the computer. The present invention relates to a bus access method that makes it possible to improve the display speed when writing and displaying.

In workstations, personal computers, etc., a system processor, main memory, screen memory, etc. are connected via a system bus, and the data written to this screen memory is displayed on the display section. Some systems are configured so that option boards operated by software are connected to a system bus, and each job can be performed by different software.

The processor of the option board connected to the system bus of a workstation or personal computer configured in this way writes data to the screen memory provided on the main body side via this system bus, and displays the data on the display section of the main body side. The data written in this screen memory is displayed, and the display speed needs to be fast.

[Conventional technology]

FIG. 2 is a block diagram illustrating an example of the prior art.

The system processor IO on the main body side accesses the main memory 11 or the screen memory 12 via the system bus 9 to execute a job. The data written in the screen memory 12 is then read out by the display control circuit 13, and the data written in the screen memory 12 is read out by the display control circuit 13 and
will be displayed.

Option board 1 is connected to system bus 9 as an option. When the processor 2 of the option board 1 needs to access the screen memory 12, it sends the address of the screen memory 12 to the bus 7, and when writing data, the write data is sent to the bus 7 at the same time.
Send to.

When the decoder 3 decodes the address in the screen memory 12, it activates the bus request circuit 4. Therefore, in order to obtain the right to use the system bus 9, the bus request circuit 4 requests the bus arbitration circuit 8 for permission to use the system bus 9.

Bus arbitration circuit 8 requested permission to use system bus 9
acquires the right to use the system bus 9 of the option board 1 using a known system bus acquisition procedure.
A signal is sent to the bus request circuit 4 to permit use of the system bus 9.

The bus request circuit 4 that has received the permission signal to use the system bus 9 allows the address conversion circuit 5 to send the address, so the address conversion circuit 5 transfers the address of the screen memory 12 sent by the processor 2 to the main body The address is converted into an address and sent to the system bus 9.

In addition, since the bus request circuit 4 opens the gate of the gate circuit 6, in the case of writing, the gate circuit 6 requires that the processor 2
In the case of reading, the gate circuit 6 transfers the data read from the screen memory 12 to the system bus 9 to the processor 2 according to the address sent by the address conversion circuit 5.

Therefore, when writing, the data sent from the gate circuit 6 is written to the screen memory 12 according to the address sent from the address conversion circuit 5, and when reading, the data is written from the screen memory 12 according to the address sent from the address conversion circuit 5. The read data is transferred to the processor 2 via the gate circuit 6.

Further, the data written by the processor 2 to the screen memory 12 is displayed on the display section 14 in the same manner as described above.

[Problem to be solved by the invention]

As mentioned above, conventionally the processor 2 of the option board 1
accesses the screen memory 12, the screen memory 12
Each time an address is sent, the right to use the system bus 9 must be acquired through arbitration by the bus arbitration circuit 8.
Screen memory 12 cannot be accessed.

Therefore, the access efficiency of the processor 2 to the screen memory 12 depends on how quickly the right to use the system bus 9 can be acquired after the processor 2 sends out the address of the screen memory 12, and therefore depends on the performance of the system bus 9. Therefore, there is a problem that the screen display speed becomes slow.

In particular, when scrolling a graphic image, the processor 2 transfers data from an area of the screen memory 12 to the screen memory 12.
Because the system is used to continuously transfer data to different areas, the right to use the system bus 9 must be acquired frequently, and the operating performance of the system bus 9 directly affects the screen display speed. There is.

In view of these problems, the present invention aims to reduce the influence of the operating performance of the system bus 9 and improve the screen display speed.

[Means to solve the problem]

As shown in FIG.
, a system processor 10 that accesses the screen memory 12, an option board 15 equipped with the processor 2 and operated by unique software, the screen memory 12, the system processor IO, and the option board 15.
system bus 9 connecting the system bus 9 and the option board 1
In the device, the bus arbitration circuit 8 acquires the right to use the system bus 9 and grants permission to use the system bus 9 in response to a request to use the system bus from the option board 15. Addresses for accessing the local screen memory I7 (having the same memory capacity and number of branes) and the screen memory 12 are sequentially read out in the order in which they were stored and sent to the system bus 9, and data to be written to the screen memory 12. A FIFO buffer memory 16 is provided to sequentially read data in the order in which it was stored and send it to the system bus 9. When the processor 2 of the option board 15 writes data to the screen memory 12, the local screen memory 17 stores data. By sequentially writing data and sequentially writing the address and data to be sent to the screen memory 12 into the FIFO buffer memory 16, the FIFO buffer memory 16 is granted the right to use the system bus by the bus arbitration circuit 8. Each time the FI
Based on the addresses successively output from the FO buffer memory I6, the data read from the FIFO buffer memory 16 is written to the screen memory 12 via the system bus 9, and the processor 2 reads the data from the screen memory 12. In this case, instead of accessing the screen memory 12,
This is accomplished by reading data from the local screen memory 17.

[Effect]

With the above configuration, when reading data from the screen memory 12, the local screen memory 17, which stores the same data as this screen memory 12, is used, and the screen memory 12 is not accessed, so the system bus 9 Since there is no need to acquire the right to use the system bus 9, the operating performance of the system bus 9 is not affected.

Further, when writing data to the screen memory I2, the processor 2 writes the address and data to the FIFO buffer memory 16, and then writes the FIFO buffer memory 16 to write data to the screen memory 12.
While the FO buffer memory 16 acquires the right to use the system bus 9 and writes data, the processor 2
can perform other processing.

Therefore, when the processor 2 successively transfers data from one area of the screen memory 12 to another area of the screen memory 12, such as when scrolling a graph ink image, the FIF
While the O buffer memory 16 is writing data to the screen memory 12, the processor 2 can read data from the local screen memory I7, and while the processor 2 is reading the next data. ,F
Once acquisition of the system bus 9 and data writing by the lFO buffer memory 16 are completed, there will be no influence on the operating performance of the system bus 9, but since the operating performance of the system bus 9 is actually slow, it will be affected by the operating performance of the system bus 9. That will happen.

However, since at least the read cycle is completely unaffected by the operating performance of the system bus 9, it is possible to obtain a performance improvement of approximately twice that of the conventional system.

〔Example〕

FIG. 1 is a block diagram of a circuit illustrating the principle and one embodiment of the present invention.

The same reference numerals as in FIG. 2 indicate the same functions. Option board 15 is connected to system bus 9 as an option. When writing data to the screen memory 12, the processor 2 of the option board I5 sends a write signal to the local screen memory 17, sends the address of the screen memory 12 to the bus 7, and sends the write data to the bus 7. Send.

When the decoder 8 decodes the address in the screen memory 12, it sends a storage signal to the FIFO buffer memory 16. Therefore, the FIFO buffer memory 16 stores the address that the address conversion circuit 5 converts from the screen memory 12 address sent by the processor 2 to an address used by the main body, and also stores the data sent to the bus 7.

The FIFO buffer memory 16 has, for example, a two-stage configuration, and when addresses and data are stored in one or more stages, the bus request circuit 4 is activated. Therefore, in order to obtain the right to use the system bus 9, the bus request circuit 4 requests the bus arbitration circuit 8 for permission to use the system bus 9.

Bus arbitration circuit 8 requested permission to use system bus 9
When acquiring the right to use the system bus 9 of the option board 15 through a known system bus acquisition procedure, it sends a signal to the bus request circuit 4 to permit use of the system bus 9.

The bus request circuit 4 that has received the system bus 9 use permission signal allows the FIFO buffer memory 16 to send the address and data, so the FIFO buffer memory 16 uses the address stored in the first stage of the system bus 9. Send the data and move the address and data stored in the second stage to the first stage.

Therefore, when the processor 2 writes, data is written to the local screen memory 17 at the address sent by the processor 2, and data is written to the screen memory 12 at the address sent from the FIFO buffer memory 16 to the system bus 9. is written.

When the FIFO buffer memory 16 finishes storing the data sent out by the processor 2, it notifies the processor 2 that data writing is complete, and when the local screen memory 17 finishes storing the data sent out from the processor 2, it notifies the processor 2. Notifies completion of data writing. Therefore, when the processor 2 receives both write completion notifications, it sends out the next address and data, but the decoder 18 uses the FIFO
When the buffer memory 16 still stores data for two stages, the processor 2 instructs the processor 2 to hold the next address and data, so the processor 2 waits for free space in the FIFO buffer memory 16. wait.

When processor 2 reads data, decoder 1
8 and the local screen memory 17, an address is sent to the local screen memory 17, and the required data is read out. At this time, the decoder 18 does not send a storage signal to the FIFO bumper memory 16 because it is a read signal.

In this embodiment, the screen memory 12 is described as being one plane, but the same applies when multiple planes are used.

〔Effect of the invention〕

As explained above, the present invention provides a system for installing a processor on an option board such as a workstation or personal computer, running software separate from the main unit, and directly using the main unit's screen memory. It is possible to perform high-speed display that is less affected by the operating performance of the bus.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a circuit illustrating the principle and one embodiment of the present invention, and FIG. 2 is a block diagram illustrating an example of a conventional technique. In the figure, 1.15 is an option board, 2 is a processor, 3.1
8 is a decoder, 4 is a bus request circuit, 5 is an address conversion circuit, 6 is a gate circuit, 7 is a bus,
8 is a bus arbitration circuit, 9 is a system bus, 10 is a system processor, 11 is a main memory, 12 is a screen memory, 13 is a display control circuit, 14 is a display section, 16 is a FIFO buffer memory, and 17 is a local screen memory. .

Claims (1)

[Scope of Claims] A screen memory that stores at least data to be displayed on a display section, a system processor that accesses the screen memory, an option board that is equipped with the processor and operates by unique software, and the screen memory and the system. An apparatus comprising a system bus that connects a processor and an option board, and a bus arbitration circuit that acquires the right to use the system bus and grants permission to use the system bus in response to a request for use of the system bus from the option board. The option board has a local screen memory that is the same as the screen memory, and addresses for accessing the screen memory are sequentially read out in the order in which they are stored and sent to the system bus, and data to be written to the screen memory is stored. A FIFO buffer memory is provided that is sequentially read out and sent to the system bus, and when the processor of the option board writes data to the screen memory, it sequentially writes the data to the local screen memory and also writes the data to the FIFO buffer memory. By sequentially writing into memory the address and data to be sent to the screen memory, the address read from the FIFO buffer memory each time the FIFO buffer memory is given the right to use the system bus from the bus arbitration circuit. Based on this, data read from the FIFO buffer memory is written to the screen memory via the system bus, and when the processor reads data from the screen memory, instead of accessing the screen memory, the local A bus access method characterized by reading data from screen memory.