JPS62212826A - Screen controller in multi-job system - Google Patents

Screen controller in multi-job system

Info

Publication number
JPS62212826A
JPS62212826A JP61056497A JP5649786A JPS62212826A JP S62212826 A JPS62212826 A JP S62212826A JP 61056497 A JP61056497 A JP 61056497A JP 5649786 A JP5649786 A JP 5649786A JP S62212826 A JPS62212826 A JP S62212826A
Authority
JP
Japan
Prior art keywords
data
address
holding
circuit
mpu
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP61056497A
Other languages
Japanese (ja)
Inventor
Shinji Nakada
Original Assignee
Casio Comput Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Casio Comput Co Ltd filed Critical Casio Comput Co Ltd
Priority to JP61056497A priority Critical patent/JPS62212826A/en
Publication of JPS62212826A publication Critical patent/JPS62212826A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE: To more efficiently and economically execute the screen control of each job by holding an address and data generated at the inhibition of access to an arithmetic processing means by a holding means and writing data in a logical screen storing means at the time of unconditional interruption processing.
CONSTITUTION: When a picture memory access arbitrating circuit 24 makes a memory access permission signal 25 inactive, data access to a physical picture RAM 15 is inhibited and a hold control signal is activated, so that an MPU holding address holding circuit 18 temporarily holds an address on an address bus 12. When the access request is a data writing request, a hold control signal 28 is activated and an MPU data holding circuit 19 temporarily holds data on a data bus 13. The address held by the circuit 18 and the data held by the circuit 19 are read out and inputted to an MPU 11 through the data bus 13 and an operating system writes data in a logical screen RAM 23 in stead of the job executed at that time.
COPYRIGHT: (C)1987,JPO&Japio
JP61056497A 1986-03-14 1986-03-14 Screen controller in multi-job system Pending JPS62212826A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP61056497A JPS62212826A (en) 1986-03-14 1986-03-14 Screen controller in multi-job system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP61056497A JPS62212826A (en) 1986-03-14 1986-03-14 Screen controller in multi-job system

Publications (1)

Publication Number Publication Date
JPS62212826A true JPS62212826A (en) 1987-09-18

Family

ID=13028736

Family Applications (1)

Application Number Title Priority Date Filing Date
JP61056497A Pending JPS62212826A (en) 1986-03-14 1986-03-14 Screen controller in multi-job system

Country Status (1)

Country Link
JP (1) JPS62212826A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01232487A (en) * 1988-03-14 1989-09-18 Hitachi Ltd Graphic display system and method thereof
JPH0244419A (en) * 1988-06-22 1990-02-14 Bull Sa Method for generating interactive window displayable on display of information processing system and device for executing the method

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01232487A (en) * 1988-03-14 1989-09-18 Hitachi Ltd Graphic display system and method thereof
JPH0244419A (en) * 1988-06-22 1990-02-14 Bull Sa Method for generating interactive window displayable on display of information processing system and device for executing the method

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