JPS63197254A - Virtual memory controller - Google Patents

Abstract

PURPOSE:To restart an instruction without a malfunction after the page fault processing is finished by providing a means which compares the contents LA of a logic address register with the next page boundary address BA and detects that the conditions BA-N<=LA<BA are satisfied against a certain fixed natural number N. CONSTITUTION:The warnings can be issued against a 3-word access, a 4-word access, etc. In other words, it may be required to give a warning when the conditions BA-N<=LA<BA are satisfied with the logic address LA of a memory access, a page boundary BA and a prescribed natural number N (issuing the warning to an N-word access). Especially, the conditions equivalent to a state where bits n-11 are equal to 'all-1' when N=2<n>+1 (n: non-negative integer). Thus a warning signal 131 can be issued with a simple logic.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a computer that handles virtual memory, and particularly to a method suitable for simplifying instruction restart processing when a page fault occurs.

[Conventional technology]

Conventionally, methods for restarting instructions after completion of page fault processing in virtual memory computers have been described by I.E.E.
Micro June 1983 issue pages 28 to 32 (I
EEE MICROJune 1983 P2g-32
) is discussed in

According to the document, there are two methods for restarting instructions after page fault processing is completed: restart at the beginning and restart in the middle, which are described in detail. Here, first, page faults will be briefly explained, and then each restart method will be explained.

Virtual memory uses a small-capacity, high-speed main storage device and a large-capacity, slow-speed secondary storage device, and has a large-capacity, high-speed main storage device when viewed from the central processing unit (CPU). It is made to look like this.

This is realized by the following two properties of the computer. One is that access from the CPU to the storage device is limited to one storage unit at a time, and the other is the locality of the access, which means that this access is only made to a certain area of the storage area within a certain time. .

Therefore, in order to realize virtual memory, areas that are currently frequently accessed are stored in the main memory, and areas that cannot be placed on the main memory are placed on the secondary storage to achieve high-speed access. memory access becomes possible.

Here, a unit called a page is considered as an area arranged on the memory, and the area is managed on a page-by-page basis.

Now, when the CPU attempts to refer to data within a page on the secondary storage device, that area must be replaced with another page on the main storage device.

7. Since the location of each page changes over time, it is necessary to manage the location of each page and convert the addresses issued by the CPU to make them correspond to each other. Since this conversion is performed while the CPU is running, it is called dynamic address conversion.

The translated address is an address on main memory,
called a physical address. In contrast, the address issued by the CPU is called a logical address in the sense that it does not care about the actual location of the page. Generally, the logical address space is wider than the physical address space, so when performing address translation, there are cases where a page containing the desired data does not exist on the main memory. This state is called a page fault, and a series of processes that are performed to import this page into the main storage, which involves exchanging pages between the main storage and the secondary storage, are called page fault processing.

Page fault processing can be broadly divided into three parts.

The first is to save information destroyed by page fault processing to memory, and the second is to instruct the input/output controller to perform page replacement processing.
The third step is to import the saved data and restart the instruction.

Since a page fault occurs during memory access, that is, during instruction execution, the instruction must be executed without malfunction after page fault processing is completed. A method for this purpose is the instruction start restart method described below.

When a page fault occurs, save the minimum necessary information,
After the processing is completed, the same instruction is executed again from the beginning.

In this case, various information may be destroyed before a page fault occurs, and in that case, this method will malfunction. Therefore, for this method.

Before rewriting various information, dummy access is performed to check whether a page fault will occur. This ensures that a page fault does not occur when rewriting various information. This dummy access processing is called rehearsal processing.

When a page fault occurs, information related to the microprogram is also saved, and after processing is completed, execution is resumed from the middle of the instruction.

[Problem that the invention seeks to solve]

The above conventional technology does not take into consideration the following two points.

1. When performing rehearsal processing, a page fault will not occur due to dummy access at the start of instruction execution, so there will be no malfunctions caused by page faults afterwards (instruction start restart method) However, this method uses dummy access , the number of microprogram steps increases. Therefore, although it is effective for instructions with a large number of execution cycles, the overhead is large for instructions with a small number of execution cycles.

2. If a page fault occurs during instruction execution, the values of various registers at that point are retained, and after the page fault processing is completed, the system restarts from the middle of the instruction. This method prevents malfunctions because the information is saved. (Instruction mid-resume method) However, this method requires a lot of information to be saved, and the content to be saved also differs depending on the timing when a page fault occurs, so the overhead for information saving and recovery is large. The save information differs depending on whether the fault occurs before or after the internal state of the CPU changes. This overhead requires multiple page fault handling and increases microprogram capacity.

An object of the present invention is to realize instruction restart after completion of page fault processing without malfunction, without increasing the number of microsteps or the microprogram capacity.

[Means for solving problems]

The above object is achieved by having means for determining whether a memory access is likely to cause a page fault and issuing a warning.

In a preferred embodiment of the present invention, when receiving a warning, there is provided means for causing the CPU to perform dummy access before the CPU changes the state of the CP IJ or the contents of the memory. By providing the means in the memory access controller, the number of steps in the microprogram is not increased.

[Effect]

A page fault warning is issued when a memory access during instruction execution has a possibility of a page fault.

At this time, dummy access is preferably performed.

If there is no page fault as a result of the dummy access, the instruction continues.

If a page fault occurs as a result of dummy access, a series of processes for replacing the page 69 is performed. After the processing is completed, the instruction is restarted from the beginning, but since the CPU state and memory contents at the time of the start of the instruction are saved, it is possible to restart the instruction from the beginning without malfunction.

Moreover, since these processes are performed only when a warning is issued, performance degradation is minimized and, preferably, no increase in microprograms is required.

〔Example〕

An embodiment of the present invention will be described below with reference to FIGS. 1 to 4.

First, the terminology used in this computer system will be explained.

Word: For example, a data area address consisting of 1 word and 2 bytes is 1. Allocated consecutively for each word.

Block: For example, a unit of memory access consisting of 1 block and 2 words, and the start address of the block is an even number.Page: For example, an area of 4 words per page, and the smallest unit managed by a virtual memory system. be.

The storage device of this computer system is managed by a virtual storage method. That is, in FIG. 1, the register LARI stores the logical address for memory access.
The contents of II are converted through the dynamic address translation mechanism DAT123, and the address of the main memory MM102 is set in the register PAR112 for memory access.

At this time, if the data corresponding to the contents of the register LAR is not on the main memory MM102 but on the secondary storage device fiDK104, the memory management unit MMU122 issues a command, and under the control of the input/output control unit [10C103, for example, main memory MM1 in units of words.
02 and the page on the secondary storage [DK104]. This is called page fault processing.

It is not possible to know whether a page fault will occur until conversion is performed using the dynamic address translation mechanism DAT123.

At this time, the following inconvenience occurs. As shown in FIG. 2(a), the instruction word 201 and the address area 202 rewritten by the instruction overlap, and the address area 202 to be written is located at the page boundary 211.
When the command word 20 is used as shown in Figure 2(b),
Let us consider a case where the address area 204 to be read and the address area 205 to be written overlap with each other, and the write address area 205 straddles the page boundary 212.

In Figure 2, the right direction is the increasing direction of addresses (221)
, and the downward direction shows the passage of time (222).

Accesses to data areas that straddle page boundaries, such as 202 and 205, are divided into two block accesses (206a, 206b) and (206c, 206d) as shown in FIG. 2(C). This is because page boundaries always become block boundaries.

If the parts 206a and 206d in FIG. 2(C) are invalidated, the areas 206b and 206 that span the page will be
It becomes possible to write to c.

In the case of FIG. 2(a), the instruction word 20 is
1 is read, the page including this portion exists on the main memory, and access to the first half of the write area ends without any abnormality. If a page fault occurs when the second half is accessed, the instruction cannot be restarted from the beginning after page fault processing is completed. This is because the instruction word is destroyed by accessing the first half of the write address area 202.

In the case of FIG. 2(b), the address area 20 to be read first
4 is accessed, but the contents of the memory have not been rewritten at this time, so even if a page fault occurs here, execution can be resumed from the beginning of the instruction after page fault processing is completed. However, in the case of access to the write area 205, the read area 204 has already been rewritten by the time a page fault is detected in the latter half of the access to the write area 205, as in the case of FIG. 2(a). It becomes impossible to restart the beginning of the instruction after page fault 1 to processing ends.

Conventionally, in order to solve this problem, a method was adopted in which more registers were saved when a page fault occurred so that the instruction could be restarted midway, and a dummy access was always performed before actually writing an instruction with a write access. They used methods such as:

However, the former increases the burden on the microprogram,
The latter uses an extra number of microsteps for dummy accesses, and also performs dummy accesses even for accesses that do not cross page boundaries, significantly reducing performance.

Therefore, the present invention solves the above problem by detecting in advance whether or not there is a possibility that page fault 1- will occur and taking countermeasures.

FIG. 3 shows the generation mechanism of the page fault warning signal. Address data such as logical addresses 1], 1a, Hlb, and 1110 are stored in the logical address register LAR111. Here, 111a is an address two words before the page boundary, 111b is one word before the page boundary, and 111C is an address on the page boundary.

111a is an address in which, for example, the least significant bit is O, bits 0 to 11 are all 1, 101b is an address in which the lower 12 bits are all 1, and 101e is the lower 2 bits are all 0.

When the write area is one word, the write area does not straddle page boundaries, so there is no problem when a page fault occurs. Further, when the write area is, for example, 3 words or more, even if a dummy read is performed by a microprogram, the step increase rate of the microprogram is not very large, so this is also not a good luck.

For example, when the write access is for 2 words, special processing is required because it does not belong to any of the above two cases. If the write address is 1118 or 111C, no trouble occurs because the 2-word access area does not straddle the page boundary. That is, the access area straddles the page boundary only in case 111b. Therefore, 1
It is sufficient to provide a means to detect the case of 11b and take measures only in that case.Since the characteristic of 1llb is that the lower 12 bits are all 1, the 12-bit case as shown in Figure 4(a) For example, the alarm 131, which is a warning signal, can be easily obtained using an AND circuit 121a such as a wired-OR circuit.

A signal 133 in 401a is a warning signal generation permission signal given from the MMtl 122.

Memory access control unit MMU122 issues alarm 1.31
When received, only when the access request from the microprogram is a 2-word access, it instructs the DAT 123 to only perform address translation of the address 111c.

If the area at address 111c is not in the main memory, page fault processing is performed and the instruction is restarted from the beginning, but it is guaranteed that no page fault will occur when accessing 1lle.

Problems related to page faults can be avoided.

In this method as well, dummy access is performed in the same way as in the case of accessing three or more words, but since this is executed by the MMU 122, the number of steps in the microprogram does not increase.

Also, alarm 131 is issued when the address is 1.
115, and the increase in the number of cycles due to dummy access is on average 1/4096 (0,025%).
). Furthermore, if write access and 2-word access are added as conditions for performing dummy access, the increase in the number of cycles becomes almost negligible.

Further, in addition to the above embodiment, a warning can also be issued for 3-word access, 4-word access, etc.

That is, B A N < L A < B A (1
) It is sufficient to issue a warning when the following conditions are satisfied.

Especially when N=2'+1 (n is a non-negative integer), the fifth
As shown in the figure, this is equivalent to the condition that all bits from bit n to bit 11 are 1.

Figure 4(b) (when n=1) and Figure 4(c) (n-2
It is possible to issue the warning signal 131 using simple logic such as when

In FIG. 5, 501 is a memory address;
06 is a page boundary. Reference numerals 502 to 505 indicate access area buttons of 2 words, 3 words, 4 words, and 5 words, respectively, which straddle the page boundary 506.

In addition, in the above embodiment, the case where the warning signal 131 is sent to the MMU 122 was considered, but as shown in FIG.
31. Microprogram control part 6 of CPU10I
It can also be detected by 22.

If a warning is detected by the microprogram, it jumps to a subroutine where it performs a dummy access to the address of the next page. The following methods can be considered to implement dummy access.

■ Read access ■ Write access by negating the write signal ■ Performs only address conversion Furthermore, although the above embodiment prevents erroneous operations caused by writing to memory, after changing the register inside cPUlo1, It can also deal with page 7 and torque that occur in .

In other words, by generating a warning signal without waiting for a memory access request, it is possible to
This is a method in which page faults are checked before the registers in PUl0I are changed by the execution of an instruction.

With this method, even in a computer that has a register that changes with memory access, such as a stack pointer, it is possible to restart the instruction at the beginning after processing a page fault.

〔Effect of the invention〕

According to the present invention, since the instruction can be restarted from the beginning after page fault processing is completed, the burden on the microprogram for page fault processing can be reduced.

Preferably, dummy access processing is performed only when an alarm signal occurs and when write access is performed for a specified number of words, so that it is possible to restart the beginning of an instruction with almost no increase in the number of cycles on average. be able to.

More preferably, if the memory access control device automatically issues the dummy access, there is no need for the microprogram to check alarm signals, etc., and this eliminates the need for an increase in the number of steps in the microprogram and the complexity of the microprogram itself. can be avoided.

[Brief explanation of the drawing]

FIG. 1 is a system configuration diagram of an embodiment of the present invention. FIG. 2 is a diagram showing an example of a trouble caused by page fault 1-, FIG. 3 is a diagram showing a mechanism for generating a page fault alarm, and FIG. 4 is a diagram showing an example of the generation logic of a page fault alarm. FIG. 5 is a diagram showing an example of access across page boundaries, and FIG. 6 is a diagram showing a case where an alarm signal is detected by a microprogram. (α); (C no = 2 animals = ko; 3rd year high school 4th year high school student (α) (b) (υ (1ddreSS So+ ≦

Claims (1)

[Scope of Claims] 1. At least one logical address register for storing a logical address of memory used when executing an instruction, and a signal generating means for requesting memory access based on the contents of the register; an instruction execution part that receives data corresponding to the logical address as a result, an address translation mechanism that converts the logical address into a physical address, and a physical address register that stores the physical address generated by the address translation mechanism; a memory management part having a signal generating means for receiving a memory access request signal and the contents of the logical address register, setting it in the physical address register by the address translation mechanism, and requesting that memory access be performed according to the physical address; In a computer system that manages virtual memory and has a storage part that receives a memory access request signal corresponding to an address and a physical address and sends out the corresponding data, the contents of the logical address register, A, and the next page boundary address BA are used. 1. A virtual storage control device characterized by comprising means for comparing the values and detecting that the condition BA-N≦-LA<BA holds true for a certain predetermined natural number N. 2. In claim 1, the memory management unit receives a signal that the above condition is established, and is provided with means for detecting whether or not the next page boundary address BA is address convertible, independently of the instruction execution unit. A virtual memory control device featuring: 3. In claim 1, the instruction execution unit receives a signal that the above condition is established, and under the control of the instruction execution unit, means for detecting whether or not the next page boundary address BA is address convertible. A virtual storage control device comprising: 4. A virtual storage control device according to claim 1, characterized in that a part for generating a signal that the above-mentioned condition is met is included in an instruction execution part, and is realized by a microprogram.