JPS6073759A - Address conversion buffer - Google Patents

Abstract

PURPOSE:To obtain an address conversion buffer operable without an overhead by generating the interrupt which causes registration of an address only when a discrimination circuit detects through-pages, and an address conversion circuit detects the next page unregistration. CONSTITUTION:When data spreading on two different pages are read from a main memory unit, a page unregistration signal 700 is outputted because the data are not registered in an address conversion buffer (TLB) by the initial n- address access. Then a through-page discrimination circuit 3, which received an n+1 virtual address, outputs a through-page detection signal 300 into an ANd gate 4. On the otherhand, an address conversion circuit 2 has outputted the page unregistration signal 700 into the AND gate 4, thereby outputting an interrupt signal into an interrupt control circuit 5. After the interrupt has occured, control is shifted to a firmwear. Then a new address is registered, and at the n+1 address, registration operation of a real address is immediately executed.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to an address translation buffer in a computer system that employs a virtual storage method.

[Technical background of the invention]

Generally, in a computer system that uses virtual memory, memory is divided into pages of a certain size (for example, IK bytes), each page is numbered, and a set of these pages is called a segment, and each segment is also numbered. ing. The combination of the segment number, page number, and address within the page is called a virtual address. Note that since the segment number and page number are processed as a general term for page numbers in hardware processing, the combination of the page number and intra-page address will be described below as a virtual address.

A virtual address does not have a one-to-one correspondence with an actual memory address (this is called a real address), and the virtual address must be translated into a real address using an address translation table. Since this address translation table exists in memory, an address translation buffer (hereinafter referred to as TLB) is usually used to perform these address translations at high speed.
) is used. This TLBK registers only address translation tables for frequently used virtual addresses, so it is not registered in the TLB (in this case, I
For virtual addresses (referred to as TLB misses), processing such as registering them in the TLB again using firmware or the like is required.

By the way, as shown in FIG. 1, when reading the lower 2 bytes of data from address n of a 4-byte wide memory M, and reading the upper 2 bytes of data from address n+1, two bytes each (at address n, (address n+1) is required. When two bytes of data are in the same page, the address within the page simply increases by "2", and the page number and the corresponding real address do not change, so there is no need to convert the address. but,
Page Boundary in Figure 1 As already shown, when the above 4-byte data is read from memory M across two different pages, address conversion is performed in two memory accesses of 2 bytes each. It will have to be done. Moreover, each of these two memory accesses may cause a TLB miss error.

Figure 2 shows a conventional address translation buffer (TLB) that handles the case where a TLB miss occurs as described above.
FIG. 2 is a block diagram showing a configuration example. The virtual address 100 output from the virtual address register 1 is converted into a real address 200 by an address conversion circuit 2, and this address conversion circuit 2 stores the real address 200 in a main memory (not shown).
Outputs 0 and performs memory access. The virtual address 100 output by the virtual address register 1 is input to the page transfer determination circuit 3. When the page transfer determination circuit 3 determines that there is a page transfer, the page transfer determination circuit 3 outputs the virtual address 100. A signal 300 indicating that there is a page transfer is sent to the interrupt control circuit 5 through the AND gate 4 to generate an interrupt. The contents of a flip-flop (FF) 63- are applied to the other side of the AND gate 4, and the AND gate 4 is opened and closed. In addition, the address conversion circuit 2 is connected to the interrupt control circuit 5.
A TLB mishit detection signal 400 when an LB mishit is detected is input. Note that the page transfer determination circuit 3 receives a signal 500 indicating 4-byte access, and detects the presence or absence of page transfer based on this signal.

When reading data from memory M across two different pages as shown in Figure 1, if a TLB miss occurs in the first of two memory accesses,
The address translation circuit 2 sends a TLB miss signal 400 to the interrupt control circuit 5, and under the control of the interrupt control circuit 5, switching to firmware that registers a new address 600 in the address translation circuit 2 is performed. On the other hand, 1
If a TLB miss does not occur the first time, the address conversion circuit 2 outputs the real address 200 corresponding to the first virtual address, and at the same time, the page transfer determination circuit 3 determines that there is a page transfer and detects a page transfer. signal 30
0'ii is outputted to the interrupt control circuit 5 through the AND gate 4, and the interrupt control circuit 5 generates an interrupt. Note that at this time, the flip-flop 6 is set and the AND gate 4 is open.

After that, control is transferred to the firmware, which checks whether the second virtual address is registered or not, and if it is not registered, registers it, then resets the interrupt enable flip-flop 6e and activates the AND gate 4. After shutting down, the above memory access operation is performed again from the beginning. At this time, as in the previous case, the page passing detection circuit 3 outputs the page passing detection signal 300 (actually, this signal is "1"), but since the AND gate 4 is cut off, the signal 300 is not divided. The interrupt is not transmitted to the interrupt control circuit 5, and no interrupt occurs again. When the second address conversion is completed, the flip-flop 6 is reset to open the AND gate 4 and prepare for the next new memory access.

[Problems with background technology]

In such a conventional TLB configuration, an interrupt is generated every time a memory access that spans two pages is performed, and firmware processing is required each time, resulting in a long overhead and a significant drop in address translation processing performance. There was fear.

[Purpose of the invention]

SUMMARY OF THE INVENTION An object of the present invention is to overcome the above-mentioned drawbacks and to provide an address translation buffer that can perform memory accesses that involve page passing to a high degree without overhead.

[Summary of the invention]

The present invention determines whether or not at least a part of the real address of the next page corresponding to a given virtual address is registered in the translation table of the address translation circuit that converts a virtual address into a real address. Only when the page transfer discrimination circuit detects a severage transfer and the address conversion circuit detects that the next page is not registered when memory access is performed over two pages. The above object is achieved by activating firmware control to register a new address in the address translation circuit.

[Embodiments of the invention]

Hereinafter, an embodiment of the address translation buffer of the present invention will be described with reference to the drawings, where the same parts as those of the conventional example are denoted by the same reference numerals. Third
The figure is a block diagram showing an embodiment of the address translation buffer of the present invention. A virtual address 100 output from the virtual address register 1 is input to an address conversion circuit 2 and a page transfer determination circuit 3. The address conversion circuit 2 outputs the real address 200, and also outputs the TLB to the interrupt control circuit 5.
A mishit detection interrupt signal 400f is output, and a signal 700 indicating that the next page is unregistered (next page unregistered signal) is output to the AND gate 4. The page passing determination circuit 3 outputs the page passing detection signal 300 to the interrupt control circuit 5 through the AND gate 4.

FIG. 4 shows an example of the structure of the address translation circuit 2 shown in FIG. This address conversion circuit 2 consists of a memory section (address change table TLB) 7-7 and a comparator 8, and the memory section 7 has three areas 71.
It consists of 72.73. Part of the segment number and page number corresponding to the virtual address 100 are registered in the area 71 of the memory 7. Therefore, the segment number of the virtual address 100 input from the virtual address register 1 is registered as an address in the memory 7, and part of the segment number and page number is input to one side of the comparator 8. Then, part of the segment number and page number in the area 71 read from the memory 7 is input to the other comparator 8, and it is checked whether the real address corresponding to the virtual address 100 is stored in the memory 7. If there is no real address, the comparator 8 outputs an interrupt signal 400 indicating a TLB miss. The page number of the real address corresponding to the virtual address 100 is stored in the area 72 in the memory. The real address 200 output to the main memory is composed of the page number read from the area 72 of the memory 7 and the in-page address of the virtual address 100. Memory 7 territory! 738- stores information indicating whether or not the next page is registered in the area 72 for the virtual address, and the output 00 of the area 73 is " when the next page is not registered.
1", which is a high level. Note that areas 71 to 71 of memory 7
The contents of 73 are updated under firmware control.

FIG. 5 shows an example of the configuration of the page transfer determination circuit 3 shown in FIG. The page transfer determination circuit 3 consists of an AND gate 9 and an AND gate 10. Now, assume that the page size is IK bytes (1024 bytes), the main memory address is allocated in byte units, and the memory read data width is 4 bytes. Furthermore, it is assumed that only even addresses can be specified in memory accesses in 2-byte and 4-byte units. All data 800 in bits 22 to 30 of virtual address register 1 are logic “1”
”, for example, if there is a 4-byte access, the page will be transferred as shown in Figure 1, the output of AND gate 9 will be logic “1”, and the output of bit 30 will be logic “1”. And if the signal 500 indicating 4-byte access is logic "1", the output (page transfer detection signal) 300 of AND gate 10 becomes logic "1" and an interrupt is generated in AND gate 4. .

Next, the operation of this embodiment will be explained.

When reading data from the main memory across two different pages as shown in FIG. 1, first, when accessing address n, a TLB miss occurs, but a page unregistered signal 700 is output. Next, the page transfer detection circuit 3 which receives the virtual address of address n+1 generates a page transfer detection signal 300 shown in FIG. 5 and outputs it to the AND gate 4. However, the address conversion circuit 2 detects that the next page corresponding to the virtual address 100 is not registered in the access to address n, and a page unregistered signal 700 is output to the AND gate 4. As a result, an interrupt signal is generated from the SAND gate 4 to the interrupt control circuit 5. After the interrupt occurs, control is transferred to the firmware and a new address registration process is performed. Therefore, for address n+1, an interrupt signal is immediately generated and the real address registration operation is executed without responding to the comparison result of the comparator 8.

〔Effect of the invention〕

As described above, the address translation buffer 1 of the present invention has the effect of performing memory access involving page transfer at high speed without overhead.

[Brief explanation of the drawing]

Fig. 1 is a diagram showing page passing in memory, Fig. 2 is a block diagram showing an example of the configuration of a conventional address translation buffer, and Fig. 3 is a block diagram showing an embodiment of the address translation buffer of the present invention. , FIG. 4 is a block diagram showing a detailed example of the address translation circuit shown in FIG. 2, and FIG. 5 is a block diagram showing a detailed example of the page transfer determination circuit shown in FIG. 3. 1.・Virtual address register 2... Address conversion circuit 3... Page transfer determination circuit 4.9.10... AND gate 5... Interrupt control circuit 7... Memory section 8... Comparator substitute Private Patent Attorney Noriyuki Chika (and 1 other person) Ward C- Ten Kuchitsu Figure 3 Figure 4 Figure 5

Claims (1)

[Claims] In an address translation buffer that performs address translation from a virtual address to a real address at high speed, the virtual address [
An address translation table that stores information indicating whether at least a part of the corresponding real address and the part of the virtual address corresponding to the next page of the virtual address are registered, and the data to be accessed. A page transfer discrimination circuit that determines whether or not two pages are crossed on the main memory, and this page transfer discrimination circuit determines page transfer, and based on the above information, the next page is an address conversion circuit. Address translation buffer 1゜ characterized in that it is equipped with a means for generating an interrupt only when the instruction has not been registered, and when the above-mentioned interrupt condition is satisfied, the interrupt is generated before starting execution of the instruction.