JP2504500B2 - Address translation device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Outline] The present invention relates to an address conversion system, and more particularly, to an address conversion device for converting a logical address and a real address into an absolute address of a main storage device, which is capable of performing address conversion at high speed. For the purpose of, an address translation device for translating an operand address into an absolute address of the main storage device having a TLB, a real address confirmation means for confirming that the operand address is a real address, and a predetermined operand address The 0 confirmation means for checking whether all the upper addresses are 0, the address confirmation means for confirming whether a predetermined upper address of the operand address matches the address stored in the prefix register, and the real address confirmation means. Oleland address is a logical address by output Sometimes the operand address is output to the TLB, and when the operand address is the real address and the predetermined higher address is 0 by the 0 confirmation means, the higher address is replaced with the value of the prefix register, and the operand address is the real address. When the predetermined higher address of the operand address is the same as the value of the prefix register by the address confirmation means, all the bits of the predetermined address are replaced with 0, and the operand address is the real address and the predetermined higher address. When all the addresses are not 0 and the predetermined address does not match the value of the prefix register, a control means for outputting the operand address as it is is provided.

[Industrial applications]

The present invention relates to an address conversion system, and more particularly to an address conversion device for converting a logical address and a real address into an absolute address of a main memory.

[Conventional technology]

Conventionally, there are the following address translation devices as described above. This is to convert the input logical address into a real address, and further to convert this real address into an absolute address on the main memory.

Here, when the input address is designated in the translation mode, the logical address is translated into a real address by the dynamic address translation mechanism (DAT). However, when the program is written in the non-translation mode, the logical address and the real address match.

When converting a real address to an absolute address, when the number of processors of the computer is one, the values of the real address and the absolute address match, but in a computer adopting a so-called multiprocessor system having a plurality of processors, Has a real address space, and the real address space of each processor is converted into an absolute address space by a prefix conversion mechanism (prefix register). This is because the hardware fixed areas existing in the respective real address spaces are not overlapped in the absolute address space.

By the way, the above-mentioned DAT and prefix conversion is not executed each time the main memory is accessed, but TLB (T
ransration Lookaside Buffer) to hold a part of the logical address and absolute address for which DAT and prefix conversion have been performed, or a pair of real address and absolute address as an entry in the TLB to access the main memory device. In this case, first, the TLB is referred to by a logical address or real address, and when the entry to be referred to is found in the TLB, the logical address or real address is replaced with an absolute address, and the main storage device is accessed.

If the entry to be translated cannot be found in the TLB, the DAT and prefix translation mechanism translates the logical address or real address into an absolute address to access the main storage device, and the TLB performs the translation with the absolute address. Register an address or a pair of real address and absolute address as an entry in the TLB.

In this way, the time spent on DAT and prefix conversion is minimized.

[Problems to be solved by the invention]

By the way, in such an address translator, only the prefix translation is performed when the main memory is accessed by the real address.

In this prefix conversion, the address is converted only in the hardware fixed area and the area indicated by the address of the prefix register, and other addresses are the same as the real address and the absolute address. However, even if the real address and the absolute address are the same, one entry of the TLB is used, and in such a case, one entry among the registered entries is expelled. In addition, access to the hardware fixed area where the prefix conversion is performed is performed relatively frequently,
Even with logical addresses, the access frequency is high and they are driven out of each other, so the TLB hit rate decreases and address translation takes time.

Therefore, an object of the present invention is to provide an address translation device that can perform address translation at high speed.

[Means for solving problems]

As shown in FIG. 1, a means for solving the above-mentioned problems in the present invention is an address translation device 1 for translating a logical address and a real address which are operand addresses into an absolute address of a main storage device, which is a TLB2. Of the operand addresses, the real address confirmation means 3 for confirming that the operand address is a real address, and 0 for checking whether all predetermined upper addresses of the operand address are 0
The confirming means 4 and the address confirming means 5 for confirming whether a predetermined upper address of the operand address matches the address stored in the prefix register, and the output of the address confirming means 5 causes the operand address to be a logical address. Sometimes the operand address
When the operand address is a real address and the 0 address checking means 4 has a predetermined upper address of 0, the upper address is replaced with the value of the prefix register 6, and the operand address is a real address. When the predetermined upper address of the operand address is the same as the value of the prefix register 6 by the confirmation means 5, all the bits of the predetermined address are replaced with 0, and the operand address is the real address and the predetermined upper address. Is not all 0 and the predetermined address does not match the value of the prefix register, the control means 7 is provided for outputting the operand address as it is.

[Action]

According to the present invention, when the operand is a logical address, it is converted to an absolute address by the TLB, and when the operand is a real address, it is subjected to prefix conversion by the control means. Since it is sufficient to store the entry related to the logical address because it is not necessary to store the
The hit rate of will not decrease.

〔Example〕

An embodiment of an address translation device according to the present invention will be described below with reference to the drawings.

2 and 3 show an embodiment of the address translation device according to the present invention. In this embodiment, the address translation device has two TLBs, that is, a primary TLB (PRI-TLB).
And an alternate TLB (ALT-TLB). When an ordinary logical address is input as an operand address, when an entry corresponding to any TLB exists, the absolute address corresponding to that logical address is output. Address translation. Then, in the present embodiment, the address translation device uses the primary TLB (PRI-TL
B) and an alternate TLB (ALT-TLB) TLB match signal generator 10 for designating which TLB is permitted to output,
The address output device 40 actually outputs the absolute address. Then, the control means has a configuration excluding the TLB, 0 confirmation means and address confirmation means from these configurations.

The above-mentioned TLB match signal generator 10 has a configuration as shown in FIG. In the figure, 11 is an operand address holding device for holding an operand-addressed address, 12
Is the STO holding device that holds the state of the segment table origin that specifies which table to use, 13 is the MODE holding device that holds the mode specification information that specifies the usage mode, and 14 is the state when the operand address is a real address. 1 ”stands for the REAL information holding device as a real address confirmation means. In the figure, reference numeral 15 is a primary TLB, and 16 is an alternate TLB, which refer to the upper address of the operand address holding device 11 respectively, and are valid (V), mode (M), STO (S) and virtual. The status of the address (VR ADRS) is output. Further, in the figure, 17,18,19 are the above TLBs 15,16.
Mode (M), STO (S), virtual address (VR ADRS) and the predetermined address of the operand address holding device 11 and the outputs of the STO holding device 12 and the MODE holding device 13 are compared and they match. It is a comparator which sometimes outputs the state "1". Similar comparators 20, 21 and 22 are also provided on the alternate TLB 16 side. The reference numeral 23 indicates an AND gate to which the information obtained by inverting the valid state of the comparators 17, 18, 19 and the TLB and the state of the REAL information holding device 14 by the inverter 24 is input. The gate 25 and the inverter 26 are also provided on the alternate TLB 16 side. Further, 27 is a 0 state detecting device as 0 detecting means for outputting a state "1" when all the predetermined upper addresses in the operand address are "0" (hereinafter referred to as all 0 states), and 28 is this An AND gate for outputting a logical product of the output of the 0 state detecting device 27 and the output of the REAL state holding device 14 is shown. Further, the same 0 state detecting device 29 and AND gate 30 are also provided on the alternate TLB 16 side, and the output of the 0 state detecting device 29 of this alternate TLB 16 is inverted and input to the AND gate 30.

Next, the operation of this TLB match signal generator 10 will be described.

In this embodiment, when the operand address is a logical address, the REAL information holding device 14 is in the state "0", and therefore the state "1" is input to the AND gates 23 and 25 from the inverters 24 and 26, and the TLBs 15 and 16 ( V) and the state of the comparator are all "1", a TLB match signal is output from any TLB. When the operand address is a real address, the state of the REAL information holding device 14 is "1", the state "0" is input to the AND gates 23 and 25, and the AND gates 23 and 25 are in the state "0". Is output. Then, the 0-state comparators 27 and 29 determine whether or not a predetermined higher-order address of the operand address is in the all-0 state, and if it is the all-0 state, the state of the AND gate 28 on the primary TLB 15 side is "1" alternate TLB16. State becomes "0", and the primary TLB match signal is generated. When the value of the predetermined address is not all 0s, on the contrary, the state of the AND gate 28 on the primary TLB 15 side becomes "0" and the state of the AND gate 30 on the alternate TB16 side becomes "1", and the alternate TLB side.
A match signal is generated.

 The results are tabulated as shown in Table 1 below.

Next, the configuration of the address output device 40 that constitutes the address translation device according to the present embodiment will be described. In this example,
The address output device 40 has a structure as shown in FIG. In the figure, reference numeral 41 is a primary that outputs an absolute address corresponding to the upper address of the operand address.
TLB, 42 is a similar alternate TLB, 43 is an inverter that outputs the information of the REAL information holding device 14 described above and the information obtained by inverting this information, 44 is the absolute output that the primary TLB 41 outputs by the inverted output of this inverter Reference numeral 45 denotes a first selector for turning on / off, and 45 denotes a second selector for turning on / off the real address from the prefix register 6 by the non-inverted output of the inverter 43. On the alternate TLB 42 side, 46 indicates an inverter similar to the inverter 43 provided on the primary TLB 41 side described above, and 47 indicates a third selector similar to the first selector 44. Reference numeral 48 is a comparator as an address confirmation means for comparing the address of the prefix register 6 with the operand address and generating a state "1" and this inverted signal when they match, and 49 is a non-inverted output of the inverter 46. The fourth selector 50 outputs a predetermined address of the operand address when both the inverted output of the comparator 48 and the state "1" are present, and 50 is the state "1" when the non-inverted signal of the comparator 48 is in the state "1".
The fifth selector outputs an address (all 0s) in which the predetermined address is all 0s.

Therefore, according to the present embodiment, when the operand address is a logical address, the REAL information holding device 14 becomes the state "0", the inverted outputs of the inverters 43 and 48 become the state "1", and the operands indicating the logical address from the primary TLB 41 and the alternate TLB 42. The absolute address corresponding to the address is output. When the operand address is the real address, the REAL information holding device 14 is in the state "1", and the outputs of both TLBs are not output from the first and third selectors 44 and 47 and the second.
The selector 45 outputs the address of the prefix register 6. Further, in this state, when the value of the prefix register 6 and the value of the operand address do not match, the value of the operand address is the same as that of the fourth selector.
When the value of the prefix register 6 matches the value of the operand address, the fifth selector 50 outputs the address of all 0s.

When the outputs of the TLB match signal generator 10 and the address output device are combined, the address conversion device according to the present embodiment outputs the values shown in Table 2 below depending on the state of the operand address. It will be.

As described above, according to the address translator according to the present embodiment, when the real address is input, the translation can be executed by hardware without using the TLB when performing the prefix translation. Since it is not necessary to store the entry for the logical address, it is sufficient to store the entry for the logical address, so that the frequency with which the entries are driven out from each other decreases, and the hit rate of the TLB does not decrease. As a result, the address conversion including the prefix conversion can be executed at high speed.

〔The invention's effect〕

As described above, according to the present invention, since the translation can be executed by hardware without using the TLB in the prefix translation when the real address is input to the address translator, the TLB is an entry related to the real address. Need not be stored and it is sufficient to store the entry related to the logical address. For this reason, the number of times each entry is banished from the other in the TLB,
The TLB hit rate can be improved, and address conversion including prefix conversion can be performed at high speed.

[Brief description of drawings]

FIG. 1 is a principle diagram of the present invention, FIG. 2 is a block diagram showing a TLB match signal generator which constitutes an address translator according to an embodiment, and FIG. 3 is an address output which constitutes an address translator according to the embodiment. It is a block diagram which shows an apparatus. 1 ... Address converter 2 ... TLB 3 ... Actual address confirmation means 4 ... 0 confirmation means 5 ... Address confirmation means 6 ... Prefix register 7 ... Control means

Claims (1)

(57) [Claims] 1. A real address confirmation device for confirming that an operand address is a real address in an address translation device for translating a logical address and a real address, which are operand addresses, into an absolute address of a main storage device and having a TLB. Means, 0 confirmation means for checking whether all predetermined upper addresses of the operand address are 0, and address confirmation for confirming whether the predetermined upper address of the operand address matches the address stored in the prefix register. Means and the output of the real address confirmation means outputs the operand address to the TLB when the operand address is a logical address, and when the operand address is the real address and the predetermined higher address is 0 by the 0 confirmation means. Upper address prefix register When the operand address is a real address and the predetermined higher address of the operand address is the same as the value of the prefix register by the address confirmation means, all the bits of the predetermined address are replaced with 0, and An address conversion, characterized in that the operand address is a real address, the predetermined upper address is not all 0, and the predetermined address does not match the value of the prefix register, the control means outputs the operand address as it is. apparatus.