JPS63245743A - Memory access system - Google Patents

Abstract

PURPOSE:To suppress address conversion at its minimum required by selecting the access of an I/O device to a logical address memory or a physical address memory. CONSTITUTION:A logical/physical selection signal line for selecting a physical address or a logical address at the time of accessing a memory from a system bus 1 side is connected to the system bus 1. When the memory 23 is accessed from the system bus 1, a data processor 2 checks said logical/physical selection signal line and accesses the memory 23 by the route of gate 25 physical address 28 memory 23 when the access is based upon the physical address. In case of the access based upon the logical address, the memory 23 is accessed by the route of gate 24 logical address 27 MMU 22 physical address 28 memory 23 and the physical address 28 is outputted to the system bus 1 through the gate 26.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for an input/output device (hereinafter referred to as an I10 device) to access memory, and in particular, in a data processing system having a memory management mechanism. This relates to a memory access method for accessing memory.

[Conventional technology]

Converts logical addresses to physical addresses in page units,
Conventionally, the following various methods are known as methods for an I10 device to access memory in a data processing device having a memory management unit (hereinafter referred to as MMU).

1) Always access memory via the MMU using logical addresses.

2) When the data processing unit (hereinafter referred to as CPU) starts the ■10 device, by specifying the physical address,
I10 devices access memory directly by physical address without going through the MMU.

3) Prior to the first memory access and the memory access immediately after a page switch, the I10 device
A physical address is calculated by checking the address conversion table of U, and the memory is accessed using the calculated physical address.

[Problem that the invention seeks to solve]

Below, each conventional method will be explained using FIGS. 2 and 3,
Clarify those problems.

FIG. 2 shows an example of address conversion by an MMU, where 4 indicates a logical address space, 5 indicates a physical address space, and 22 indicates a memory management unit (MMU).

The logical address space 4 is divided into fixed sizes called pages. In order to simplify the explanation, FIG. 2 illustrates a case where the page is divided into three pages L1 to L3. The logical address space 4 has M M for each page.
It is projected by U 22 into the physical address space 5.

In FIG. 2, it is shown that page L1 is projected onto page P1, page L2 is projected onto page P2, and page L3 is projected onto page P3. Here, within each page, both the logical address space and the physical address space are continuous areas.

FIG. 3 shows the correspondence between logical addresses and physical addresses, where 41 and 42 are the upper and lower parts of the logical address, respectively, and 5L52 are the upper and lower parts of the physical address, respectively.

The logical address lower part 42 and the physical address lower part 52 are parts representing intra-page offsets, and are completely the same. The logical address upper part 41 is a part representing a page, and is converted into the physical address upper part 51 by the MMU 22.

In most I10 devices, the logical address space is accessed continuously, so here it is assumed that the access is performed in the order of page L1→page L2→page L3 shown in FIG.

Problems with method 1): In this method, since the I10 device continuously accesses the logical address space, address translation is performed by the MMU in all accesses.

However, address conversion by the MMU requires time, which reduces the throughput of the system bus.

Problems with method 2): In this method, the I10 device directly accesses the memory using a physical address in order to avoid the reduction in system bus throughput caused by method 1).

In this case, the CPU needs to notify the ■/○ device of pages P1 to P3 instead of pages L1 to L1 to L1 to 3 to start the device. However, since pages P1 to P3 are generally not continuous areas, the CPU divides each page into page P3.
1. Page P2. The I10 device must be activated a total of three times on page P3. Therefore, the overhead of the CPU becomes large and the processing capacity is reduced.

Problems with method 3): In this method, in order to avoid the CPU overhead in method 2), the CPU starts the ■/○ device with a logical address, but when crossing a page boundary on the I10 device side,
The physical address upper part 51 corresponding to the logical address upper part 41 is obtained by referring to the address conversion table of the MMU, and memory access is performed for each page using this.

However, in this method, the number of overloads of the I10 device increases, reducing the data transfer ability of the I10 device.

The present invention does not reduce the throughput of the system bus,
Another object of the present invention is to provide a method for an I10 device to access the memory of a data processing device having a memory management mechanism without increasing the overhead of the CPU and the I10 device.

[Means for solving problems]

M includes a memory management unit (MMU) that converts logical addresses output from the CPU into physical addresses in page units.
In a data processing system in which a data processing device that accesses memory using physical addresses output from an MU and an input/output device that accesses the memory of this data processing device are connected via a system bus, memory is accessed using logical addresses. A signal line is provided on the system bus to distinguish whether the data is accessed by a physical address or by a physical address. If the access is by a logical address, it is converted to a physical address via the MMU and the memory is accessed.
The input/output device outputs the physical address converted by the MU, and when accessing the memory for the first time and immediately after the page is switched, the input/output device accesses the memory using the logical address and also outputs the physical address output from the data processing device. The stored physical address is used to access the memory during other memory accesses.

[For production]

The present invention is based on the fact that in a memory management method that performs address translation on a page-by-page basis, both logical addresses and physical addresses are continuous within a page, and that in many I10 devices, continuous areas in the logical address space are accessed. This was done with attention to it.

That is, the system bus, CPU, and MMU.

In a data processing device having a memory, means for allowing the I10 device to select whether to access the memory using a logical address or a physical address, and means for notifying the I10 device of a converted physical address when accessing the logical address. By providing the I10 device, the I10 device accesses the memory using the logical address only during the first memory access when the physical address is unknown and when accessing the memory immediately after the page is switched, and does not receive the corresponding physical address. When a memory is accessed within the same page, the memory is accessed using a physical address based on the physical address that was retrieved.

By doing this, the ■/○ device only needs to be notified of the logical address when it is started up, and memory access via the MMU is also kept to a minimum.

〔Example〕

FIG. 1 shows an embodiment of the present invention, and only the relationship between address lines is shown here. In the same figure,
1 is a system bus, 2 is a data processing device, 3 is an input/output device (10 devices), 21 is a data processing unit (CPU),
22 is the memory management unit (MMU), the edict is the memory, 24
．． 25 and 26 are gates, 27 is a logical address, 3 is a physical address, 31 is a lower address counter, 32 is an upper logical address counter, 33 is an upper physical address register, 34 is an upper address selector, 35, 36 and 37 are signal lines , 38 is a lower address counter carry.
The data processing device 2 and the I10 device 3 are connected by a system bus 1. The data processing device 2 includes a CPU 21, an MMU 22 that converts a logical address 27 into a physical address 28 in page units, and a memory address accessed by the physical address 28.

Here, the system bus 1 is provided with a logical/physical selection signal line for selecting whether to access the memory 23 from the system bus 1 side using a physical address or a logical address. When the memory 23 is accessed from the system bus 1, the data processing device 2 checks the above-mentioned logical/physical selection signal line, and if the access is by a physical address, the memory is routed from the gate 25 to the physical address 28 to the memory 23. 23, while if access is by logical address, gate 24 → logical address 27 → M
The memory 23 is accessed via the route MU 22 → physical address 28 → memory 23, and the physical address 28 at that time is output to the system bus 1 via the gate 26.

At this time, the physical address to be output to the system bus 1 may be outputted to the address line by using a dedicated signal line or by using the address line of the system bus 1 in a time-sharing manner.

The lower address counter 31 in the I10 device 3 is an address counter for a portion corresponding to the intra-page offset portion, and is a lower address counter for a portion corresponding to the logical address lower portion 42 . It corresponds to the physical address lower part 52, and includes a logical address,
This is common to physical addresses, and its contents are output to the system bus 1 via the signal line 35. The upper logical address counter 32 is an address counter corresponding to the page designation part of the logical address, and is the upper logical address part 4 of FIG.
1, the lower address counter 31
The lower address counter carry 38 from the lower address counter 38 makes the address counter continuous with the lower address counter 31. On the other hand, the upper physical address register 33 is a register that holds a physical address corresponding to the page designation part of the logical address, and is a register that holds the physical address corresponding to the page designation part of the logical address, and is a register that holds the physical address upper part 51 of the physical address in FIG.
When the memory is accessed using a logical address, the physical address notified by the data processing device is set via the signal line 37.

34 is an upper address counter, which stores the contents of the upper logical address counter 32 and the upper physical address register 33.
and the contents of the system bus 1 via the signal line 36.
Output to.

When the I10 device 3 is activated with a logical address specified by the CPU 21, the I10 device 3 stores the specified logical address in the lower address counter 31. Upper logical address counter 3
Set to 2 to start memory access. In this case, at the time of the first memory access and immediately after the page is switched, that is, immediately after the lower address counter carry 38 from the lower address counter 31 has occurred and the upper logical address counter 32 has been counted, the upper address selector 34 selects the upper logical address counter 32, accesses the memory using the logical address, and sets the physical address notified from the CPU 21 in the upper physical address register 33. During other memory accesses, the upper address selector 34 selects the upper physical address register 33 and accesses the memory using the physical address.

By doing this, the CPU 21
When activating the , it is sufficient to specify a logical address, so the overhead of the CPU 21 does not increase. In addition, MMU is based on logical addresses that require address conversion time.
The memory access via 22 is only required for the minimum necessary memory access time, which is the first time and immediately after the page is switched, and the decrease in the throughput of the system bus 1 can be kept to a minimum.

Further, in order for the I10 device 3 to know the physical address from the logical address, there is no need for a special sequence such as referring to the address conversion table of the MMU 22, so the overhead of the I10 device 3 does not increase.

Furthermore, the amount of hardware according to the present invention is increased by a gate 26 which is a means for outputting a physical address to the system bus 1 when the data processing device is accessed by a logical address.
and ■/○ The device 3 only has an upper physical address register 33, which is a means for holding its physical address, and an upper address selector 34, which is a means for selecting a logical address and a physical address.Therefore, it can be implemented using simple hardware. The present invention can be realized.

〔Effect of the invention〕

As explained above, according to the present invention, when accessing by a physical address, the memory is directly accessed, and when accessing by a logical address, the memory is accessed by converting it to a physical address via the MMU, and the system bus The input/output device outputs the physical address converted by the MMU, and when accessing the memory for the first time and immediately after the page is switched, the input/output device accesses the memory using the logical address and also outputs the physical address output from the data processing device. Since the memory is accessed using the stored physical address during other memory accesses, the input/output device only needs to be notified of the logical address by the CPU at startup, and therefore the CPU can access the memory in page units. There is no need for the process of dividing the memory address into two parts and notifying the physical address, and memory access using logical addresses via the MMU, which requires address conversion time, is kept to the minimum necessary, and the drop in system throughput is also minimized.

[Brief explanation of drawings]

FIG. 1 is a diagram showing an embodiment of the present invention, FIG. 2 is a diagram illustrating address conversion by a memory management device, and FIG. 3 is a diagram showing the correspondence between logical addresses and physical addresses. 1-System bus 2-Data processing device 3--Input/output device (I10 device) 21--Data processing unit (CPU) 22-Memory management unit (MMU) Edict---Memory 24, 25.26-- - Gate 27 - Logical address 28 - Physical address 31 - Lower address counter 32 - Upper logical address counter 33 - Upper physical address register 34 - Upper address selector 35, 36.37 - Signal line

Claims (1)

[Scope of Claims] A memory management unit (hereinafter referred to as MMU) that converts logical addresses output from a data processing unit (hereinafter referred to as CPU) into physical addresses in page units; In a data processing system in which a data processing device that accesses a memory and an input/output device that accesses the memory of the data processing device are connected via a system bus, the memory is accessed using a logical address on the system bus. A signal line is provided to distinguish whether the access is by a physical address or by a physical address, and when the data processing device receives a memory access request from the system bus, if the access is by a physical address, the data processing device directly accesses the memory; If the access is based on a logical address, the memory is accessed by converting it to a physical address via the MMU, and the physical address converted by the MMU is output to the system bus. When accessing the memory immediately after switching, the memory is accessed using a logical address and the physical address output from the data processing device is stored, and during other memory accesses, the memory is accessed using the stored physical address. A memory access method that uses