JPH0442342A - Bus arbitration circuit - Google Patents

Abstract

PURPOSE:To easily change the priority when the bus using request signals received from plural data transfer modules are arbitrated by using a switch circuit and a preference circuit consisting of a memory storing plural priority patterns. CONSTITUTION:A request register 2 holds the bus using request signals REQ1 - REQn received from the data transfer modules M1 - Mn. A switch circuit 7 changes a priority pattern. A priority pattern store ROM 8 decides the priority of the bus using requests given from the modules M1 - Mn and uses the output of the circuit 7, an output ACK 112 received from a circuit 9 which shows either one of modules M1 - Mn can use a bus, and the output of the register 2 as addresses respectively. Then a bus use grant register 4 holds the bus use grant signals ACK1' - ACKn' received from the ROM 8. Thus a preference circuit 8 does not consist of hardware and the priority is easily changed.

Description

TECHNICAL FIELD The present invention relates to a bus arbitration circuit, and more particularly to a bus arbitration circuit that grants bus usage permission to bus usage requests from a plurality of data transfer modules according to predetermined priorities. be.

Prior Art An example of a conventional bus arbitration circuit of this type is shown in FIG. In the figure, a bus use request signal 1? for bus 1 from a plurality of data transfer modules M1 to Mn? EQl～RBQ
n is held in each corresponding bit of the bus use request register 2 and input to the priority circuit 3.

FIG. 4 is a diagram showing an example of the priority circuit 3 in detail. In this example, the bus use request signals RIEQI', REQ2°, R1SQ3' from the bus use request register 2 are
. . . is a priority circuit configured to be selected preferentially in this order.

For example, this priority circuit 3 receives a bus use request signal RIEQl.
', REQ2', and REQ3° are input at the same time, the bus use request signal REQF is
- At the same time as being input to 41, it is inverted by the inverter 31 and is input to anime game-1 42 to 4n.

The bus use request signals REQ2° and REQ8' are suppressed by AND gates 42 and 43, and the priority circuit 3 outputs only the bus use permission signal ACKI°. This bus use permission signal is held in the bus use permission register 4, and is output as the bus use permission signal A (, Kl).At the same time, the bus use request register 2 holds its own bus use request signal.
Reset.

Further, the bus use permission signal ACKI is inputted to the NOR gate 5, and inputted to the priority circuit 3 as a suppression signal 111 to suppress other bus use request signals. Bus use permission signal AC
After receiving the KI, the data transfer module M1 outputs a data transfer end signal ENold after completing the data transfer. This signal is ORed by the OR gate 6, and the bus use end signal E
The permission register 4 is reset as ND.

Thereafter, the bus use request signals REQ2° and REQ3' are also accepted according to the priority order as described above.

In the conventional bus arbitration circuit described above, the priority order is configured by hardware, so it is difficult to change the priority order, and as the number of data transfer modules increases, the amount of hardware for the priority circuit becomes extremely large. There is a drawback.

OBJECTS OF THE INVENTION An object of the present invention is to provide a bus arbitration circuit that can flexibly respond to changes in priorities and addition of data transfer modules without increasing the amount of hardware.

SUMMARY OF THE INVENTION According to the present invention, there is provided a bus arbitration circuit that grants bus use permission to bus use requests from a plurality of data transfer modules according to a predetermined priority order, the bus arbitration circuit comprising: A priority conversion setting switch that can freely set conversion data, and a storage means that uses the setting data of the priority conversion setting switch and a bus use request from the data transfer module as address inputs and stores bus use permission data in advance. There is obtained a bus arbitration circuit characterized in that bus use permission is granted based on the bus use permission data successively outputted from the storage means.

Embodiments Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the present invention, and parts equivalent to those in FIG. 3 are designated by the same reference numerals. This bus arbitration circuit includes a request register 2 that holds bus use request signals REQI-REQn from a plurality of data transfer modules M1-Mn, a switch circuit 7 that changes a priority button, and a switch circuit 7 that holds bus use request signals REQI-REQn from a plurality of data transfer modules M1-Mn. A CK11 determines the priority of the bus use request from the switch circuit 7 and outputs the output from the circuit 9 indicating that any one of the plurality of data transfer modules is in the bus use state.
2, a priority pattern storage ROM 8 whose address is the output of the bus use request register 2, and a bus use permission register 4 that holds the bus use permission signals ACKI' to ACKn' outputted from the ROM 8.

Further, the bus use permission signals ACKl to ACKn outputted from the bus use permission register 4 are sent to each transfer module M1 to Mn, and at the same time reset their own bus use request register 2 and transfer multiple data. A circuit 9 consisting of an OR gate indicating which one of the transfer modules is in a bus use state, and a reset circuit 6 consisting of an OR gate for inactivating the bus use permission signals ACK1 to ACKn at the end of data transfer. It is equipped with

In FIG. 2, there are three data transfer modules, and the priorities are as follows: when the output of the switch circuit 7 is "oo", the bus use request signal REQ1. ．． ReO2,I? 1 Q3,
When the output of the switch circuit is "ol", the bus use request signal REQ2. In this example, there are three types of priorities: ReO3 and REQI, and when the output of the switch circuit is "10", the bus use request signals REQ3°REQI and ReO2 are given.

Next, the operation of this embodiment will be explained with reference to FIGS. 1 and 2. Here, the priority is assigned to the bus use request signal RE.
The case where Ql, ReO2, and ReO3, that is, the output of the switch circuit 7 is "oo" (sw-○○ in FIG. 2) will be explained.

Assume that bus use request signals REQI, ReO2, and ReO3 are simultaneously input to this arbitration circuit. Bus use request signal REQ1. REQ2. REQ3 is set in the bus use request register 2 and input to the ROM 8. The address of this ROM8 is “000111”, and the ROM
Data “100” is read and bus use permission signal ACK
It is output as I'.

This bus use permission signal ACKI'' is set in the permission register 4, and sent as the bus use permission signal ACKI to the transfer module M1 that has output the bus use request signal.

Further, the bus use π'1 enable signal ACKI is outputted by the bus use permission register 4, and at the same time, the bus use request register 2 which holds its own bus use permission signal is reset, and furthermore, the bus use permission signal ACKI is received. The bus usage status display signal 112 is inputted to the circuit 9 consisting of an OR gate indicating that the transfer module M1 is in the bus usage status.
is input as the highest address of the ROM 8 to suppress other request signals.

Here, the ROM address is "100011" and R
OM data is read as "000", and bus use request signal REQ2. REQ'3 is suppressed.

After receiving the bus use permission signal ACKI, the data transfer module M1 sends a data transfer end signal E after the data transfer is completed.
Send NDI to or games 1-6. This or gate 1
06 outputs a data transfer end signal END and resets the bus use permission register 4. When this register 4 is reset, the bus request inhibition signal is also reset, making it possible to accept other bus requests.

Hereinafter, bus use request signal REQ2. The old EQ8 is also accepted according to the priority order shown in FIG. 2 in the same manner as above. In this embodiment, there are three data transfer modules, but
The present invention is not limited to this, and it is clear that even if the number of data transfer modules increases, the data in the ROM may be increased accordingly.

Although a ROM is used as an example of the priority circuit 8, it goes without saying that a RAM in which data can be freely rewritten may also be used.

As described in detail, according to the present invention, when arbitrating bus use request signals from a plurality of data transfer modules, a priority circuit comprising a switch circuit and a memory storing a plurality of priority patterns is used. By using , priority changes can be easily changed using only switch circuits. Also, conventionally, priority circuits were composed of AND gates and OR gates, so the larger the number of data transfer modules, the more hardware the priority circuit requires. Although the size of the data transfer module becomes extremely large, it is possible to easily accommodate an increase in the number of data transfer modules by simply changing the contents of the memory.

[Brief explanation of drawings]

Figure 1 is a block diagram of an embodiment of the present invention, Figure 2 is a ROM
3 is a block diagram of a conventional bus arbitration circuit, and FIG. 4 is a circuit diagram showing a specific example of the priority circuit 3 of FIG. 3. Explanation of symbols of main parts 1... Bus 7... Switch circuit 8... ROM M1 to Mn... Data transfer module

Claims (1)

[Claims] (1) A bus arbitration circuit that grants bus usage permission to bus usage requests from a plurality of data transfer modules according to predetermined priorities, and that can freely set conversion data for converting the priorities. It includes a priority conversion setting switch, and storage means in which the setting data of the priority conversion setting switch and the bus use request from the data transfer module are input as addresses, and bus use permission data is stored in advance, and the data is stored in the storage means. A bus arbitration circuit characterized in that bus use is permitted based on read bus use permission data.