JPS6242306B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an interrupt control method in a multiprocessor system in which a plurality of processor modules and a plurality of input/output device control modules are connected through a common bus.

In such a conventional multiprocessor system, each input/output device control module employs an interrupt control method in which an interrupt signal is sent as a level signal to the processor module through a dedicated signal line. In this method, it is necessary to provide a number of dedicated interrupt signal lines on the bus equal to the number of input/output device control modules or the number of necessary interrupt factors. For this reason, there was a drawback that the number of pins for the printed board plug was insufficient. Additionally, consideration is given to wiring on the backboard to avoid a shortage of pins, but in this case, the interrupt level is determined by the insertion position of the printed board, which affects expandability and the inserted printed board. The disadvantage was that the freedom of choice was lost.

SUMMARY OF THE INVENTION It is therefore an object of the present invention to provide an interrupt control method that does not have the above-mentioned drawbacks.

Another object of the present invention is to provide an interrupt control method that eliminates the above-mentioned drawbacks and can easily increase the number of interrupt levels.

A feature of the present invention is that interrupt information, including the device number or interrupt level of the module and the number of the processor module to which the interrupt is placed, is transmitted from the input/output device control module that generated the interrupt request to the address/data line of the common bus. Each processor module determines whether the interrupt destination processor module number in the interrupt information on the bus address/data line corresponds to its own module number, and sends the interrupt information to the corresponding processor module. This is an interrupt control method that processes interrupts according to the device number or interrupt level.

In order to carry out the present invention, it is necessary to take measures such as providing each processor module with a decoder for decoding interrupt information on the address/data line, but these will be explained in detail in one embodiment. explain.

FIG. 1 is a general schematic diagram of a multiprocessor system to which the present invention is applied. A plurality of processor modules 10 and a plurality of input/output device control modules 11 are connected by a common bus 12. Each processor module 10 generally needs to have a priority interrupt mechanism.

FIG. 2 is a block diagram showing one embodiment of the present invention, in which one of the processor modules 10 and the input/output device control module 11 in FIG.
A portion related to one interrupt control and some signal lines of the common bus 12 are shown.

common bus 12 to processor module 10
, the interrupt command line 45 is input to the AND gate 33, and three signal lines 47 among the address/data lines 44 are input to the processor number decoder 3.
0, and the other four signal lines 48 of the address/data lines are input to the interrupt level decoder 31. Note that the interrupt command line 45 is common to all input/output device control modules.

One of the eight output lines of the decoder 30, which is specific to the processor module, is connected to the AND gate 33.
The output of the gate is input to a gate group 32 that gates the output of each bit of the decoder 31.
is input to each gate group 32 as a passage control signal. The gate group 32 inputs the signals of each bit of the output of the decoder 31 to the interrupt priority control circuit 34 all at once when the output of the AND gate 33 becomes "1".

The output signal of gate group 32 is latched in interrupt priority control circuit 34 and compared with the interrupt level currently being serviced, and if the interrupt level of the newly latched signal is high, it is routed to interrupt line 49.
The signal is supplied to the processor 35 via the processor 35. Processor 35 and interrupt priority control circuit 34 are also connected by control lines 50 and 51.

In the input/output device control module 11, the contents of the register 37 are transferred to the common bus 12 via the gate group 36.
The data is output to the address/data line 44 of the address/data line 44. Also, the signal line 35 indicating that the module 11 is using the bus is connected to the AND gate 4.
0 and 41. A signal line 54 is input to the gate 40 in addition to the signal line 53, and the output thereof controls the gate 36 and is simultaneously sent to the busy signal line 46 on the bus via the inverter 38. This busy signal line 46 is common to all input/output device control modules. A signal line 52 is input to the gate 41 in addition to a signal line 53, and its output is sent to the buffer 3.
9 to the interrupt command line 45 on the bus.

Next, the operation when an input/output device control module 11 issues an interrupt to a certain processor module 10 will be described.

In the input/output device control module 11, interrupt information is stored in the register 3 with a bit configuration as shown in FIG.
It is set to 7. A signal line 53 indicating that the module 11 has obtained the right to use the bus line.
and the signal line 54 instructing to send the contents of the register 37 to the address/data line are set to "1", and the output of the AND gate 40 becomes "1", so the interrupt information in the register 37 is Sent on address/data line 44. At the same time,
A busy signal is sent to the busy signal line 46 via the inverter 38. Then the signal line 52 becomes “1”
Therefore, a strobe signal is sent to the interrupt command line 45 via the buffer gate 39. FIG. 3 shows a timing chart of the address/data line 44, interrupt command line 45 and busy signal line 46.

In each processor module, a decoder 30 decodes the processor number ( ²¹⁴ to ²¹³ bits in FIG. 4) of the interrupt information on the address/data line 44. For processor module 10 with the corresponding processor number, AND gate 3
The output line of the decoder 30, which is one input of the signal 3, becomes "1". Therefore, interrupt command line 4
The stroke signal above 5 opens the gate group 32 all at once via the AND gate 33.

On the other hand, the interrupt level decoder 31 decodes the device number or interrupt level (bits ²⁷ to ²⁴ in FIG. 4) of the interrupt information on the address/data line 44, and selects the corresponding one of the 16 output lines. A “1” signal is output to one of the interrupt levels. The output of the decoder 31 is then input to the interrupt priority control circuit 34 via the gate group 32. That is, from the perspective of the interrupt priority control circuit 32, it is the same as if the interrupt signal was individually given from the input/output device control module as in the conventional case.

The interrupt priority control circuit 34 determines the priority and sends the interrupt to the processor 35 via the signal line 49, and then from the processor 35 to the signal line 5.
0 sends a signal indicating that the interrupt request has been accepted. When the signal on the signal line 50 is received, data such as the program jump address is sent from the interrupt priority control circuit 34 to the processor 35 via the signal line 51, and at the same time, the interrupt priority control circuit 34 sends data such as the jump address. The request latch information for the corresponding interrupt that was sent is reset, the interrupt service flag is set, and preparations are made for subsequent interrupt input. Note that the interrupt priority control circuit 31 may be the same as the conventional one, and for example, integrated circuits 82 and 59 manufactured by Intel Corporation in the United States may be used.

In the embodiment described above, the processor number of the interrupt information is expressed using 3 bits, and the device number or interrupt level is expressed using 4 bits, but the present invention is not limited to this. Similarly, the bit position of the interrupt information is not limited to the above-mentioned position.

As described above, according to the present invention, the number of signal lines for interrupts can be significantly reduced, and problems such as implementation problems due to insufficient number of pins and restrictions on the number of interrupt levels can be solved. Many advantages can be obtained, such as the ability to easily expand the system within the range allowed by the number of bits of interrupt information.

[Brief explanation of the drawing]

FIG. 1 is a general configuration diagram of a multiprocessor system to which the present invention is applied, and FIG. 2 is an embodiment of the present invention.
FIG. 3 is a timing chart for explaining the operation of the same embodiment, and FIG. 4 is a diagram showing an example of the bit configuration of interrupt information. be. 10...Processor module, 11...I/O device control module, 12...Common bus, 3
0...Processor number decoder, 31...Interrupt level decoder, 32, 36...Gate group, 3
4...Interrupt priority control circuit, 35...Processor, 37...Register, 44...Address/data line, 45...Interrupt command line, 46...Busy signal line.

Claims (1)

[Claims] 1. In a system in which multiple processor modules and multiple input/output device control modules are connected via a common bus, each input/output device control module receives the device number or Interrupt information including the interrupt level and the number of the interrupt destination processor module is sent to the address/data line of the bus, and each processor module transmits the interrupt destination processor module number of the interrupt information on the address/data line of the bus. An interrupt control method characterized in that it is determined whether a module number corresponds to the number of its own module, and the corresponding processor module processes an interrupt according to a device number or an interrupt level included in interrupt information.