JPH0227696B2 - JOHOSHORISOCHI - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an information processing apparatus, and particularly to a configuration of an information processing apparatus in which a plurality of data processing units transfer data to a common memory.

In recent years, with the diversification and multiplication of data processing, complex information processing devices (multiprocessing systems) for the purpose of multiple processing have been developed. In this method, a series of data processing is subdivided into a plurality of processes, a dedicated information processing device (hereinafter referred to as a processor) is provided for each process, and data processing is performed by competing with these plurality of processors. For this reason, each processor is connected by a bus for data transfer, and at least one common memory that is shared and accessed by each processor is connected to this bus. Further, each processor is configured in units of word length (number of bits) necessary for processing given data. For example, the processors may have different processing word lengths, such as a processor that transfers data with input/output equipment that processes 8 bits, and a processor that performs high-speed calculations that processes 16 bits.

Conventionally, in complex information processing devices (multiprocessor systems) that are composed of multiple processors with different processing word lengths, the bus is configured with a bit length based on the longest word length or the shortest word length among them. , which was used as a common bus for each processor. Figure 1 is a system configuration diagram of a composite processor using such a common bus, which includes a 16-bit processing processor 100 with 16-bit data input/output terminals,
A processor 110 for 8-bit processing having 8-bit data input/output terminals is connected to a common bus 120 having a 16-bit configuration. here 13
0 is a common memory group commonly used by processors 100 and 110.

In a multiprocessor system that uses multiple processors with different data processing word lengths, the 8-bit processing processor 110 is used for devices such as input/output devices that often process data with a short word length (8 bits), while the 8-bit processor 110 is used for high-speed processing. By using a processor 100 with a long processing word length (16 bits) in a device that requires data processing, processing according to the purpose can be executed smoothly and without waste. However, in the configuration shown in FIG. 1, the period during which the processor 110 for 8-bit processing uses the common bus 120 is
The processor 100 for 16-bit processing uses the common bus 1.
20 could not be used. In particular, even if the memory accessed by the 8-bit processing processor 110 and the memory accessed by the 16-bit processing processor 100 are different chips, since the 16-bit processing processor 100 cannot use the common bus 120, the processing The problem was that the processing speed was slowed down because it could not be executed. Furthermore, the processing speed of the entire system could not be increased due to the inefficient use of the common bus.

On the other hand, as a method to improve processing speed, there is a method in which the input/output data is assembled into 16 bits on the 8-bit processor 110 side and then transferred to the common bus 120. Considering the extended processing time required, it could not be said to be a satisfactory multiprocessor system. It is also possible to separate the bus by making the memory accessed by each processor exclusive memory for that processor.
Since memory separated by a bus cannot be used by processors connected to other buses, memory usage efficiency is poor, and since memory is added to each processor, the overall memory capacity of the system is insufficient. The disadvantage is that it increases the need. Therefore, in order to make effective use of a small memory capacity, it is necessary to share the memory with each processor, making it difficult to improve memory usage efficiency.

The present invention was made in view of the above circumstances, and
The purpose is to provide an information processing device that increases bus usage efficiency and increases data processing speed without increasing memory capacity.

In order to achieve the above object, the information processing device of the present invention includes a first bus having n bit lines, and a first processing means connected to the first bus to transfer data using the bus. , a second bus having 2n bit lines and provided separately from the first bus, and a second process connected to the second bus to transfer data using the bus. a shared memory connectable to the first and second buses and commonly accessible by the first and second processing means; The second processing means is configured to be able to transfer data in both n-bit units and 2n-bit units.

In this configuration, the first and second processing (control) means connected to the first and second buses are as follows:
Any hardware mechanism may be used as long as it is capable of receiving data, transmitting data, or both. For example, a processor including a central processing unit (CPU), or simply a CPU block, an input/output control device that transfers data with peripheral devices, a register that inputs data from memory, outputs data to memory, etc. Data processing Any device that has the function of receiving transferred data or creating data to be transferred may be used. Furthermore, the common memory connected to the first and second buses can be considered as a general term for any number of memory chips, from one memory chip to multiple memory chips.
It can also be considered as a memory block within a one-chip microcomputer. In addition, the first bus and the second bus are configured so that independent data can be transferred simultaneously, and these buses include a common memory, a dedicated memory, a CPU, an input/output control device, or one Devices having various data processing functions such as chip microprocessors are connected as appropriate.

According to the present invention, commonly used memories are not simply connected to one common bus, but are configured to be connected to multiple buses capable of transferring data of a number of bits depending on the purpose. Because of this, multiple processing mechanisms do not have to compete with each other to use one bus, and each can use the assigned bus independently, so data processing speed can be significantly improved. Furthermore, since the common memory is configured so that it can be connected to any of these plurality of buses, the given capacity can be utilized to the maximum extent without increasing the memory capacity. Furthermore, by making the number of bits constituting the bus equal to the processing word length, efficient data transfer can be performed. In this case, it is only necessary to switch and control the number of bits of data read from the common memory or data written to the common memory as described later.

Embodiments of the present invention will be described in detail below with reference to the drawings.

Here, a multiprocessor system will be described as an example in which each of the first and second processing means has independent processors and two memories that can be commonly accessed by these processors.

FIG. 2 is a block diagram of a multiprocessor system showing an embodiment of the present invention, in which a 16-bit bus 230 having 16-bit parallel bit lines and an 8-bit bus 240 having 8-bit parallel bit lines are independently operated. However, the 16-bit bus is connected to a processor 210 for 16-bit processing used for high-speed calculations, etc., and an additional mechanism 270 such as a dedicated memory, input/output control device, and registers used by this processor 210 in data processing, and an 8-bit bus 240 peripherals (keyboard, printer, display, etc.)
A processor 220 for controlling input/output devices for 8-bit processing is connected to the processor 220, and additional mechanisms 280 such as input/output devices and registers for data transfer with this processor 220. Furthermore, these buses 23
0 and 240 are shared memories 250 and 26 that can be commonly used by the processors 210 and 220.
0 is provided so that it can be connected to both buses.

With this system configuration, the 16-bit processor 210 uses the bus 230 to access the common memory 25.
0, while simultaneously using an 8-bit processor 22
0 tries to access the common memory 260 using the bus 240, the memory 250 is accessed from the bus 23.
By connecting memory 260 to bus 240, the processes of the respective processors can be executed simultaneously and in parallel without any delay in memory access. Now, let's assume that the 16-bit processor 210
If the 8-bit processor 220 and the 8-bit processor 220 are accessing the same memory, for example 250, at the same time, or if one of them attempts to access the other, a priority determining circuit is provided as described later, and this circuit assigns the memory to the processor given priority. The remaining processors may be given the right to use the memory with priority, and the remaining processors may be allowed to use the memory after the access of the prioritized processor is completed. Usually, the 8-bit processor 220 is replaced by the 16-bit processor 210.
The 16-bit processor 2 performs input/output data processing based on the commands of the processor, and is programmed to use common memory if necessary.
The 8-bit processor 220 rarely accesses the memory module in which the processing program for 8-bit processor 10 is stored. Therefore, in many cases, the two processors 210 and 220 can access the common memory independently using their respective buses and perform data processing in parallel, and the processing time is approximately the same as each processor's own. It is determined by the processing speed, and data processing can be executed effectively at high speed. Particularly during the period when processor 210 is transferring data to memory 250, it is easy for processor 220 to transfer data to additional mechanism 280 using bus 240.

Next, in order to explain in more detail the common memory connectable to the two buses in the system of FIG. 2 and its connection control, the main parts thereof are shown in blocks in FIG. Two buses are used, an 8-bit data bus and a 16-bit data bus, and the common memory is designed to be able to store 8-bit data (1-byte data) per address.
Two bytes of data are read/written to the bit bus. The 8-bit processing processor 360 uses the address bus 3 of the 8-bit bus.
01 is connected to a memory access control signal 302 that controls reading/writing to memory and an 8-bit data bus 303, and a 16-bit processing processor 370 is connected to a 16-bit address bus 30.
4. 16-bit bus memory access control signal 30
5 and 16-bit data buses (lower 8-bit bus 3
06 and the upper 8-bit bus 307). The memory is configured so that 8-bit data specified by a corner number address is transferred to the signal line 308, and 8-bit data specified by an odd number address is transferred to the signal line 309, and one set each of even and odd addresses is used. The upper and lower bits of 16-bit data are defined as . Furthermore, it has an 8-bit bus control circuit 350 and a 16-bit bus control circuit 351,
The address signal 310 and access signals 311 and 312 output from these are used to control the even address memory block 340 and the odd address memory block 34.
1 is accessed. In addition, each bus control circuit 35
0,351 is the corresponding processor 360,370
It may also have a function to decode address data sent from. Here, processor 360
can read data one byte at a time by sequentially specifying memory addresses MO, MO+1, ..., but the processor 37
For 0, it is necessary to control the address so that addresses MO and MO+1 are specified as one address and 2 bytes of data are read out at the same time. Further, from the bus control circuits 350 and 351, the processor 370
memory access request signal 313 and processor 3
The memory access request signal 315 from 60 is output to the priority determination circuit 352 when each processor accesses the memory, and as a result, the memory access permission signal 314, 31 is sent to the one with higher priority.
6 is output. If only one of them makes a request, an immediate permission signal is issued. Further, 8-bit bidirectional data buffers 330 to 333 are inserted between the memory and the bus, and data at even addresses and data at odd addresses of the memory are transferred through these buffers. This buffer control is
In the case of an even address, the control signal 317 causes buffer 3.
30 is activated, and control signal 3 is activated for odd addresses.
At step 18, the buffer 331 is operated. Further, buffers 332 and 333 connected to the 16-bit bus are set to an operating state by control signals 319 and 320 simultaneously or time-divisionally based on the address from processor 307.

According to this circuit configuration, when the processor 360 accesses the memory block 340 or 341 from the 8-bit bus 301 to 303 side, the control circuit 350 decodes the address bus 301 and the memory access control signal 302 to give priority to the memory block 340 or 341. A memory access request signal 315 is output to the ranking determining circuit 352. At this time, the priority order determination circuit 35
2, when there is no memory access request from the 16-bit bus 304 to 307 side, or when requests occur at the same time, it is determined which one has a higher priority and permission is given to the one with the higher priority. If permission is now given to the 8-bit processing processor 360, the control circuit 350 waits for the access permission signal 316 to become valid, and if the information on the address bus 301 is an even number, the data buffer is 330 and memory block 340
A specified address in the memory 340 and the 8-bit data bus 303 are selected, and read or write processing is specified by the control signal 311.
are connected and data transfer is performed. On the other hand, when the address is an odd number, reading or writing is designated by the control signal 312, and the memory 341 and the 8-bit bus 303 are connected under the control of the buffer control signal 318 to enable data transfer.

Next, the processor 370 converts the 16-bit bus 304 to
When the memory blocks 340 and 341 are accessed from the 307 side, the address signal from the address bus 304 and the memory access control signal 305 are decoded by the control circuit 351, and the memory access request signal 3 is sent to the priority determination circuit 352.
Outputs 13. As a result, if a permission signal is issued, the memory block 34 is
Select each 1-byte data from 0,341,
Buffer 33 is used to perform read or write operations specified by control signals 311 and 312.
16-bit bus 3 with both 2 and 333 in operation
Connect 06,307 and memory. If the processor 370 requests only 8 bits of data, only one of the memory blocks 340 or 341 is selected and the buffer connected to the selected memory block is operated to configure 16 bits. It is connected to either the upper or lower 8-bit bus 306 or 307.

As described above, the common memory can be connected to both the 16-bit bus and the 8-bit bus, and the memory can be disconnected from the bus during periods when the processor is not transferring data to the memory. Bit processing processor 3
The 60 and 16-bit processing processors 370 can access a common memory using their respective dedicated buses without competing for the same bus. Therefore, as described above, the data transfer speed can be improved and the processing time can be significantly shortened. Further, even if a plurality of memories as shown in FIG. 3 are provided, each data bus can be used efficiently, and each processor can perform high-speed memory access without waiting time.

In the above embodiment, an example is shown in which there are two buses of 8 bits and 16 bits, but more buses may be provided. At this time, as for the block configuration of the common memory, the number of bits defined by the bus having the smallest processing word length (number of bits) is 1 byte. Furthermore, the memory block 34 shown in FIG.
0, 341, control circuits 350, 351, priority determining circuit 352, and buffers 330 to 333 may be integrated in one chip or may be formed separately. Furthermore, the present invention can be applied to a system having one processor and a plurality of memories, and when this processor executes data processing with different processing word lengths, it is possible to provide a plurality of buses according to the word lengths. , the effects of the present invention can be sufficiently obtained by configuring it so that it can be connected to a memory. Further, a means for connecting these different buses via a gate circuit or the like may be provided to transfer data from one bus to another. Additionally, when a 16-bit processor transfers 8-bit data in a time-division manner, the two buses may have the same number of bits (8 bits) even if they are separated.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the configuration of a conventional multiprocessor system, FIG. 2 is a block diagram showing an embodiment of the present invention, and FIG. 3 is a block diagram showing the main parts of FIG. 2 in detail. . 100,210,370...processor for 16-bit processing, 110,220,360...processor for 8-bit processing, 120,230...16-bit bus, 240...8-bit bus, 130,25
0,260...shared memory, 270,280...
Additional mechanism, 301, 304...address bus, 3
02,305...Memory access control signal, 30
3...8-bit data bus, 306, 307...
16-bit bus of 8 bits each, 308... 8-bit data line of even address value (lower bit), 30
9... 8-bit data line of odd address value (upper bit), 317-320... Control signal, 31
5,313...Memory request signal, 314,316
... Permission signal, 352 ... Priority determining circuit, 3
50, 351...Memory control circuit, 340, 34
1...Memory block, 330-333...Data buffer, 360...8-bit processor,
370...16-bit processor.

Claims (1)

[Claims] 1. A first bus of n bit length connected to a first processor whose processing unit is n bit length, and
Second and third buses each having a length of n bits are connected to a second processor whose processing unit is bit length, and first and second memories are commonly connected to the first to third buses. each of the first and second memories includes a first bus control circuit that is connected to the first bus and controls access to the memory block; and a first bus control circuit that is connected to the second and third buses. a second and third bus control circuit for controlling access to a memory block; a priority determination circuit connected to the first bus control circuit and the second and third bus control circuit; When one processor accesses the first memory and the second processor accesses the second memory, the first memory and the first bus are connected; By connecting the memory of the first processor and the second and third buses, each processor can access different memories at the same time.
When two processors access the same memory, the priority determining circuit allows one of the processors to access the memory according to the priority order,
The first processor uses the first bus under the control of the first bus control circuit.
2n bit length data is transferred to the second processor using the second and third buses simultaneously under the control of the second and third bus control circuits. and a second mode in which n-bit length data is transferred using either the second or third bus. Information processing equipment.