JPS60110065A - Dual port memory - Google Patents

Abstract

PURPOSE:To prevent a defect of data transmission between systems of different number of bits by prescribing a fixed time width during which the access is possible with a system and starting again the transfer of data in the next access mode in case the data transfer is not finished within said fixed time. CONSTITUTION:When an access request is given from a 16-bit system, a 16-bit system bus A is connected to a dual port memory D after the access is validated in a certain time width. Then the 16-bit data transmitted via the bus A is written to an address within the memory D designated by an address signal sent via the bus A. In case an access request is given from an 8-bit system in the same time width, an 8-bit system bus B permitted in the next time width is connected to the memory D via a buffer F.

Description

Detailed Description of the Invention [Technical Field of the Invention] The present invention provides a dual port memory (dual port memory) that can be accessed from both a 16-bit system and an 8-bit system in a microconverter, etc.
ry).

[Prior art]

Conventionally, a device of this type is shown in FIG. 1. In the figure, Bl is a bus dedicated to a 16-bit microcomputer system (referred to as a 16-bit system bus in this specification), (Bl is a bus dedicated to an 8-bit microcomputer system (referred to as an 8'-bit system bus in this specification), (c) is the access arbitration circuit, (D) is the dual port memory.Dual port memory +3
ff) l is composed of keys.

When a 16-bit system microcomputer (not shown) and an 8-pin system microcomputer (not shown) attempt to access the dual port memory 'J (D), they each use a 16-bit system bus (
Sends an access request to the access arbitration circuit (Cl) via A) and the 8-bit system bus (B).Access arbitration 1p
Route 1 (C1 connects the system bus that requested access to the pool port memory (D) when access fees from both sides do not conflict. Access device from both sides)
When k conflicts, access rights are given to one of the systems according to a predetermined 1·p priority order. However, in the conventional method, if the access axis is given and the access is in progress, control is not performed to interrupt the access, and if the access axis is When this happens, a flag indicating the end is sent to the other party's system bus via the access arbitration circuit (C) via the system bus.

For example, when transferring data from a 16-bit system microcomputer to an 8-bit system microcomputer, 16-bit units of data are written to the dual port memory via the 16-bit system bus (A)4, and this writing is completed. 8 flags indicating that
When data is sent to the bit system (B1), the microcomputer of the 8-bit system issues an access request to the access arbitration circuit (C1), obtains access rights, and reads out the contents of the dual port memory IJ (DJ) in 8-bit units.

Conversely, a similar procedure can be used to transmit data from an 8-bit system to a 16-bit system.

Since the conventional device is constructed as described above, it has the following drawbacks. In other words, even if an access request is issued from one system, if another system is currently accessing, the access cannot be accessed until the other system is accessed.If an accident occurs in the system being accessed and the access is not completed, n For example, a system that made an access request later was forced to wait! ! : Manaru.

Also, from the perspective of a 16-bit system, the 8-bit data written from the 8-bit system to the dual port memory D) is half of the data, and the 8-bit data that is written from the 8-bit system to the dual port memory D) is half the data. Bit data is 8
2 from bit system to dual boat memory Q))
It is necessary that consecutive address locations corresponding to one address in a 16-bit system be written accurately by one access. Therefore, if the timing of loading v1 into memory (1)) from an 8-bit system and releasing it from memory (1) D) by a 16-bit system is incorrectly controlled, meaningless data will be transmitted.
Transmission failure due to soft error.

Similarly, when writing 1 to dual port memory 0 from a 16-bit system and reading it from an 8-bit system, a transmission failure due to a soft error occurs (
I.

[Invention No. 41] This invention was made to eliminate the drawbacks of the conventional ones as described above, and in this invention, a time division switching function is added to the access arbitration circuit so that one system can access the system. If the time width is restricted to a certain time width, and data transfer does not end within that time width, data transfer is resumed after waiting until the next cycle of the time width that the system can access. This eliminates the drawback that the system stops while accessing dual port memory 0, making access from the other system impossible.

It also supports an 8-bit system and pool memory (DL).
A 16-bit bidirectional latch buffer is added between the 8-bit system and this latch buffer, and input/output to the dual port memory 'J (1)) is performed in 16-bit units from this launch buffer. The input/output was done in 8-bit units to prevent transmission failures due to soft errors. In other words, when writing from an 8-bit system to memory (2), the first 8 bits are simply written to the latch buffer, and when writing 8 bits of consecutive addresses, they are written to the latch buffer. At the same time, I decided to fill the 16 bits of the launch buffer into memory 0 as one word. Also, when the 8-bit system reads the memo IJ [D], when reading the first 8 bits, extract the 16-bit data including the following 8 bits and set it in the latch bar sofa. - When 8 bits of these are read to the 8-bit system side and the 8-bit system reads the next 8 bits, memory 0 is read out.
) The remaining 8 bits are read from the latch buffer without accessing the latch buffer.

[Practice of the invention y1”] Embodiments of the present invention will now be described with regard to mouth opening.

FIG. 2 is a block diagram showing one example of the addition of this invention, in which the same reference numerals as in FIG. 1 indicate the same or corresponding parts, E is a clock generator, and F is a bidirectional 16-bit latch buffer. . Fig. 3 is an operation time diagram showing the progress of the output voltage from the clock generator), where the horizontal axis is time t, To is one cycle of switching, and TA is valid access for the 16-bit system. The time TB is the time at which access of the 8-bit system is valid, and the output logic of the clock generator (E) is, for example, rlJ during T and ``0'' during T.

A B TA and Tn switching is T1. T2. i'3. T4
It is cycled and repeated periodically as shown in . The access arbiter (C) is switched by K (J) as shown in Figure 3 by the output of the clock generator (fc), but this switching can be done at any time, and the access arbiter +C) is used for 16-bit systems. Only when there is a conflict between an access request from the 8-bit system and an access request from the 8-bit system, the third
The switching shown in the figure may also be performed.

Next, the 16-bit data is transferred from the 16-bit system to 8
The operation of the apparatus shown in FIG. 2 will be explained by taking as an example the case of transferring data to a bit system.

1 during the time span immediately before the time span shown as T1 in Figure 3.
Assuming that there is an access request from a 6-bit system, this access request is waited until the time interval shown by T□ arrives, and when this time interval comes and the access from the 16-bit system becomes valid, the 16-bit system bus is freed. Memo 'J (D) connected to Pu'al port Memo IJ (D) and designated by the address signal sent on bus (A)
) The 16-bit data (temporarily data W16) sent to the address in ) is written. Memo 'J (D) is sent from the 8-bit system during the time period shown by T□.
Assuming that there is an access request to
connected to. In an 8-bit system, the lower 8 bits of data W16 (temporarily set as data 'W8L', and similarly the upper 8 bits are
When the address signal to read the bit (data W8H) is sent on the bus tBl, the data stored in the address specified by this address signal and the next address from the memory (g), that is, WaL+W8H =
Wl a to read out, 16 htl.
ii"), and W8L is fetched by the 8-bit system. Next, the 8-bit system issues an access request to read W8H, but at this time the time width shown by T3 has been reached. If rJ' - this access request is allowed after waiting for the time period shown by η, in this case access to the pool port memory (Dl is not required), but the 16-bit latch buffer (from F+ to W8H is connected to the 8-bit system If you read it, it will be read.

Therefore, there is no problem in writing new data from the 16-bit system to the data W16 position during the time width indicated by T3.

Dual port memory (I) from 8-bit system
When convolving, the first data WsL is the lower 8 bits of the 16-bit reset buffer (li'))
, when writing buffer y (WB of Fl, WB
Write L+WB H=W, 6 to Pual port memory.

Therefore, it is impossible that only the first half of 8 bits of 16-bit data are written and then read by a 16-bit system, resulting in a soft error.

Note that in the above embodiment, data transmission between a 16-bit system and an 8-bit system was explained;
The data word structure in one system may be 32 bits or 64 bits, and there is no limit to the number of bits.

〔Effect of the invention〕

According to this invention, as shown in FIG.
In data transmission between two systems, transmission failures due to software errors can be prevented.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a conventional device, FIG. 2 is a block diagram showing an embodiment of the present invention, and FIG. 3 is an operation time diagram showing the progress of the output voltage from the clock generator in FIG. 2. It is. A: 16-bit system bus, B: 8-bit system bus, C: access arbitration circuit, D: dual port memory, E: clock generator. F...
16 bits later. Note that the same reference numerals in each figure indicate the same or corresponding parts. Agent Masuo Oiwa Figure 1 Figure 2 Figure 3

Claims (1)

[Claims] In a dual-port memory device having a dual-port memory that can be accessed from both a 16-bit system and an 8-bit system, access requests via a 16-bit system bus and access requests via an 8-bit system bus are processed. an access arbitration circuit that accepts access requests and controls the connection between the dual port memory and either the 16-bit system bus or the 8-bit system bus; During a period when the arbiter circuit receives an access request from the 16-bit system and an access request from the 8-bit system at the same time, the iαH node system bus and the A clock generator controls the switching of the 8-bit system bus to connect it to the dual-port memory, and a pair of 8-bit signals is used to input and output data from the 8-bit system bus to the dual port memory. A dual port memory device comprising: a 1ifN 16-bit latch buffer for temporarily storing input/output data for the 8-bit system bus so as to be input/output to the dual port memory as 16-bit signals constituting the 8-bit system bus.