JPH039453A - Data transfer controller - Google Patents

Abstract

PURPOSE:To transfer the data of one word started from an odd numbered address by controlling whether an address obtained by adding '1' to an address on an address bus is outputted to an even numbered address storage means or is outputted as it is. CONSTITUTION:A DMA controller 2 is activated by a CPU 1, and in the case of executing DMA transfer between plural memories, a source address and a destination address are set up by the CPU 1. In this case, an auxiliary address bus 7 for transmitting an output from an adder 6 for adding '1' to an address on the address bus 5 is connected to an even numbered memory block 3 to supply an address signal to the block 3. In the case of transferring the data of one word starting from an odd numbered address, the address obtained by adding '1' to the address on the address bus by the adding means 6 is supplied to the even numbered address storing means 3 by the control of an addition control circuit 9. Consequently, the data of one word starting from an odd numbered address can be transferred.

Description

Detailed Description of the Invention (a) Industrial Application Field The present invention relates to a data transfer control device that directly transfers data between peripheral devices such as storage devices and input/output devices connected to the same bus. This relates to data transfer in word units.

(B) Conventional technology Information processing devices such as computers have traditionally transferred data directly between multiple (or single) peripheral devices connected to the same bus without the intervention of the CPU.
M A (Direct Memory Access
) transfer is taking place. DMA transfer is controlled by a DMA controller (for example, μPD71071 manufactured by NEC@).

Now, normally the data bus is 16 bits (2 bytes, or 1
As shown in FIG. 2, the memory is divided into an even address memory block (21) and an odd address memory block (22). Address signals of A and ~An bits (addresses are A0 to An bits) are input to both of these memory blocks (21) and (22), and the even address memory block (21)
Bit A of the address is applied to the memory blocks (22) at odd addresses, and a BHE signal indicating validity of the upper 8 bits of the data bus is applied to the memory blocks (22) at odd addresses, and each memory block is accessed.

Therefore, when accessing data in word units to memory, the address signals input to each memory block are A, ~An bits, so (address 01 address 1), (address 2, address 3), etc. - A combination of (address 2m, address 2m+1) (m is a natural number), that is, words starting from even addresses are accessed.

Therefore, in a general DMA controller, when transferring data in word units between memories (hereinafter simply referred to as word transfer), data for one word starting from an even address is transferred from an even address to an even address. Transfers to 1-word addresses starting from even addresses) are supported.

(c) Problems to be solved by the invention Therefore, it is possible to convert one word from an odd number address to one word from an even number address, or one word from an even number address.
When performing DMA transfer of one word from an odd numbered address, the DMA transfer had to be performed in units of nodes.

Therefore, when transferring one word of data in bytes between an odd number address and an even number address (even number address - odd number address), it takes twice as long as a word transfer between an even number address and an even number address. Efficient transfer was not possible.

The present invention has been made in view of the above problems, and provides a data transfer control device capable of word transfer of one word of data starting from an odd numbered address.

(d) Means for Solving the Problems The present invention provides an even address storage means for an even address storage area and an odd address storage means for an odd address storage area, which are connected to the same address node. a data transfer control device for transferring data, the adding means being connected between the address bus and the even address storage means and outputting an address obtained by adding 1 to the address on the address bus to the even address storage means; The apparatus includes an addition control means for controlling whether the means outputs the address on the address bus as it is or outputs an address added by 1.

(E) Operation When one word of data starting from an odd address is transferred, the addition control means adds 1 to the address on the address bus and supplies the address to the even address storage means. As a result, one word worth of addresses starting from the odd address is accessed, making word transfer possible.

(f) Embodiment FIG. 1 is a schematic diagram of an embodiment of the present invention. (1)
is the CPU that normally serves as the bus mask for this system, (2)
is the bus mask during DMA transfer and controls the transfer.
This is the A controller. DMA controller (2) is C
When activated by PU(1) and performing DMA transfer between memories, a source address and a destination address are set by CPU(1).

(3) is an even number memory block, (4
) is an odd memory block as an odd address storage means to which an odd address storage area is allocated.

(5) is an address bus that transmits address signals of bits A, ~An, and address signals from CPU (1) or DMA controller (2) are sent to even memory blocks (3) by this address bus (5). '? It is supplied to the odd memory block (4). Although not shown, the upper 8 bits (D) of the data bus are added to the even-numbered memory block (3) with address A and bit.

~D1. ) is valid for the odd block (4
) from a CPU (1) and a DMA controller (2).

The address bus (5) is not directly connected to the even memory block (3), but is connected to the adder circuit (6) via an adder circuit (6) that adds 1 to the address on the address bus (5). An auxiliary address bus (7) is connected which conveys the output from the even numbered memory blocks (3) and supplies address signals to the even numbered memory blocks (3).

(8) is a signal 1 when the CPU (1) starts a DMA transfer by the DMA controller (2), if the set source address is a word transfer with an odd number address, and the signal 1 is sent if the set destination address is a word transfer with an odd number address. If so, it is a control boat that activates signal 2.

(9) is an addition control that receives signals from the control port (8) and the DMA controller (2) and controls whether or not to add 1 to the address on the address bus (5) in the addition circuit (6). It is a circuit.

(10) consists of four bidirectional buffers (11) (12) (1
3) (14), is an exchange circuit for exchanging data on the upper 8-bit data bus (15) and the lower 8-bit data bus (16). ).

Now, when performing DMA transfer, the CPU (1) sets appropriate source and destination addresses and other necessary parameters in the DMA controller (2). In this case, in word transfer, if any of the set addresses is an odd address 2m+1, an even address of 2m is generated in the DMA controller (2).

Next, when the DMA transfer to be performed is a word transfer and is one word from an odd address, the CPU (1) sends a signal 1 from the control port (8) when the source address is an odd number, and when the destination address is an odd number. Activate signal 2 and output it.

Note that even if the DMA transfer is a word transfer, if the transfer is from an even address to an even address, the control port (8) will not output signal 1 or signal 2 in an active state.

After that, the CPU (1) issues a DMA transfer request to the DMA controller (2), and the DMA controller (2)
) puts the CPU (1) into a hold state in response to the request.

Then, DMA transfer is performed by the DMA controller (2).

Now, in a memory-to-memory DMA transfer, one word of data from an even address is transferred to one word of data from an odd address.
The case of word-to-word transfer will be explained.

Following the bus mask, the DMA controller (2) first reads one word of data from the source address from the memory blocks (3) and (4).

At this time, since the source address is an even number, signal 1 is not active and the DMA controller (2)
Even if the memory read signal MRD from the adder circuit (9) and the address enable signal AEN indicating that the address is valid are input to the adder control circuit (9), the adder circuit (6) is sent from the adder control circuit (9) to the adder circuit (6). ), the control signal 3 that causes 1 to be added to the address does not become active.

Therefore, the address on the address bus (5) is directly passed through the auxiliary address bus (7) to the even memory block (3).
), the address on the address bus (5) is also input to the odd memory block (4), and one word of data from the even address is read onto the data bus.

Note that when the address is supplied to each memory block, the A0 bit of the address is supplied to the even numbered memory block (3), and the BHE signal is supplied to the odd numbered memory block (4).
It is input from the controller (2).

In the switching circuit (10), since the control signal 3 from the addition control circuit (9) is not in the active state, output from the two bidirectional buffers (11) and (14) is possible, and the even memory block ( The lower 8 bits of data read from the data bus (16) and the bidirectional buffer (14) are input to the data bits D, ~D, of the DMA controller (3), and are sent to the odd memory block (3).
The upper 8 bits and 7 bits of data read from 4) are passed through the data bus (15) and the bidirectional connector (11) to bits D, ~D of the data of the DMA controller (2).
14.

Next, the DMA controller (2) writes one word of read data into one word starting from an odd address.

If the odd address specified by the CPU (1) as the destination address is 2m+1 (the addresses of one word are 2m+1 and 2m+2), the DMA controller (2) specifies 2 as the destination address.
The address of m is output to address nox (5).

Since the signal 2 of the control port (8) is in the active state, the addition control circuit (9) makes the control signal 3 active when the signal AEN or the memory write signal MW is input from the DMA controller (2). .

Then, the adder circuit (6) adds 1 to the address on the address node (5) (i.e., 2(m+1)=2m
+2) to the auxiliary address bus (7).

As before, even memory block (3) has address A.
, the BHE signal is input to the odd memory block (4), and address 2m+1 is accessed in the odd memory block (4) and address 2m+2 is accessed in the even memory block (3).

If the adder circuit (6) does not add 1, the address 2m on the address bus (5) will access address 2m in the even memory block (3) and address 2m+1 in the odd memory block (4). Therefore, one word is not accessed from an odd address.

When the control signal 3 from the addition control circuit (9) becomes active, the switching circuit (10) can output from the two bidirectional buffers (12) and (13), and the DMA controller (2) The upper 8 bits of data output from
13) is output to the data node (15).

The data on the data bus (15) is then transferred to the data bus (16) at address 2m+1 of the odd memory block (4).
) is address 2 of even memory block (3)
m+2, and the word transfer from the even address to the odd address is completed.

Similarly, when word transfer is performed from an odd address to an even address or from an odd address to an odd address, when accessing one word from an odd address, the adder circuit (6) transfers data on the address bus (5). 1 is added to the address, and one word from the odd address is accessed.

(g) Effects of the Invention As is clear from the above description, the present invention enables one word access starting from an odd address by providing an adder circuit that adds 1 to an address given to an even memory block.

Thus, it is possible to perform word transfer in one word starting from an odd-numbered address, allowing efficient MA transfer and speeding up the processing.

[Brief explanation of the drawing]

FIG. 1 is a schematic diagram of an embodiment of the present invention, and FIG. 2 is a diagram showing a memory configuration. (1) CPU, (2) DMA controller, (3) Even memory block (even address storage means), (4) Odd memory block (odd address storage means) (5 )...address bus, (6)...
Adder circuit, (8)...Control boat, (9)...
...Addition control circuit, (10)...Switching circuit, (15X
16)...Data bus.

Claims (2)

[Claims] (1) In a data transfer control device in which an even address storage means in a storage area with an even address and an odd address storage means in a storage area with an odd address are connected to the same address bus, and data is transferred in these storage means, the address an addition means connected between the bus and the even address storage means for outputting an address obtained by adding 1 to the address on the address bus to the even address storage means; and whether the addition means outputs the address on the address bus as is or adds 1 1. A data transfer control device comprising: addition control means for controlling whether or not the address is output. (2) It is characterized by comprising an exchanging means controlled by the addition control means and exchanging the data on the data bus connected to the even address storage means and the data on the data bus connected to the odd address storage means. The data transfer control device according to claim 1.