JPS60189052A - Memory access controller - Google Patents

Abstract

PURPOSE:To attain both two-byte transfer and one-byte data transfer even when memory is extended by providing a bus switching device which accesses the memory, word by word, and, byte by byte, selectively at any time. CONSTITUTION:When one word (two bytes) is transferred from an eight-bit input/output port 7 to the memory 5, an upper data strobe signal becomes active on the start of the DMA transfer cycle of direct memory access (DMA) 2. Consequently, memory 51 is accessed and further a high-order byte indication signal is also active, the bus switching device 4 operates to connect buses 23 and 24, and 21. Then, data from the port 7 is stored in the high-order byte side memory 51 through a signal line 30. Data of next two bytes is transferred in the same sequence to low-order side byte memory 52 and stored in the low-order byte side memory 52 through a signal line 31 at this time, so the bus switching device 4 does not operate. Extended memory 6 is exactly the same.

Description

DETAILED DESCRIPTION OF THE INVENTION (Technical Field) The present invention relates to a memory access control device, and more particularly to a memory access control device that selectively accesses memory at any time in word units or byte units.

(Prior technology) By configuring an input/output control port with a bus width of 1 byte and an input/output control port with a bus width of 2 bytes, both 1-byte data transfer and 2-byte data transfer are possible. For example, there is a technique shown in Japanese Patent Publication No. 58-46727.The content of this technique is to arrange a bus switching device between the memory and the main bus, and to Is it a 2-byte transfer?
The connection method between the memory and the main bus is controlled depending on whether the transfer is on the upper byte side of a 1-byte transfer or the lower byte side of a 1-byte transfer. However, it is always possible to make it possible even with 1-byte transfer (byte-level memory access). However, in this case, if you try to add more memory modules, you will have to add bus switching equipment accordingly. (Objective) The purpose of the present invention is to eliminate the above-mentioned drawbacks and to prevent the sound system from becoming dog-shaped even when memory modules are added. To provide a memory access control device that performs either 2-byte data transfer or 1-byte data transfer.

(Embodiment) The present invention provides a bus switching device between a control circuit fyB consisting of a central processing unit or the like and a main bus, in which the control circuit section selectively accesses memory at any time, whether in word order or byte order. Arranged and configured.

The present invention (for example, the central processing unit J-! I!
In a data processing system in which a rear port and a memory capable of word specification and byte specification are connected to a main bus, the central processing unit and the direct memory access control signal selectively function, and the memory on the back side of the bus control signal Referring to at least one of a signal instructing a first memory portion consisting of one h byte of a memory capable of both word specification and byte specification and a signal indicating a second memory portion consisting of lower bytes; Furthermore, each of the central processing unit and the direct memory access controller Q, j+ is placed between the control circuit unit and the main bus to control the memory in units of words or bytes.
It consists of a bus switching device that selectively accesses the bus.

FIG. 1 is a block diagram schematically showing the basics of an embodiment of the present invention.

1 (ri) is a 16-bit main central processing unit (hereinafter abbreviated as CPv), and a direct memory access (hereinafter abbreviated as DMA) control circuit 2 (is a main bus 2', 22K connected memory 5, Memory 6 (added memory), 8-bit memory card door, 16-bit input/output board 8, which is a circuit for controlling DMA transfer between each other, and bus switching device 4 (d, internal bus 2
3.24 and the main buses 21 and 22. In addition, 51,611 dimensions, ``memory organized in nodes (2 bytes)!, i, memory consisting of the upper bytes of 6, 52.62 (ri+H from the lower bytes) , Q is a memory.

Next, the operation of the present invention will be explained using FIG.

Now, 2 bytes (1 word) from the 8-bit input/output capo door
The case where the data is transferred to the memory 5 will be explained. First, each signal that will be used in the following explanation will be explained.

DREQ (DMA [transmission request 1 word)] When the data to be sent is ready for input/output port door or 8, it is sent from the port to DMA control, 1 line 2. It is.

6 A CK (DMA transfer permission town signal) DR
Permission number 1u for EQ, DMA control circuit 2
It can be sent to more ports. And this is the boat
1, it takes K to send the data.

1. DTACK (data transfer permission signal) This is a signal sent from the memory to the DifA control circuit 2 during the DMA transfer cycle, and is used to synchronize according to the speed of the memory.

■ AS (Address Strobe Signal) Indicates that the 1-high address indicated by address bus lines A1 to A23 (not shown) has been determined. (Φ LDS (Low Byte Data Strobe Signal)) This indicates that the memory 52.62 of the lower A rule byte is being accessed.

”/1) UDS (Upper data stroke 1 word)
Upper byte memory 51. Indicates that file 1 is being accessed.

■ HIBYTF4 upper byte instruction signal) This is the number that is output from the DMA control circuit 2, and in DMA transfer from the port or to the boat, the upper 11 of the memory
This signal indicates the transfer of data corresponding to the ′ξ byte side.

(8) R/W (Lard write signal) Indicates whether the main bus is in a read state or a write state.
Indicates whether it is used in i, 14.

The above signals (are omitted in No. 11:' for the sake of brevity).

Then, when the data chapter (N) is completed, the DMA transfer from the 8-bit input/output port door and the request signal DREQ are input to the DMA control circuit 2.Then, the DMA fill control circuit 2 acquires the main bus from the main CPU 1. A request signal (not shown) is output, and the main buses 21 and 22 are connected to A (μ).Then, the DMA control wholesale circuit 2 outputs the address bus lines A, to A23, and upper data stroke read write signal R/W ( This pigeon coop is in light condition).

Upper byte instruction signal 1-fIBYTE is output, and DMA transfer permission 1 DACK is returned to the 8-bit input/output coupler for four cycles of hDMA DMA rotation.

At this time, since the upper data strobe signal 'U D S is active, the memory 51 is accessed, and since the upper byte instruction signal f (IBYTE is also active, the bus switching device 4 is activated and the internal
Buses 23, 24 and main bus 21 are connected.

Also, 11 to the memory by the read/write signal R/W.
8-bit input/output capo.
The data +d from the door is stored in the upper byte side memory 1J51 following the path indicated by the dotted line 30 in FIG. At this time, in order to synchronize according to the speed of the memory, the data transfer permission signal DTACK is sent from the memory to the DMA
The signal is sent to the control circuit 2.

The next 2nd byte data transfer follows a similar sequence, but in this case, unlike the 1st byte data that was previously transferred, it is transferred to the lower byte memory 52, so the upper data strobe signal uDs is active. ((not,
Instead, the low byte data strobe signal LDS becomes active, and the high byte instruction signal HI BYT
E is also not active. Therefore, the bus switching device 4 does not operate. In this case, the data from the 8-bit input/output port door passes through the path shown by the dotted line 31 in FIG. Stored.

At this time, the bus switching device 4 does not need to operate.

The above explains the transfer of data (7) from the 8-bit input/output coupler to the memory 5 (-, but the read/write signal R/W also changes when data is transferred from the memory 5 to the 8-bit input/output coupler in the opposite direction). Basically, the sequence is exactly the same.In addition, 16-bit input/output port 8 and memory 5
As is clear from FIG. 1, the data transfer between ir'i and ir'i is carried out using the main buses '2'''1 and 22 at the same time in black-marked words.

One thing about this point is that it happened in January.

Father, is that more? 9. Although the description above concerns reading and writing to the memory 5, it is natural that the exact same sequence applies to the expanded A-memory 6 as well. Also, although the present invention has been explained using the DIIIA transfer as an example, the present invention has been explained using the DIIIA transfer as an example.
Even in a dual processor system consisting of U3, the bus switching device 4 allows each CPU to share the same i.
(Effects) As explained above, the present invention provides a bus between the control circuit section consisting of the central processing unit and the direct memory access control device and the main bus. Since it has a configuration equipped with a switching device, even if memory is expanded to 7, memory access in word units and memory access in byte units can be selectively realized at any time without adding any other hardware.
This has the effect of making the system more compact.

[Brief explanation of drawings]

FIG. 1 is a strategic block diagram showing one embodiment of the present invention. 1...16-bit main CPU 2...DMA control circuit 6...8-bit slave CPU4...
Bus switching device 5.6... Memory 7... 8-bit input/output boat 8... 16-bit input/output boat or more Agent Patent Attorney Mogami

Claims (1)

[Claims] ・Central part 8! It is arranged between the main bus and a control circuit section consisting of a direct memory access control device 4 and a direct memory access control device 4, and the control circuit section selects one of a word unit and a byte unit of the memory at 1'. A memory access control device comprising a bus switching device for access.