JPS62276655A - Dma transfer system - Google Patents

Abstract

PURPOSE:To improve a transfer speed and to efficiently and surely write data in a storage device by controlling data transfer and writing/reading data in/from the memory device in each word and byte. CONSTITUTION:The DMA transfer between a transfer device 1 for transferring data in each byte and the storage device having data width of each word consisting of plural bytes is controlled in each word by using a DMA controller 3. A bus switching control means 5 counts up a strobe signal obtained from the device 1 and controls a bus switching circuit 4 for switching a data bus from the device 1 based on the output of the device 1. On the other hand, a strobe control means 6 controls a data strobe signal of the device 2 based on a previously set flag. Consequently, data transfer to the device 2 and data writing into the device 2 can be executed by either one format, i.e. word or byte.

Description

[Detailed Description of the Invention] 3. Detailed Description of the Invention [Overview] DM that controls data transfer to and from memory in word units
Between the A control device and the device that transfers data in bytes, byte transfers are converted to word transfers and the memory strobe signal is controlled, thereby allowing transfers in both word/byte formats and data transfers to memory. It is possible to write.

[Industrial Field of Application] The present invention relates to DMA transfer between a transfer device that transfers data from an input/output device and a storage device, and particularly relates to transfer 'ATL' that transfers data in units of bytes and words consisting of multiple bytes. The present invention relates to a DMA transfer method between unit storage devices.

DMA is a method in which a transfer device directly accesses a main memory to perform reading and writing without using a central processing unit (hereinafter abbreviated as CPU), and is widely used in information processing devices.

The data bus of the transfer device is typically 8 bits wide, and the data width of the main memory is typically 16 or 32 bits.

Therefore, when a fractional hide occurs in the main memory in DMA, special processing is required, and the most efficient processing method is desired.

[Prior Art] DMA transfer between a transfer device that transfers data in units of hides and a storage device in units of words consisting of multiple bytes is as follows.
Traditionally, there were two types of clothing.

The first method, as shown in Figure (a), is a method in which the DMA transfer itself is a byte transfer in accordance with the device that transfers data in units of height, and the second method is shown in Figure (a). As shown in b), this is a method in which the byte data from the transfer device is switched between upper and lower order and transferred in units of words.

[Problems to be Solved by the Invention] According to the above-mentioned conventional DMA transfer method, the first method requires twice the transfer time, and the second method requires the data management unit on the storage device to be word-based. Therefore, when the first and last DMA transfers are fractional bytes, there is a risk that errors such as erasure or overwriting may occur.

The present invention aims to provide a new MA transfer method that solves these problems.

[Means for Solving the Problems] FIG. 1 shows a block diagram of the principle of the DMA transfer method of the present invention.

In FIG. 1, 1 is a transfer device that transfers data in byte units, 2 is a storage device of m words consisting of 2 bytes,
3 is a DMA control device that controls DMA transfer in units of words.

4 pretends to hold byte data, 2& of Buflo 7p
11 and a changeover switch, it is a bus switching circuit that converts a byte-width bus from the transfer device 1 into a word-width bus.

Reference numeral 5 denotes bus switching control means for counting strobe signals from the transfer device 1 and controlling the bus switching circuit 4.

Reference numeral 6 denotes a data strobe control means for controlling a data strobe signal to the storage device 2 using a preset flag.

Under the control of the bus switching control means 5, the bus switching circuit 4 can convert the byte width data from the transfer device 1 into word transfer, upper byte transfer, or lower byte transfer.

The data strobe system 411 means 4 controls the data strobe for each upper and lower hide of the storage device 2 using a flag set in advance.
It becomes possible to write in either word unit or hide unit format.

[Operation] By adopting the above configuration, it is possible to perform DMA transfer at high speed in units of words, and manage and write the beginning and/or end of DMA transfer in units of bytes.

[Example] The present invention will be explained in more detail with reference to the embodiment shown in FIGS. 2 and 3. FIG. 2 is a schematic diagram of one embodiment of the present invention.

In the figure, 1 is a transfer device that transfers data in byte units, 2 is a storage device in word units consisting of 2 bytes, and 3 is a DMA control device that controls DMA transfer in word units.

41 and 42 are flip-flops for latching data bytes from the transfer device 1;
42 is latched to write to the upper byte of storage device 2, and 42 is latched to write to the lower byte of storage device 2. A multiplexer 43 (hereinafter abbreviated as M P X) switches data from the transfer device 1 to either of the flip-flops 41 and 42 .

51 is a 1-bit counter that counts the strophe words B from the transfer device 1 and outputs the current result data as the MPX switching signal upper latch signal E and lower latch signal F.

61 is a flag 1 latch, 62 is a flag 2 latch, and 63 and 64 are AND gates that control a data strobe signal to the storage device 2.

Flag 1 is a flag for masking the upper data strobe signal G, is set in advance by a program, and is reset at the end of the first data strobe signal (this part is not shown).

Flag 2 is a flag for masking the lower data strobe signal I, and is set by the logical product of the transfer request signal A, the strobe signal B from the transfer device, the transfer end signal C, and the MPX switching signal. Reset at the end of the strobe signal (at this point, the address signal and data strobe signal to the storage device 2 are output.

The data strobe signal from the DMA control device 3 is AN
The D gates 63 and 64 divide the memory device 2 into an upper strobe signal G and a lower strobe signal H. The upper strobe signal G is masked by the AND gate 63 when flag 1 is "1", and the lower strobe signal H is masked by the flag 1. 2 is masked by AND gate 64 when it is "1".

Counter 51 starts counting in response to transfer request signal A, but when flag 1 is not set, MPX
When the MPX 43 starts from the upper position and flag 1 is set, the MPX 43 is preset to start from the lower position.

FIG. 3 is a timing chart showing the timing of each signal in the embodiment of the present invention.

FIG. 3 shows an example in which a 6-byte DMA transfer is performed, the first byte is written in the lower byte of the storage device, the 2nd to 5th bytes are written in words, and the 7th byte is written in the upper byte.

(1) In order to write the first byte from the lower byte, flag 1 is set by the program.

Therefore, when the transfer request signal A rises, the counter 51 starts counting the strobe signal B of the transfer device from the lower side (L) of the MPX 43.

(2) The first byte is latched to the lower side and the byte is transferred. The first address and strobe signal are output from the DMA control device, but the upper data strobe signal is masked by flag 1, and only the lower byte is written into the storage device 2. Flag 1 is reset at the end of the data strobe signal.

(3) The counter 51 is inverted by the next strobe signal B from the transfer device 1, the MPX 43 is switched to the upper side (U), the second byte is latched to the upper side, and the counter 51 is inverted by the next strobe signal B. is inverted again, the third byte is latched to the lower order, and the word is transferred. Word writing is performed by the next address and data strobe signal from the DMA controller 3. Similarly, the fourth and fifth bytes are word-transferred and word-written.

(4) Due to the sixth strobe signal B from the transfer device 1, the MPX+jJ conversion signal becomes a car signal (U), the sixth byte is latched to the upper side, and the byte is transferred in response to the transfer end signal C. As shown by the small circle in the figure, flag 2 is set to The lower data strobe signal H is masked, and the sixth byte is written into the upper byte. Flag 2 is reset at the end of its data strobe signal H.

[Effects of the Invention] As explained above, according to the present invention, data transfer and writing/reading to and from a storage device can be managed in word units and byte units, improving transfer speed and improving storage efficiency. This makes it possible to write to the device efficiently and reliably, and has great practical effects.

[Brief explanation of drawings]

FIG. 1 is a block diagram of the principle of the present invention, FIG. 2 is a block diagram of an embodiment of the present invention, FIG. 3 is a timing chart of the embodiment of the present invention, and FIG. 4 is a block diagram of a conventional example. In the drawings, 1 is a transfer device, 2 is a storage device, 3 is a DMA control device, 4 is a bus switching circuit, 5 is a bus switching control means, 6 is a data strobe control means, 41 and 42 are flip-flops, and 43 is a multiplexer ( MPX), 51 is a counter, 6L, 62 is a flag latch, and 63 and 64 are AND gates, respectively. The principle block diagram of the present invention is shown in Fig. 1. The block diagram of the actual product 7111 of the present invention is shown in Fig. 2. The timing chart of the actual product 5 of the present invention is shown in Fig. 3.

Claims (1)

[Claims] A DMA that controls DMA transfer in word units between a transfer device (1) that transfers data in byte units and a storage device (2) that has a data width in word units consisting of multiple bytes.
In DMA transfer performed using the control device (3), a bus switching circuit (4) that counts strobe signals from the transfer device (1) and switches the data bus from the transfer device (1) based on the output. A bus switching control means (5) for controlling a data strobe signal to the storage device (2) according to a preset flag, and a strobe control means (6) for controlling a data strobe signal to the storage device (2). A DMA transfer method characterized in that writing to a storage device (2) is possible in either word or byte format.