JPH03204753A - Dma controller - Google Patents

Abstract

PURPOSE:To decrease the cycle for a DMA transfer between memories and to operate the whole system at a high speed by providing independently a control circuit of a read signal, a write signal and an address signal for the memory of a transfer origin and the memory of a transfer destination, respectively. CONSTITUTION:An address signal for indicating a transfer origin is outputted to an address bus 41 from a DMA controller 11, and simultaneously, an address signal for indicating a transfer destination is outputted to an address bus 42 from the DMA controller 11. Also, a read signal 51 outputted from the DMA controller 11 becomes active, the contents of a memory 21 of the transfer origin are outputted to a data bus 30, and also, a write signal 61 outputted from the DMA controller 11 becomes active, and the contents of the memory 21 being the transfer origin are written in a memory 22 being the transfer destination. In such a way, the transfer of data to the memory 22 being the transfer destination from the memory 21 being the transfer origin is completed in one cycle.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a DMA control device, and in particular, to
The present invention relates to a DMA controller that performs MA transfer.

[Conventional technology]

The case of DMA transfer between memories as a conventional DMA control device will be explained using the block diagram of FIG. 5 and the timing diagram of FIG. 6.

In FIG. 5, it is composed of a DAM controller 10, a memory 20, a data bus 30, and an address bus 40. A signal 60 for reading out is used.

First, an address signal pointing to the transfer source is output from the DMA controller 10 to the address bus 40, a read signal 50 output from the DMA controller 10 becomes active, and the contents of the memory 20 of the transfer source are input to the DAM controller 10.

Subsequently, an address signal pointing to the transfer destination is output from the DMA controller 10 to the address bus 40, a write signal 60 output from the DMA controller 10 becomes active, and the data output from the DMA controller is transferred to the memory 20 of the transfer destination. will be written to.

[Problem to be solved by the invention]

In this way, DMA transfer between memories in a conventional DMA controller takes a total of two cycles: a read cycle from the memory 2o to the DMA controller 10, and a write cycle from the DMA controller to the memory, which takes time for system operation. There is a problem.

An object of the present invention is to solve such problems and to provide control circuits for read signals, write signals, and address signals independently for the transfer source memory and the transfer destination memory, thereby improving DAM transfer. It is an object of the present invention to provide a DMA control device that reduces cycles and realizes speeding up of the entire system.

[Means for solving and resolving issues]

The configuration of the present invention is that in a DMA control device that controls DMA transfer between a plurality of memories, a DMA control device that controls read signals, write signals, and address signals of each of the memories is provided.
The MA controller is characterized in that it has independent connection lines for read signals, write signals, and address signals between a transfer source memory and at least one transfer destination memory.

〔Example〕

Next, the present invention will be explained using the drawings.

FIG. 1 is a block diagram of one embodiment of the present invention. In this figure, a DMA controller 11, a memory 21 .
22, a data bus 30, and address buses 41 and 42 for the memory 21.22, and a signal 51.52 for writing data on the data bus 30 to the memory 21.22.
and signals 61.62 for reading data from memory 21.22 onto data bus 30 are used.

Next, the operation of this DMA controller will be explained. FIG. 2 is a timing chart of FIG. 1.

First, an address signal indicating the transfer source is output from the DMA controller 11 to the address bus 41, and at the same time an address signal indicating the transfer destination is output from the DMA controller 11 to the address bus 42.

Furthermore, the read signal 51 output from the DMA controller 11 becomes active, and the contents of the transfer source memory 21 are output to the data bus 30, and the write signal 61 output from the DMA controller 11 becomes active, and the transfer is completed. The contents of the source memory 21 are written to the transfer destination memory 22.

In this way, data transfer from the memory 21, which is the transfer source, to the memory 22, which is the transfer destination, is completed in one cycle. FIG. 2 shows a case where such MA transfer cycles are repeated twice.

Note that although the above shows DMA transfer from memory 21 to memory 22, DMA transfer from memory 22 to memory 21
The same applies to transfer.

FIG. 3 is a block diagram of a second embodiment of the present invention, and FIG. 4 is a timing chart of FIG. 3. In FIG. 3, a DMA controller 12, memories 21 to 23, a data bus 30, and an address bus 41 for memories 21 to 23 are shown.
-43, signals 51-53 for writing data on the data bus 30 to the memories 21-23, and signals 51-53 for writing data on the data bus 30 to the memories 21-23;
Signal 61 for reading data from ~23 to data bus 30
~63 are used.

Next, this DMA controller will be explained. Here, it is assumed that DMA transfer is performed from the memory 21, which is the transfer source, to the memories 22 and 23, which are the transfer destination.

First, an address signal indicating the transfer source is output from the DMA controller 12 to the address bus 41, and at the same time, an address signal indicating the transfer destination is output from the DMA controller 12 to the address buses 42, 43. Further, the read signal 51 output from the DMA controller 12 becomes active, the contents of the transfer source memory 21 are output to the data bus 30, and the write signals 62 and 63 output from the DMA controller 12 become active. , the contents of the transfer source memory 21 are transferred to the transfer destination memory 22.23.
will be written to.

In this way, this embodiment is effective when transferring the same data to two destinations.

Although the case where there are two transfer destinations is shown here, the same applies to the case where there are three or more destinations.

〔Effect of the invention〕

As explained above, the present invention has independent control circuits for the read signal, write signal, and address signal for the transfer source memory and the transfer destination memory, thereby controlling the cycle of DMA transfer between memories. This has the effect of increasing the speed of the entire system.

Data read signal, 60.61-63... Data write signal.

Claims (1)

[Claims] DMA that controls DMA transfer between multiple memories
In the control device, a DMA controller that controls read signals, write signals, and address signals of each memory transmits these read signals, write signals, and address signals between a transfer source memory and at least one transfer destination memory. A DMA control device characterized in that it has independent connection lines for address signals.