JPH02132543A - Information processor - Google Patents

Abstract

PURPOSE:To realize the transfer of data among the central processing circuits without affecting the process of each central processing circuit by transferring the contents of data on a writing action area received from the central processing circuits set opposite to each other within a dual port memory to the same address area of another dual port memory. CONSTITUTION:When a central processing circuit 1 transfers data to other central processing circuits 2 and 3, the data are written into the read/write area in a dual port memory 10. The dual port memories 10 - 30 are connected in common to each other via an external address bus 102 and an external data bus 101. Then the data are transferred with the external read control signals 113 - 133 and the external write control signals 114 - 134 from the data transfer control circuit 100. As a result, the circuits 1 - 3 own the same data and each of these circuits requires no special process for transfer of the data. Thus it is possible to minimize the influence of the transfer of data to the normal process of each central processing circuit and to carry out the transfer of data among the central processing circuits.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an information processing device equipped with a plurality of central processing circuits, and particularly to a device for transferring data between central processing circuits.

[Conventional technology]

Generally, in an information processing device including a plurality of central processing circuits, it may be necessary to transfer data between the respective central processing circuits. In conventional information processing devices, data transfer methods between each central processing circuit include a method of transferring data while maintaining synchronization between the central processing circuits, that is, a method using handshake, and a method that transfers data between central processing circuits in a manner common to multiple central processing circuits. Methods such as using connected memory, that is, shared memory, are used. [Problems to be Solved by the Invention] However, in the conventional handshake-based data transfer method described above, it is necessary to synchronize the central processing circuits that transfer data, so each central processing circuit operates with independent synchronization and timing. In order to transfer data between central processing circuits, the time required for data transfer becomes a problem. That is, there is a problem in that data transfer affects the processing of the central processing circuit, and is not suitable for transferring a large amount of data.

Further, when a common memory commonly connected to a plurality of central processing circuits is used, each central processing circuit can access this memory independently, so that there is little influence on the processing of each central processing circuit. However, there is only one memory for data transfer for multiple central processing circuits, and only one central processing circuit can be accessed at any given moment. Therefore, while one central processing circuit is accessing the memory, other central processing circuits cannot access it, and a plurality of central processing circuits cannot transfer data at the same time. Therefore, when any central processing circuit is connected to that memory, other central processing circuits are forced to wait until that central processing circuit disconnects the memory.

An object of the present invention is to provide an information processing device that enables data transfer between central processing circuits without affecting the processing of each central processing circuit.

[Means to solve the problem]

In the information processing device of the present invention, a dual port memory is installed in each of the plurality of central processing circuits, one bus line of the dual port memory is connected to a bus line of the corresponding central processing circuit, and the dual port memory is connected to the bus line of the corresponding central processing circuit. The other bus line is commonly connected to a data transfer means for all dual port memories, and the data transfer means exclusively writes to the memory area of each dual port memory on the memory address map for each central processing circuit. means for allocating the data contents of a write operation area from a corresponding central processing circuit in one dual port memory to the same address area of another dual port memory, and performing the data transfer operation on all dual ports. It is provided with a means for periodically and repeatedly executing the process.

[Effect]

In the above configuration, when data is transferred between central processing circuits, each central processing circuit does not require special processing, and data can be transferred between central processing circuits without affecting the processing of each central processing circuit.

〔Example〕

Next, the present invention will be explained with reference to the drawings. FIG. 1 is a block diagram of main parts of an embodiment of an information processing apparatus of the present invention. In the figure, this information processing device includes three central processing units 1, 2, 3, dual port memories 10, 20, 30 connected to each central processing circuit 1, 2.3, and each dual port memory. It consists of a data transfer control circuit 100 that controls data transfer between 10.20.30. Each central processing circuit 1 to 3 and each dual port memory 10 to
One bus line of 30 is connected to the internal address bus 12, 2.
2.32, internal data paths 11, 21.31, and read/write control is performed using internal read control signals 13.23, 33 and internal write control signals 14, 24.34.

Further, the data transfer control circuit 100 and the other bus line of each of the dual port memories 10 to 30 are connected by an external address bus 102, and each of the dual port memories 10 to 30 are commonly connected by an external data path 101, Read control signals 113, 123, 133,
Read/write control is performed using external write control signals 114, 124, and 134.

FIG. 2 shows a memory map for the dual port memory of each central processing circuit 1 to 3 shown in FIG. In the figure, each read/write area can be freely read/written only by the central processing circuit connected to the corresponding dual-port memory.
This area can be written to, and each read area can only be read by the central processing circuit connected to the corresponding dual port memory.

FIG. 3 shows a timing chart of the data transfer cycle between the dual port memories 10 to 30 under the control of the data transfer control circuit 100, and the direction of data transfer in each area between the dual port memories.

The operation of data transfer between each central processing circuit in the information processing apparatus having the above configuration will be explained.

Each central processing circuit 1 to 3 and each dual port memo I-10
30, normal read/write operations between the central processing circuit and the memory are performed. Since all the central processing circuits operate in the same way, the central processing circuit 1 and the dual port memory 10 will be explained here as examples.

When the central processing circuit 1 transfers data to another central processing circuit 2.3, the data is written to the read/write area in the dual port memory 10. The respective dual port memories 10 to 30 are commonly connected by an external address bus 102 and an external data path 101, and external read control signals 113 to 1 from the data transfer control circuit 100 are connected in common.
33, data transfer operation is executed by external write control signals 114-134. A counter is built in the data transfer control circuit 100, and operates at a cycle shown in FIG. 3 to generate a data transfer cycle.

In the first phase of the data transfer cycle shown in FIG.
Data read from area (3) of dual port memory 10 is written to area I of dual port memories 20, 30. In the second phase, dual port memory 20
The data read from area (2) is written to area (2) of dual port memory 30.10. In the third phase, data read from area (2) of dual port memory 30 is written to area (2) of dual port memory 10.20. By periodically executing the operations from the first phase to the third phase, the dual port memories 10, 20 and 30 each hold the same contents.

Through the above operations, each of the central processing circuits 1 to 3 has the same data, and each central processing circuit does not have to perform any special processing for data transfer. Data transfer between each central processing circuit can be performed with minimal impact on processing.

〔Effect of the invention〕

As explained above, in order to transfer data between central processing circuits, the present invention does not require special processing in each central processing circuit, and the central processing circuit can transfer data between central processing circuits without affecting the processing of each central processing circuit. It becomes possible to transfer data between Therefore, there is a great effect on the effective use of the central processing circuit and the accompanying speeding up of information processing.

[Brief explanation of drawings]

FIG. 1 is a block diagram of main parts of an information processing device according to an embodiment of the present invention, FIG. 2 is a memory map diagram for dual port memory, and FIG. 3 is a diagram showing the timing of data transfer cycles between dual port memories and each FIG. 3 is a diagram showing the direction of data transfer in each area between port memories. 1-3...Central processing circuit, 10-30...Dual port memory, 13-33...Internal read control signal,
14-34... Internal write control signal, 100... Data transfer control circuit, 101... External data path, 10
2... Circuit address bus, 113-133... External read control signal, 114-134... External write control signal.

Claims (1)

[Claims] 1. In an information processing device comprising a plurality of central processing circuits and a data transfer means for mutually exchanging data between these central processing circuits, a dual port memory is installed in each of the central processing circuits, One bus line of this dual port memory is connected to the bus line of the corresponding central processing circuit, and the other bus line of the dual port memory is commonly connected to the data transfer means for all dual port memories, and the data transfer The means exclusively allocates a write operation to a memory area of each dual-port memory on a memory address map for each central processing circuit, and writes to a write operation area from a corresponding central processing circuit in one dual-port memory. What is claimed is: 1. An information processing device comprising: means for transferring the data contents of a dual port memory to the same address area of another dual port memory; and means for periodically repeating the data transfer operation for all dual ports.