JP4539481B2 - Multiprocessor system - Google Patents

Description

  The present invention relates to a multiprocessor system incorporated in an electronic device or an electronic system.

FIG. 10 is a block diagram showing a configuration of a conventional multiprocessor system. The multiprocessor system shown in FIG. 10 is a typical configuration example of an embedded multiprocessor system whose non-patent document 1 introduces a substantially similar configuration example.
The multiprocessor system shown in FIG. 10 includes n processors 1A to 1N each formed of a semiconductor chip, and an arithmetic processor which is a CPU (central processing unit) in the semiconductor chip inside each of the processors 1A to 1N. 11A to 11N, read / write internal memories 12A to 12N connected to these arithmetic processors 11A to 11N, and external bus IFs 13A to 13N, and local to each external bus IF (interface) 13A to 13N Bus drivers with enable 41A to 41N connected via buses 4A to 4N, local memories 42A to 42N such as E ² PROM (Electrically Erasable Programmable Read-Only Memory), and local I / O (Input / Output) 43A to 43N And bus drivers 41A to 41N with enable via the common bus 9. And shared memory 2 is continued, and is configured by a arbiter 3 connected to each external bus IF13A～13N.

In the following description, suffixes such as A to N attached after the numerical symbols of the constituent elements may be omitted.
More specifically, the external bus IFs 13A to 13N are interface controllers in the semiconductor chip that perform access control to the processors 1A to 1N, that is, the buses outside the semiconductor chip. The common bus 9 is a common bus used when the processors 1A to 1N access the shared memory 2.

The access arbitration device 3 performs arbitration that selects and permits only one access when there are a plurality of access requests. Access request signals 5A to 5N between the access arbitration device 3 and the processors 1A to 1N are signals requesting access permission, and the access permission signals 6A to 6N permit access to the access permission request signals 5A to 5N. Signal.
This multiprocessor system includes a shared memory 2 that is commonly used by n processors 1A to 1N, and each processor 1A to 1N writes or reads data at a predetermined promised address of the shared memory 2 to thereby store data. Sharing and exchanging.

  Since the shared memory 2 and the common bus 9 cannot be used simultaneously by the processors 1A to 1N, the access arbitration device 3 is provided. The processor (for example, 1A) that wants to access the shared memory 2 outputs the access request signal 5A as the first step, and receives the access permission signal 6A from the access arbitration device 3 in the second step. 41A is opened, and the shared memory 2 is read and written via the common bus 9.

When the processors 1A to 1N access the local memories 42A to 42N or local I / Os 43A to 43N used locally, the bus drivers with enable 41A to 41N are closed, and the common bus 9 is not affected.
When two or more access requests overlap at the same time in each of the processors 1A to 1N, the access arbitration device 3 selects one of the access requests according to the determined rule, and returns an access permission signal corresponding thereto. Thus, a plurality of processors do not use the common bus 9 and the shared memory 2 at the same time.
"4.3 Multiprocessor System / 4.3.3 Specific Example / (7) Process" of "Microprocessor Technology: Published May 10, 1979, First Edition, Editor and Publisher, The Institute of Electrical Engineers, Publisher, Ohmsha" Control system "

  However, in the conventional multiprocessor system, the shared memory 2 is installed outside the semiconductor chip of each of the processors 1A to 1N, so that the operation clock of the arithmetic processors 11A to 11N is increased and the built-in memory on the same semiconductor chip is used. The time required for the read / write operation from the external bus IFs 13A to 13N to the outside of the semiconductor chip such as the shared memory 2 via the common bus 9 is relatively longer than the time required for the read / write operation to 12A to 12N. It has become.

  In addition, since the local memories 42A to 42N and the local I / Os 43A to 43N are connected to the external bus IFs 13A to 13N via the local buses 4A to 4N, the local memories 42A to 42N or the local I / Os 43A to 43N are connected. In this case, this access is performed in a time-sharing manner with access to the shared memory 2 via the common bus 9. In this case, the time required for the read / write operation to the outside of the semiconductor chip such as the shared memory 2 via the common bus 9 is further increased.

In a general-purpose arithmetic processor, it is unclear when the data read into the arithmetic processors 11A to 11N is used, particularly for the read operation, depending on the program. For this reason, the program processing is stopped until the read data is stored in the internal registers of the arithmetic processors 11A to 11N.
For these reasons, there is a problem that reading and writing to the shared memory 2 which is essential in the multiprocessor system lowers the program processing efficiency.
The present invention has been made in view of such problems, and an object of the present invention is to provide a multiprocessor system capable of preventing a decrease in program processing efficiency due to reading and writing to a shared memory.

In order to achieve the above object, a multiprocessor system according to claim 1 of the present invention is a semiconductor chip in which data is transferred between an arithmetic processor, a built-in memory capable of reading and writing data, and a local bus outside the semiconductor chip. In a multiprocessor system in which a plurality of processors each having an external bus interface for performing input / output of each other share and exchange data with each other, a memory used for sharing and exchanging the data in the plurality of processors A virtual shared memory having a capacity and deployed in the built-in memory, a common bus interface used for sharing and exchanging the data, and a storage area of the virtual shared memory designated independently of the arithmetic processor And a DMA processor for performing a copying operation from one storage area to another storage area. A common bus that is used to share and exchange of the data by connecting the common bus interface, specifying signal that specifies the format of the data write and read operations with respect to the trigger signal and the virtual shared memory to start the DMA processor And a transmission bus for transmitting a trigger signal and a designation signal from the generation means to the DMA processor of each processor , wherein the DMA processor responds to the trigger signal and the designation signal. Data writing and reading operations from a memory are performed .

According to this configuration, in order to share and exchange data, the arithmetic processor of each processor does not need to provide a shared memory outside the semiconductor chip as in the prior art and directly access it, but the built-in memory on the same semiconductor chip What is necessary is just to write / read to / from the virtual shared memory. In addition, the operation to input / output data to / from the local bus via the external bus interface and the operation to share / exchange data to / from the common bus via the common bus interface should be performed independently. Can do. As a result, when accessing the common bus as in the prior art, access to the local bus and time division are not performed. In the present invention, the access to the common bus and the access to the local bus are reduced. Can be done in parallel.
Further, according to the above configuration, each processor can perform writing / reading to / from the virtual shared memory in accordance with predetermined data write / read operation formats.

  A multiprocessor system according to a second aspect of the present invention is the multiprocessor system according to the first aspect, wherein the virtual shared memory is divided into write areas for the plurality of processors, and the arithmetic processor is a virtual shared memory in its own processor. Data is shared / exchanged by writing data to other processor's write area to other processor's write area and reading data notified by other processors from areas other than its own processor's write area of the virtual shared memory It is characterized by.

  According to this configuration, for example, the arithmetic processor of the processor A writes data to be notified to the other processors B to N to the area A of the virtual shared memory, and the data notified from the other processors B to N is stored in the virtual shared memory. Data is shared and exchanged by reading from the areas B to N. The same applies to the other processors B to N. By such an operation, the arithmetic processor of each processor does not need to directly access the shared memory outside the semiconductor chip in order to share and exchange data, but to the virtual shared memory in the built-in memory on the same semiconductor chip. Write and read may be performed.

The multiprocessor system according to claim 3 of the present invention is the multiprocessor system according to claim 1 or 2 , wherein the generation means sends, as the trigger signal, data to be notified to another processor written in the virtual shared memory to the common bus. A first trigger signal for timing to output, and a second trigger signal for timing to read data notified from another processor transmitted from the common bus from the common bus, the first trigger signal Is generated at a timing earlier than that of the second trigger signal.
According to this configuration, when data is output from the own processor to the common bus at the timing of the first trigger signal, the output data is read by another processor at the timing of the second trigger signal. Can be replaced properly.

According to a fourth aspect of the present invention, there is provided a multiprocessor system according to the first or second aspect , wherein the virtual shared memory is provided outside the built-in memory and provided in the processor, and the generation means includes the designation signal as the designation signal. The DMA processor generates a first designation signal that designates an upper address for the virtual shared memory and a second designation signal that designates a lower address, and the DMA processor responds to the first and second designation signals. Data write and read operations are performed by designating upper and lower addresses for the virtual shared memory.
According to this configuration, the arithmetic processor can share and exchange data with other processors by writing data to the own area of the virtual shared memory in the own processor and reading data from the other area.

  As described above, according to the present invention, there is an effect that it is possible to prevent a decrease in program processing efficiency due to reading and writing to the shared memory.

Hereinafter, embodiments of the present invention will be described with reference to the drawings. However, parts corresponding to each other in all the drawings in this specification are denoted by the same reference numerals, and description of the overlapping parts will be omitted as appropriate.
(Embodiment)
FIG. 1 is a block diagram showing a configuration of a multiprocessor system according to an embodiment of the present invention.
The configuration of the multiprocessor system shown in FIG. 1 that is different from the conventional multiprocessor system shown in FIG. 10 will be described.
The processors 1A to 1N are provided with common bus IFs 15A to 15N, which are interface circuits for accessing the bus, and the common bus 92 is connected to the common buses IF 15A to 15N. Further, DMA processors 14A to 14N are provided, and the common bus IF 15 and the DMA processor 14 are connected together with the arithmetic processor 11, the built-in memory 12 and the external bus IF 13 through internal buses 19A to 19N.

The built-in memories 12A to 12N are readable / writable memories of the processors 1A to 1N, each formed of a semiconductor chip. Inside the storage memories 12A to 121N (simply referred to as areas) Also called).
The capacity of the virtual shared memory 121 is the same as the storage capacity actually used for data sharing in the shared memory 2 shown in FIG. 10, and the allocation of the storage area is as shown in FIG. Dedicated write areas A to N of the processors 1A to 1N are allocated.

As shown in FIG. 2B, in the virtual shared memory 121A representing each of the virtual shared memories 121A to 121N, in the area A, the arithmetic processor 11A of the own processor 1A writes data, and the written data is This is an area where the DMA processor 14A of its own processor 1A reads and outputs it to the other processors 1B to 1N via the common bus 92.
In the other areas B to N, the DMA processor 14A of the own processor 1A reads and writes data from the other processors 1B to 1N via the common bus 92, and the arithmetic processor 11A of the own processor 1A writes the written data. This is the area to read.

Furthermore, all the areas A to N are areas from which data written by the arithmetic processor 11 of the processor 1A can be read.
In addition, a trigger signal generator 7 connected to each of the processors 1A to 1N via a trigger signal transmission bus 8 is provided. The trigger signal generator 7 generates a trigger signal for starting up the DMA processor 14. The trigger signal transmission bus 8 transmits the trigger signal generated from the trigger signal generator 7. The trigger signal transmission bus 8 may be composed of a plurality of signal lines.

From the trigger signal generator 7 to the trigger signal transmission bus 8, each of the DMA processors 14 </ b> A to 14 </ b> N generates a trigger signal 831 that gives data output to the common bus 92 or data read timing from the common bus 92. Has been transmitted.
Further, from the trigger signal generator 7 to the trigger signal transmission bus 8, as shown in FIGS. 3 and 4, each DMA processor 14 </ b> A to 14 </ b> N reads out data from a specified area of the virtual shared memory 121 to share the common bus. A type designation signal 832 is also generated and transmitted for designating the operation of outputting to the designated area 92 or reading data from the common bus 92 and writing to the designated area of the virtual shared memory 121.

In the type designation signal 832, the trigger type X between times t1 and t2 shown in time series in FIG. 4 , the trigger type XX between times t2 and t3, and the trigger type XXX between times t2 and t3 are constant in that order. Repeated in a cycle.
Also, each triggering of the trigger signal 831 in the order of timings shown in (1) to (5) causes each of the DMA processors 14A to 14N to send a type designation signal for the virtual shared memory 121 in accordance with a rule set in advance for each of the DMA processors 14A to 14N. The data from the offset address of the memory area specified by 832 is read and output to the common bus 92, or the data of the memory area specified by the type specifying signal 832 of the virtual shared memory 121 is read from the common bus 92. Write to the offset address.

  As a result, the data in the own area of the virtual shared memory 121A of the processor 1A is copied to the area for the processor 1A of the virtual shared memories 121B to 121N of the other processors 1B to 1N. Similarly, the data in the own area of the virtual shared memory 121x in the processor 1x is also copied to the area for the processor 1x in the virtual shared memory 121 of another processor.

If the frequency of writing to the own area of the virtual shared memory 121 of the arithmetic processor 11 is longer than one cycle of “trigger type X → XX → XXX” of the type designation signal 832, the writing is performed in the virtual shared memory 121 in another processor. Is copied. Therefore, it is not necessary for the arithmetic processors 11A to 11N of each processor to provide the shared memory 2 outside the semiconductor chip as in the prior art and to directly access it in order to share and exchange data. What is necessary is just to write / read to the virtual shared memories 121A to 121N.
Further, unlike the prior art, when accessing the common bus 92, the access to the local buses 4A to 4N and the time division are not executed. In the present embodiment, access to the common bus 92 and access to the local buses 4A to 4N can be performed in parallel.

Hereinafter, specific examples based on the present embodiment will be described.
Example 1
The configuration of the multiprocessor system according to the first embodiment is the same as that of the multiprocessor system described in the above embodiment.
In the first embodiment, the DMA processors 14A to 14N are set to be described with reference to FIGS.
In the case of the trigger signal 831 at the timing indicated by (1) in the case of the trigger type X, the DMA processor 14A sets the offset address 0 in the area A of the virtual shared memory 121A as shown in the S1 row between the times t1 and t2. Data is read and output to the common bus 92. When the trigger signal 831 has the timing shown in (2), the data at the offset address 1 in the area A of the virtual shared memory 121A is read and output to the common bus 92. That is, a setting is made to increment or decrement the offset address of the area A of the virtual shared memory 121A to be read according to the count number of the trigger signal 831.

In the case of the trigger signal 831 at the timing indicated by (1) in the case of the trigger type XX, the DMA processor 14A reads the data from the common bus 92 and virtually shares as shown in the S1 line between the times t2 and t3. Write to offset address 0 in area B of memory 121A. In the case of the trigger signal 831 at the timing indicated by (2), data is read from the common bus 92 and written to the offset address 1 in the area B of the virtual shared memory 121A. That is, a setting is made to increment or decrement the offset address of the area B of the virtual shared memory 121A to be written according to the count number of the trigger signal 831.
Further, in the case of the trigger type XXX or the like, the DMA processor 14A, as shown in the S1 line between the times t3 and t4, similarly to the above, according to the count number of the trigger signal 831, the area N of the virtual shared memory 121A to be written. Settings are made to increment or decrement the offset address.

  Next, as shown in the S2 line between times t1 and t2, the DMA processor 14B reads the data from the common bus 92 when the trigger signal 831 has the timing indicated by (1) in the case of the trigger type X, and performs virtual processing. Write to offset address 0 in area A of shared memory 121B. In the case of the trigger signal 831 at the timing indicated by (2), data is read from the common bus 92 and written to the offset address 1 in the area A of the virtual shared memory 121B. That is, a setting is made to increment or decrement the offset address of the area B of the virtual shared memory 121A to be written according to the count number of the trigger signal 831.

  Further, when the trigger signal 831 at the timing indicated by (1) in the case of the trigger type XX, the DMA processor 14B, as shown in the S2 line between the times t2 and t3, the offset address of the area B of the virtual shared memory 121B 0 data is read and output to the common bus 92. In the case of the trigger signal 831 at the timing indicated by (2), the data at the offset address 1 in the area B of the virtual shared memory 121B is read and output to the common bus 92. That is, a setting is made to increment or decrement the offset address of the area B of the virtual shared memory 121B to be read according to the count number of the trigger signal 831.

Further, in the case of the trigger type XXX or the like, the DMA processor 14B, as shown in the S2 line between the times t3 and t4, similarly to the above, according to the count number of the trigger signal 831, the area N of the virtual shared memory 121B to be written. Settings are made to increment or decrement the offset address.
Further, the DMA processor 14N is also set to perform the same operation as the DMA processors 14A and 14B, as shown in the Sn row between times t1 and t4.

By such a setting operation, the arithmetic processor 11A of the processor 1A causes the other processor 1B to write data to the area A of the virtual shared memory 121A in the own processor and read data from the other areas B to N. Data sharing and exchange with ~ 1N can be performed.
Similarly, the arithmetic processors 11B to 11N of the other processors 1B to 1N can also write the data to the own area of the virtual shared memory 121 and read the data from the other areas B to N in the other processors 1A to 1N. 1N can share and exchange data.

(Example 2)
The configuration of the multiprocessor system of the second embodiment is basically the same as the configuration of the first embodiment, except that the trigger signal transmission bus 8 is configured as shown in FIG. 5, and the common bus IF 15 is as shown in FIG. As shown in FIG.
In the first embodiment, the DMA processors 14A to 14N are simultaneously operated with the same trigger signal 831. For example, the output to the common bus 92 by the DMA processor 14A and the reading from the common bus 92 by the DMA processors 14B to 14N are operating simultaneously. However, depending on how the processor internal buses 19A to 19N are used, the DMA processors 14A to 14N cannot always operate simultaneously. The second embodiment is an example in which it is considered as described below.

The common bus IF15 shown in FIG. 6 includes a latch register 151 connected to the internal bus 19, a tristate output buffer 152 connected between the latch register 151 and the common bus IF15, the common bus IF15, and the internal bus 19. And an input buffer 153 connected between them.
When data is set during writing from the internal bus 19, the latch register 151 outputs the same data to the common bus IF 15 until the next writing to the latch register 151 is performed. Therefore, when each DMA processor 14 outputs data to the common bus 92, the output of the same data to the common bus 92 is continued until the next operation even if the operation ends.

The trigger signal transmission bus 8 shown in FIG. 5 is configured such that trigger signals 831A to 831N dedicated to the processors 1A to 1N and a type designation signal 832 are transmitted as the trigger signal 831. That is, the trigger signal generator 7 generates the trigger signals 831A to 831N and the type designation signal 832.
As shown in (1) of FIG. 7, the trigger signals 831A to 831N are the trigger signals 831B for the DMA processor 14 that reads data from the common bus 92. It is output from the trigger signal generator 7 before 831N. The time difference between the trigger signals 831A to 831N is determined from the maximum time, although the time from the reception of the trigger signal 831x to the end of the operation of the DMA processor 14x varies depending on the use status of the processor internal bus 19.

With the configuration of the common bus IF 15 in FIG. 6, even if the operation of the DMA processor 14 that outputs data to the common bus 92 is completed, until the next operation is performed, the data state of the common bus 92 shown in FIG. Data is stored in
Then, the arithmetic processors 11A to 11N are operated in the own processor by the same operation as shown in the S1 to Sn rows between the times t1 and t4 in the first embodiment (the operation corresponding to FIG. 7 is also indicated by the same symbol). The data can be shared and exchanged with the processors 1A to 1N by writing data to the own area of the virtual shared memory 121 and reading data from other areas.

(Example 3)
The multiprocessor system of the third embodiment is configured as shown in FIG. 8, and the trigger signal transmission bus 8 is configured as shown in FIG.
First, the trigger signal transmission bus 8 shown in FIG. 9 expands the type designation signal 832 of the trigger signal transmission bus 8 shown in FIG. 5 so that an area designation signal (upper address signal) 833 and an offset address in the area are obtained. A signal (lower address signal) 834 is transmitted. That is, the trigger signal generator 7 generates a region designation signal 833 and an offset address designation signal 834.

  In the multiprocessor system shown in FIG. 8, the virtual shared memory 121 in the built-in memory 12 of the multiprocessor system shown in FIG. 1 is separated as virtual shared memories 16A to 16N of dual port memories built in the semiconductor chip. Is. One ports of the virtual shared memories 16A to 16N are connected to the internal buses 19A to 19N, and the opposite ports are the common bus 92 and the area designation signal 833 and offset address designation signal of the trigger signal transmission bus 8 via the common bus IF15. 834 is connected to the transmission line.

In the virtual shared memories 16A to 16N, dedicated write areas for the processors 1A to 1N are allocated in the same manner as shown in FIGS.
Further, in the multiprocessor system of FIG. 8, each processor 1A to 1N further includes common bus DMA processors 17A to 17N, which are connected to the internal buses 19A to 19N, and lower addresses of the virtual shared memories 16A to 16N. Is connected to a line for designating with a control signal corresponding to the offset address designation signal 834.

The common bus DMA processors 17A to 17N read the data by designating the upper address with the area designation signal 833 and the lower address with the offset address designation signal 834 with respect to the virtual shared memories 16A to 16N. Output to the bus 92. Furthermore, an operation of reading data from the common bus 92 and writing to the virtual shared memory 16 with the same designation as described above is performed. Further, each data is read from or written to the virtual shared memories 16A to 16N at the timing of the trigger signals 831A to 831N.
The arithmetic processors 11A to 11N can share and exchange data with the processors 1A to 1N by writing data to the own area of the virtual shared memory 16 in the own processor and reading data from another area.

According to the first to third embodiments described above, the arithmetic processors 11A to 11N do not need to directly access the shared memory outside the semiconductor chip in order to share and exchange data, and the built-in memory on the same semiconductor chip. What is necessary is just to write / read data to / from the virtual shared memories 121A to 121N or the virtual shared memories 16A to 16N.
Generally, the time required for the read / write operation for the built-in memory on the same semiconductor chip is much shorter than the time required for the read / write operation to the outside of the semiconductor chip via the external bus IFs 13A to 13N.

In this embodiment, since the local buses 4A to 4N and the common bus 92 are separated, the access to the local buses 4A to 4N when accessing the common bus 92 via the external bus IF 13 as in the prior art. Access to the common bus 92 and access to the local buses 4A to 4N can be performed in parallel without being executed in a time division manner.
Therefore, it is possible to prevent a decrease in program processing efficiency due to reading and writing to the shared memory that is essential in the multiprocessor system.

It is a block diagram which shows the structure of the multiprocessor system which concerns on embodiment of this invention. The shared memory and virtual shared memory of the multiprocessor system which concern on the said embodiment are shown, (a) is the allocation figure of the storage area of virtual shared memory, (b) is the write-read operation | movement to each storage area of virtual shared memory. It is explanatory drawing. It is a figure which shows the structure of the trigger signal transmission bus | bath in the multiprocessor system of Example 1 which concerns on the said embodiment. 3 is a timing chart of a type designation signal and a trigger signal in the multiprocessor system of the first embodiment. It is a figure which shows the structure of the trigger signal transmission bus | bath in the multiprocessor system of Example 2 which concerns on the said embodiment. It is a block diagram which shows the structure of common bus IF in the multiprocessor system of the said Example 2. FIG. It is a timing chart of the type designation signal and trigger signal and the data state of the common bus in the multiprocessor system of the second embodiment. It is a block diagram which shows the structure of the multiprocessor system of Example 3 which concerns on the said embodiment. It is a figure which shows the structure of the trigger signal transmission bus | bath in the multiprocessor system of the said Example 3. FIG. It is a block diagram which shows the structure of the conventional multiprocessor system.

Explanation of symbols

1A to 1N Processor 2 Shared memory 3 Access arbitration device 4A to 4N Local bus 7 Trigger signal generator 8 Trigger signal transmission bus 12A to 12N Built-in memory 13A to 13N External bus IF
14A to 14N DMA processor 15A to 15N Common bus IF
16A to 16N, 121A to 121N Virtual shared memory 17A to 17N Common bus DMA processor 19A to 19N Internal bus 31A to 31N Access request signal 32A to 32N Access permission signal 41A to 41N Bus driver with enable 42A to 42N Local memory 43A to 43N Local I / O
92 Common bus 151 Latch register 152 Tri-state output buffer 153 Input buffer 831, 831A to 831N Trigger signal 832 Type designation signal 833 Area designation signal 834 Offset address designation signal

Claims (4)

A plurality of processors each having an arithmetic processor, a built-in memory capable of reading and writing data, and an external bus interface for inputting / outputting data to / from a local bus outside the semiconductor chip are provided in the semiconductor chip. In a multiprocessor system that shares and exchanges data,
A virtual shared memory provided in the internal memory having a storage capacity used for sharing and exchanging the data, and a common bus interface used for sharing and exchanging the data; A DMA processor that performs a copying operation from the storage area of the virtual shared memory specified independently of the arithmetic processor to another storage area,
A common bus used for sharing and exchanging the data by connecting the common bus interfaces outside the plurality of processors;
Generation means for generating a trigger signal for starting up the DMA processor and a specification signal for specifying the format of data write and read operations with respect to the virtual shared memory, and the trigger signal and the specification signal from the generation means are transmitted to the DMA of each processor. A transmission bus for transmitting to the processor ,
The multiprocessor system, wherein the DMA processor performs data write and read operations from the virtual shared memory in response to the trigger signal and the designation signal . The virtual shared memory is divided into write areas for the plurality of processors, and the arithmetic processor writes data to be notified to other processors to the write area for the own processor in the virtual shared memory in the own processor, and the virtual shared memory 2. The multiprocessor system according to claim 1, wherein data sharing / exchange is performed by reading data notified by another processor from an area other than the write area for the own processor of the memory. The generation means includes, as the trigger signal, a first trigger signal for timing to output data to be notified to another processor written in the virtual shared memory to the common bus, and another processor transmitted on the common bus. A second trigger signal for timing for reading data notified from the common bus is generated at a timing when the first trigger signal is earlier than the second trigger signal. The multiprocessor system according to claim 1 or 2 . The virtual shared memory is extracted from the internal memory and provided in the processor, and the generation means specifies a first designation signal for designating an upper address for the virtual shared memory as the designation signal, and designation of a lower address The DMA processor performs a data write and read operation by designating upper and lower addresses for the virtual shared memory in accordance with the first and second designation signals. The multiprocessor system according to claim 1 or 2 , wherein:

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