RU1835551C - Data processor - Google Patents

Abstract

The invention relates to computer technology and can be used to build high-speed multiprocessor computing systems. An object of the invention is to increase speed. The device comprises a computing node 1, a state register 2, a communication node with a channel 3, a local memory node 4, an address register 5, a multiplexer b, a local control highway 7, a local information highway 8. 2 ill., 1 table.

Description

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The invention relates to computer technology and can be used to build high-speed multiprocessor computing systems.

The purpose of the invention is to increase the speed of multiprocessor computing systems.

In FIG. 1 shows a diagram of the proposed device; Figure 2 is an example of a state register format.

The device comprises a computing node 1, a state register 2, a communication node with a channel 3, a local memory node 4, an address register 5, a multiplexer b, a local control highway 7, a local information highway 8.

The elements of the device are interconnected as follows. The information inputs and outputs of the computing node, respectively, are connected via local information lines to the information inputs and outputs of the first group of the communication node with the channel and to the information inputs and outputs of the first state register group. The outputs of the group of the computing node through the local control highway are connected respectively to the first control input of the status register and to the first control input of the communication device with a channel, the information inputs and outputs of the second group of which are connected respectively to the information inputs and outputs of the local memory node, control inputs of the channel connected to the outputs of the node. The information inputs and outputs of the computing node, respectively, are connected through local information lines to the information inputs of the address register, to the information inputs and outputs of the first group of the communication node with the channel. The first input of the computing node through the local control highway is connected to the write (read) input of the address register, the outputs of which are connected respectively to the control inputs of the multiplexer, the output connected to the second control input of the communication node with the channel. The information inputs and outputs of the third group of the communication node with the channel are respectively connected to the information inputs and outputs of the first group of the device, the information inputs and outputs of the second group of which are connected respectively to the information inputs and outputs of the second group of the status register, the outputs are connected respectively to the information inputs multiplexer

The output of the latter is connected to the information output of the device. The second output of the computing node through the local control line is connected to the input of synchronization of the address register and multiplexer.

The operation of the device can be considered by the example of a computing system consisting of several data processing devices connected to one system common bus. The computing node 1 of one of the data processing devices selected as the manager loads the necessary programs and data into the local memory nodes and the system memory of the slave computing nodes. After that, the control computing node 1 sets in the status registers 2 bits of access to the system

0 to the bus as necessary (to solve the current problem). Each subordinate computing node polls its own bit. Starting the state register 2, when it is set by the controlling computing node5 to 1, the subordinate computing node begins to execute its program. In the process of work and in the process of the next preparatory stage, the exchange of information between various data processing devices of a multiprocessor computing system is significantly reduced, since it is sufficient to redistribute the memory by writing to transmit the necessary information

5 of the other control word into state registers 2. The memory allocation process is as follows. Let computing node 1 need to go to some address, for example

0 10008 (0 bank).

At the time when the computing node sets the address on the bus, the address value is written to address register 5, and the corresponding 5 value of the control bit of state register 2 is selected on multiplexer b, the received control value will go to the communication node with channel 3 and determine which memory (local or system) is needed,

0 When using this method of memory allocation, the boundaries of programs and data should be aligned with the boundaries of memory banks.

Possible status register format

5 2 is shown in Fig. 2 and is explained in the table. When the Start bit is set to 1, the computational node 1 starts to execute its program. At the end of program execution, the processor resets the Start bit and sets the Goth bit, the remaining bits of state register 2 control access to the local or system memory. All memory, both local and system, is divided into banks. Each memory bank is assigned a bit in status register 2. If the corresponding bit is set to 1, this means that when accessing the addresses of the corresponding memory bank, a system memory bank will be selected; if bit values are O-local memory bank.

. Thus, the proposed device for data processing allows to increase the speed of the multiprocessor system by reducing the time spent by the processing nodes waiting for the system channel to be provided when each of them accesses the system memory for the necessary information.

Claims (1)

SUMMARY OF THE INVENTION A device for processing data comprising a computing node, a local memory node, a communication node with a channel, and a status register, the information inputs and outputs of the computing node, respectively, being connected via local information lines to the information inputs and outputs of the first group of the communication node the channel and to the information inputs and outputs of the first group of the status register} the outputs of the group of the computing node through the local control highway are connected to the first control input of the register state and to the first control input of the communication device with the channel, information inputs-outputs the second group of which is connected respectively to the information inputs / outputs of the local memory node, the control inputs of which are connected to the outputs of the node communication with a channel, characterized in that, in order to increase speed, it comprises an address register and a multiplexer, the information inputs and outputs of the computing node, respectively through local information lines connected to the information inputs of the address register, information inputs and outputs of the first group of the status register and information inputs and outputs of the first group of the communication node with the channel, the first output of the computing node through the local control highway is connected to the write / read input register address whose outputs are connected respectively, to the control inputs of the multiplexer, the output of which is connected to the second control input of the communication node with the channel, the information inputs and outputs of the third group of which are connected respectively to the information inputs and outputs of the first group of the device, the information inputs and outputs of the second group of which are connected respectively to the information inputs and outputs of the status register, the outputs of which are connected respectively to the information inputs of the multiplexer, the output of which is connected to the information output of the device properties, second computing output the node through a local control line is connected to the synchronization inputs of the address register and multiplexer. b l bit d System memory access bum ft. memory bank) / - system memory Q-local memory Figure 1 5р р Зр lp lp Op