JPS62226366A - Shared memory system - Google Patents

Abstract

PURPOSE:To prevent the number of low order processors that can be connected from being restricted by the size of address space of high order processors by providing an FIFO memory for address information transfer, and providing an address register in each shared memory. CONSTITUTION:The system is provided with an vacant address information FIFO (First-In First-Out) memory 4 for transferring address information from a high order processor 1 respective shared memories 12, 22,...,N2, a notification FIFO memory 5 for transferring address information from low order processors 11, 21,...,N1 to the high order processor 1 and an FIFO memories. The position of the shared memories 11, 21,...,N1 on the address space of the high order processor 1 is not determined and arranged dynamically. Thus, the number of shared memories that become in use simultaneously is restricted by the maximum value of the address space of the high order processor 1. However, the number of shared memories that can be connected is not restricted.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a memory sharing method when an upper processor and a plurality of lower processors transfer data between processors via a shared memory.

(Prior Art) Conventionally, when an upper processor and multiple lower processors transfer data between processors via shared memory, the shared memories of all the lower processors are stored in the address space of the upper processor. As an example in Figure 3, there is one upper processor (PROC) 1 and N lower processors (PROC) 11.21.
・, shows the configuration when Nl is connected.

The upper processor 1 has a memory (MEM) 2 whose address is accessed only by the upper processor, and a shared memory (MEM) 2 is provided between the upper processor and each lower processor for each lower processor. ) 12.2
2. ..., N2 are provided, and these shared memories are connected to a path contention control circuit (CONT) 13, 23
．． ..., are each connected to the bus via N3.

FIG. 4 shows the allocation state of the address space of the host processor 1 in this case. The address space of the upper processor is
The total address space of the memory 2 and the address space of the shared memories 12 to N2 is required.

[Problem that the invention seeks to solve]

In the conventional memory sharing method described above, the shared memory area with lower processors must all fit within the address space of the upper processor, so there is an upper limit on the number of lower processors that can be connected based on the address space of the upper processor. The disadvantage is that it is fixed.

It is an object of the present invention to provide a memory sharing scheme that does not have such drawbacks.

[Means for solving problems]

The memory sharing method of the present invention includes one upper processor,
A plurality of lower processors, a shared memory provided for each lower processor between the upper processor and each lower processor, an address register provided for each shared memory, and an address register for transferring address information from the upper processor to the shared memory. It is equipped with a PIFO memory and a FIFO memory for transferring address information from a lower processor to an upper processor, and the address register allows the upper processor to change the address of the shared memory, thereby controlling the total amount of shared memory and the number of connectable lower processors. However, it is characterized by not being limited by the address space of the upper processor.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of a memory sharing system according to an embodiment of the present invention. Here, 1 is the upper processor (PROC),
2 is memory accessed only by the upper processor (ME
M), 12.22. ..., N2 is the lower processor (PROC) 11.21, respectively.
This is a shared memory between Nl and the upper processor 1. 14.
24. ..., N4 is an address register (REG) that each shared memory has, and it determines where each shared memory is located in the address space of the upper processor 1. The corresponding parts are retained.

This memory sharing method further includes each shared memory 12.22. ..., Empty address information FIFO for transferring address information to N2
st 4n First-Out) memory 4 and each lower processor 11, 21 . ..., notification FIFO for transferring address information from Nl to upper processor 1
It includes a memory 5 and a FIFO memory access control circuit 3 that controls access to these FIFO memories.

Next, the operation of this embodiment will be explained.

For example, when the lower processor 11 writes valid data to the shared memory 12, it first reads the data in the empty address information i1r''lFO memory 4 via the FIFO memory access control circuit 3. It contains the high-order bits of the addresses of unused memory blocks allocated to the shared memory section in the address space of 1, and the lower processor 11
reads the upper bits of the address from here, writes valid data to the shared memory 12, and writes the valid data to the address register 1.
4, the upper bits of the address previously read are written into the notification FIFO memory 5 via the FIFO memory IJ access control circuit 3. By reading the notification FIFO memory 5, the upper processor 1 learns at which address valid data is stored, and when that address is accessed, data from the lower processor 11 is read in this case.

In this way, data is transferred from the lower processor 11 to the upper processor 1. When the data on the shared memory 12 becomes unnecessary, the upper processor 1 resets the address register 14 and writes the upper bits of the address into the empty address information FIFO memory 4.

Shared memo from top proce Nosa 1 January L2L...
When writing data to Nl, similarly, empty address information 913 FIFO is written via FIFO memory access control circuit 3.
Read FO memory 4 and address register 14.24
．． ..., Set N4 and write data to the shared memory. In this case, the lower processor 11゜21. ...
・Since each shared memory is located at a fixed address from the perspective of Nl, writing to the notification FIFO memory 5 is unnecessary. When a lower processor accesses a fixed address, it reads data from an upper processor. In this way, data is transferred from the upper processor to the lower processor. When each lower-level processor no longer needs the data on the shared memory, it resets its address register and writes the upper address pin l- into the empty address information FIFO memory 4.

In this memory sharing method, shared memo January 1.21.・・・
. . , the location of Nl in the address space of the higher-level processor 1 is not determined, but is dynamically located as shown in FIG. Therefore, although the number of shared memories that are in use at the same time is limited by the maximum value of the address space of the upper processor l, the number of shared memories that can be connected is not limited.

〔Effect of the invention〕

As explained above, according to the present invention, by providing a FIFO memory for address information transfer and providing an address register in each shared memory, the number of lower-order processors that can be connected is not limited by the size of the address space of the higher-order processor. There is an advantage of not receiving it.

[Brief explanation of drawings]

FIG. 1 is a block diagram of the memory sharing method of the present invention, FIG. 2 is a diagram showing the address space allocation state of the upper processor in the configuration shown in FIG. 1, and FIG. 3 is a block diagram of the conventional memory sharing method. , FIG. 4 is a diagram showing the allocation state of the address space of the upper processor in the case of the configuration of FIG. 3. ■...Upper processor 2...Memory 3...FIFO memory access control circuit

Claims (1)

[Claims] (1) One upper processor, multiple lower processors, a shared memory provided for each lower processor between the upper processor and each lower processor, an address register provided for each shared memory, and a shared memory from the upper processor. FIFO memory for transferring address information to memory;
FIFO memory for transferring address information from the lower processor to the upper processor, and the address register allows the upper processor to change the address of the shared memory, so that the total amount of shared memory and the number of connectable lower processors can be changed from the upper processor to the upper processor. A memory sharing method that is characterized by not being subject to address space limitations.