JPH01154272A - Multiprocessor device - Google Patents

Abstract

PURPOSE:To reduce the overhead required for master and slave processors to perform communication processing by mapping a memory of a slave processor selected by a master processor in a fixed area of a system memory space as a shared memory. CONSTITUTION:A local memory 12 and a shared memory 13 are memory mapped from a CPU 11 and can be seen. While another processor unit 17 acquires a master processor right and accesses the memory 13 via an external system bus 18. In such a case, the series number of the unit 17 containing the memory 13 for accessing is written in a register of a processor selector 14. Thus the memory 13 is mapped in a system memory map and the unit 17 is made accessible. Then the communication of data can be performed with transfer of memories.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a multiprocessor device in which a large amount of data is communicated between a plurality of master processors in a computer system.

Conventional technology Conventional data communication between multiple master processors is
They either communicated through input/output ports or mapped memory into the system's memory space and communicated over it as shared memory.

An example of a data communication device in the above-described conventional multiprocessor system will be described below with reference to the drawings. FIG. 4 shows a block diagram of a conventional multiprocessor device that communicates data via input/output ports. In FIG. 4, 11a, b are CPUs (central processing units), 12aSb are local memories, 16a, b are internal buses, 41a, b are input/output ports, and 42 is a communication line.

Multiprocessor devices that communicate data via conventional input/output ports communicate data in the following manner. First, the CPU 11a reads the contents of the local memory 12a and writes them to the input/output port 41a.

Data passes through the communication line 42 and the other input/output port 41
b takes it inside. The other CP Ull b learns that data has arrived at the input/output port 41b by interrupting or polling the input/output port 41b, reads the data from the input/output port 41b, and writes it into the local memory 12b. This completes the communication of the -word.

Further, FIG. 5 shows a block diagram of a conventional multiprocessor device that communicates data via a shared memory. In Figure 5, 11 is a CPU, 12 is a local memory, 13 is a shared memory, 15 is an external bus controller, 16 is an internal bus, 17 is a processor unit, 18 is an external system bus, and 51 is a shared memory. It is a memory controller.

Conventional multiprocessor devices that communicate data via shared memory communicate data in the following manner.

First, the configuration of the system will be explained. Looking at the memory map in the processor unit 17 from the CPU II, both the local memory blind 2 and the shared memory 13 can be accessed, while the external system.

When the processor unit 17 is viewed from the bus 18, the shared memory 13 is memory mapped. The shared memory controller 51 controls this. In addition, the shared memory controller 51
When a plurality of processor units 17 are connected to the system bus 18, mutual adjustment is made so that the shared memory 13 in each processor unit 17 is not mapped to the same address, and the CPU 11 and the external processor unit 17 are connected to the system bus 18. shared memory 1 simultaneously via 18
Arbitration is performed to avoid accessing the same address in 3. That is, when a plurality of processor units 17 are connected to the system bus 18, the memory map of the entire system as viewed from the CPU II in one processor unit 7 is as shown in FIG. The shared memo January 3 of the processor unit 17 becomes an area corresponding to the number of processor units, and the area of the own local memo January 2.

With such a configuration, one processor unit 17
The shared memo 1/3 in any processor unit 17 can be accessed directly. Data communication can be easily performed by reading and writing data between memories.

Problems to be Solved by the Invention In the above-mentioned method using ports, there is a problem of overhead due to the use of both the multiprocessor and slave processors for communication processing. If you create communication-specific hardware to solve this problem, the problem is that the scale of the hardware will increase.

Another problem with the method using shared memory is that when a large amount of data is communicated, the capacity of the shared memory to be mapped increases, and furthermore, as the number of processors increases, the data cannot be stored in the system memory space.

Means for Solving the Problems In order to solve the above problems, the device of the present invention maps the memory of one slave processor selected by the master processor as shared memory in a fixed area in the system memory space. It is equipped with an address decoder with added functionality so that the master processor can read and write.

Effect of the Invention The present invention enables data communication between two processors, a mask and a slave, in a multiprocessor system by simply adding a small amount of hardware.

Embodiment Hereinafter, the principle of data communication by a multiprocessor uH according to an embodiment of the present invention will be explained with reference to the drawings.

A block diagram is shown in FIG. In Figure 1, 11 is C
In the PU, 12 is a local memory, 13 is a shared memory, 14 is a processor selector, 15 is an external bus controller, 16 is an internal bus, 17 is a processor unit, and 18 is an external system bus.

The operation of the multiprocessor device configured as described above will be described below with reference to FIG. CPUII
From here, the local memory 12 and shared memory 13 can be mapped and viewed.

Meanwhile, another processor unit I7 takes over the master processor right and uses the external system bus 18 to load the shared memory 1
3, first access processor selector 14.
The serial number of the processor unit 17 containing the shared memory 13 to be accessed must be written to the processor select register in the processor unit 17.

By doing so, the shared memory 13 is mapped into the system memory map and is accessible to the mask's processor unit 17.

The system memory map at this time, that is, the memory map seen from the CPU II in the mask processor unit 17 is shown in FIG. Using the memory space mapped in this way, the processor unit 17 of the mask performs data communication by memory transfer.

Next, the inside of the processor selector 14 will be explained with reference to the drawings. A block diagram is shown in FIG. Second
In the figure, 21 is a data bus, 22 is a processor select register, 23 is a match detector, 24 is a processor ID register, 25 is an address bus, 26 is an address decoder, 27 is an address map register,
28 is an address mapping control line, and 29 is a memory select signal line.

The operation of the multiprocessor device configured as described above will be explained below using FIG. 2. The address decoder 26 decodes the address bus 25 when accessed from the internal CPU II, and maps it to the local memory 12 and shared memory 13 spaces set in advance in the address map register 27. On the other hand, when the shared memory 13 is normally accessed from the external system path 18, mapping is not performed. When accessing the shared memory 13 from the external system hash 18, the processor unit 17 is set in the processor select register 22.
Write the serial number and processor ID. Then, the ID number registered in advance in the processor ID register 24 is compared by the match detector 23, and if they are the same, a signal is output to the address mapping control line 28. If a signal is output to the address muffing control line 28, the address decoder 2
6 outputs a signal to the memory select signal line 29 so that the shared memory 13 is mapped to the system memory.

If such a processor selector 1 exists in each processor unit 17 and the processor select register 22 in each processor selector 14 is mapped to the same address on the system memory map, the processor select register 1 as shown in FIG. The shared memory area of the processor unit corresponding to the processor ID written in is mapped to a fixed address in the system memory space. With this method, even if the capacity of the shared memory 13 is increased, or even if the total capacity of the shared memory 13 increases due to an increase in the number of processor units 17, it can be easily handled without making any major changes to the map processor system.

Effects of the Invention As described above, the present invention eliminates the overhead of devoting both the master processor and slave processors to communication processing, and requires less hardware when communicating large amounts of data or when the number of processors increases. This is effective in simplifying the design of system memory space.

[Brief explanation of the drawing]

Figure 1 is an overall block diagram of the present invention, Figure 2 is a detailed block diagram of the processor selector in Figure 1, Figure 3 is a system memory map diagram of the present invention, and Figure 4 is a diagram of the conventional implementation method. Figure 5 is a block diagram of a system when using an input/output boat, which is an example. Figure 5 is a block diagram of a system when using shared memory, which is an example of a conventional implementation method.
The figure is a system memory map diagram when using shared memory, which is an example of a conventional implementation method. 11...CPU, 12...Local memory, 13...Shared memory, 14...
Processor selector, 15...External bus controller, 16...Internal bus, 17...
Processor unit, 18... External system path, 21... Data bus, 22... Processor select register, 23... Coincidence detector, 24... ...Processor ID register, 25.
... Address bus, 26 ... Address decoder, 27 ... Address map register, 2
8...Address mapping control line, 29...
...Memory select signal line, 41a, b...
Input/output boat, 42...Communication line, 51...
...Shared memory controller. Name of agent Patent attorney Toshio Nakao 1 person 21 - Data bus n - Pro 9 preselect register 23 - Coincidence check β unit 24 - Pro Qt ID register 5 - Address bus 26 - Address decoder 29- Left signal line in memory Figure 3 Figure 6

Claims (1)

[Claims] A register that stores its own unique processor serial number in advance, a register that stores the processor serial number instructed by an external master processor, a match detector that compares the contents of these two registers and detects a match, and an internal memory A multiprocessor device comprising, for each processor, an address decoder that performs address mapping in conjunction with its match detector.