JPH05120207A - Data transfer system - Google Patents

Data transfer system

Info

Publication number
JPH05120207A
JPH05120207A JP30562491A JP30562491A JPH05120207A JP H05120207 A JPH05120207 A JP H05120207A JP 30562491 A JP30562491 A JP 30562491A JP 30562491 A JP30562491 A JP 30562491A JP H05120207 A JPH05120207 A JP H05120207A
Authority
JP
Japan
Prior art keywords
data
cpu
bus
cpus
code
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP30562491A
Other languages
Japanese (ja)
Inventor
Susumu Aoki
晋 青木
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Takaoka Toko Co Ltd
Original Assignee
Takaoka Electric Mfg Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Takaoka Electric Mfg Co Ltd filed Critical Takaoka Electric Mfg Co Ltd
Priority to JP30562491A priority Critical patent/JPH05120207A/en
Publication of JPH05120207A publication Critical patent/JPH05120207A/en
Pending legal-status Critical Current

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Abstract

PURPOSE:To transfer data at a high speed without requiring a host CPU which controls the data transfer when the data transfer is performed among plural CPUs through a single bus. CONSTITUTION:Dual-port memories 4, 5, and 6 which can be accessed in series from the side of the bus 7 and at random from the sides of the CPUs 1, 2, and 3 are provided between the CPUs 1, 2, and 3 and the bus 7, and the data transfer system consists of a bus arbitrating circuit 8 which receives and arbitrates bus request signals from the CPUs 1, 2, and 3 and outputs a bus use permission signal to only one CPU and a selecting circuit 9 which receives the code of the data reception side CPU from the CPU having received the bus use permission signal and selects the dual-port memory connected to the data reception side CPU.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】この発明は複数CPU間でのデ−
タ転送方式に関する。
BACKGROUND OF THE INVENTION The present invention relates to data processing between a plurality of CPUs.
Data transfer method.

【0002】[0002]

【従来の技術】従来、複数CPUにより並列処理を行う
装置において、単一バスでCPU間のデ−タ転送を行う
には、複数CPUのうちの1つがホストCPUとなりこ
のホストCPUの制御のもとでデ−タ転送を行う方法
や、バスにグロ−バルメモリを接続して、このグロ−バ
ルメモリを介してデ−タ転送を行う方式などがある。
2. Description of the Related Art Conventionally, in a device for performing parallel processing by a plurality of CPUs, in order to transfer data between the CPUs by a single bus, one of the plurality of CPUs becomes a host CPU and the control of this host CPU is also performed. There is a method of performing data transfer by using, or a method of connecting a global memory to the bus and performing data transfer via this global memory.

【0003】[0003]

【発明が解決しようとする課題】しかしながら、この従
来の前者の方法においては、実際に演算処理を行うCP
U以外にデ−タ転送を制御するホストCPUが必要とな
り、さらに制御を行う信号線や各CPUがホストCPU
に対して行う転送要求や受信要求のための信号線が必要
となる。
However, in the former method of the related art, the CP which actually performs the arithmetic processing is used.
In addition to U, a host CPU for controlling data transfer is required, and the signal line for controlling and each CPU are host CPUs.
A signal line for a transfer request or a reception request to be sent to is required.

【0004】また後者においては、1回のデ−タ転送に
おいてデ−タ送り側CPUからグロ−バルメモリへのデ
−タ書き込みと、グロ−バルメモリからデ−タ受け側C
PUへのデ−タ読み出しとの2回のアクセスが必要とな
り、デ−タ転送に時間がかかる。さらにグロ−バルメモ
リへの書き込みおよび読み出しアドレスの制御が必要と
なる。
In the latter case, in one data transfer, the data sending side CPU writes data to the global memory and the global memory sends data to the data receiving side C.
It is necessary to access the PU twice, that is, to read the data, and it takes time to transfer the data. Furthermore, it is necessary to control the write and read addresses to the global memory.

【0005】そこでこの発明は、単一バスで複数CPU
間のデ−タ転送を行う場合に、デ−タ転送の制御を行う
ホストCPUを必要とせず、高速でデ−タ転送を行える
ようにしたものである。
Therefore, according to the present invention, a plurality of CPUs are provided by a single bus.
In the case of performing data transfer between them, the host CPU for controlling the data transfer is not required and the data transfer can be performed at high speed.

【0006】[0006]

【課題を解決するための手段】この発明においては、複
数CPUのそれぞれに対してバス側からはシリアルアク
セス可能で前記CPU側からはランダムアクセス可能な
デュアルポ−トメモリを設けるとともに、デ−タ転送時
において前記複数CPUのうちのデ−タ送り側CPUか
ら出力されたバス要求信号を受け取り、前記バスが未使
用状態になるまで待って、前記デ−タ送り側CPUにバ
ス使用許可信号を返すバス調停回路と、前記デ−タ送り
側CPUから出力されたデ−タ受け側前記各CPU毎に
決められたコ−ドを受け取り、そのデ−タ受け側CPU
に接続された前記デュアルポ−トメモリへセレクト信号
を出力するセレクト回路とを設けて、前記デ−タ送り側
CPUから、そのデ−タ送り側CPUのコ−ドとしての
自己の前記コ−ドと転送デ−タ数および転送デ−タを前
記デ−タ受け側CPUに接続されたデュアルポ−トメモ
リへ書き込み、前記複数CPUはそれぞれに接続された
前記各デュアルポ−トメモリから必要デ−タを前記デ−
タ送り側CPUのコ−ドにより選択して読み出すように
する。
According to the present invention, a dual port memory which can serially access from the bus side and random access from the CPU side is provided for each of a plurality of CPUs, and at the time of data transfer. A bus which receives a bus request signal output from the data sending side CPU of the plurality of CPUs, waits until the bus is in an unused state, and returns a bus use permission signal to the data sending side CPU The arbitration circuit and the data receiving side, which receives the code determined for each CPU from the data sending side CPU, and receives the data receiving side CPU
And a select circuit for outputting a select signal to the dual port memory connected to the data sending side CPU, and the own code as the code of the data sending side CPU. The number of transfer data and the transfer data are written in the dual port memory connected to the data receiving side CPU, and the plurality of CPUs obtain the necessary data from the respective dual port memories connected to the respective CPUs. −
It is selected and read by the code of the CPU on the data sending side.

【0007】[0007]

【作用】上述したこの発明のデ−タ転送方式において
は、複雑なデ−タ転送の制御やホストCPUを必要とせ
ず、高速な複数CPU間でのデ−タ転送がなされる。
In the above-described data transfer system of the present invention, complicated data transfer control and host CPU are not required, and high-speed data transfer between a plurality of CPUs is performed.

【0008】[0008]

【実施例】以下、この発明の実施例を、CPUの数が3
個の場合について述べる。
Embodiments of the present invention will now be described with reference to the number of CPUs being three.
The case of individual pieces will be described.

【0009】図1は全体のブロック図で、1、2、3は
CPUであり、7はバスである。4、5、6はデュアル
ポ−トメモリでCPU1、2、3とバス7の間にそれぞ
れ設けられており、CPU1、2、3側からはランダム
アクセス可能で、バス7側からはシリアルアクセス可能
である。8はCPU1、2、3からのバス要求信号を受
け取り、バス7の使用に関して調停を行いCPU1、
2、3のうちバス要求信号を出力したCPUのいずれか
1つのみにバス使用許可信号を返すバス調停回路であ
る。9はCPU1、2、3のうちバス調停回路8からバ
ス使用許可信号を受けたCPUからデ−タ受け側CPU
のコ−ドを受け取り、デュアルポ−トメモリ4、5、6
のうちデ−タ受け側CPUに接続されたデュアルポ−ト
メモリをセレクトするセレクト回路である。
FIG. 1 is an overall block diagram, in which 1, 2, 3 are CPUs, and 7 is a bus. Numerals 4, 5 and 6 are dual port memories provided between the CPUs 1, 2 and 3 and the bus 7, respectively. Random access is possible from the CPUs 1, 2 and 3 side and serial access is possible from the bus 7 side. .. 8 receives the bus request signals from the CPUs 1, 2, 3 and arbitrates the use of the bus 7,
A bus arbitration circuit that returns a bus use permission signal to only one of the CPUs that output the bus request signal out of the two or three. 9 is a data receiving side CPU out of the CPUs 1, 2, and 3 which receives the bus use permission signal from the bus arbitration circuit 8.
Of the dual port memory 4, 5, 6
A select circuit for selecting a dual port memory connected to the data receiving CPU.

【0010】バス調停回路8の実施例を図2に示す。図
2のbr1、br2、br3はそれぞれCPU1、2、
3からのバス要求信号で、bg1、bg2、bg3はそ
れぞれCPU1、2、3へのバス使用許可信号でCPU
1、2、3の割り込み入力信号線に接続されている。ま
た、d1、d2は遅延回路である。11、21、31、
24、34はAND回路で、12、22、32、26、
36はOR回路で、13、23、33、25、35はN
OT回路である。
An embodiment of the bus arbitration circuit 8 is shown in FIG. In FIG. 2, br1, br2, br3 are CPUs 1, 2, respectively.
3 is a bus request signal from CPU 3, bg1, bg2, and bg3 are bus use permission signals to CPUs 1, 2 and 3, respectively.
It is connected to the 1, 2, and 3 interrupt input signal lines. Further, d1 and d2 are delay circuits. 11, 21, 31,
24 and 34 are AND circuits, which are 12, 22, 32, 26,
36 is an OR circuit, 13,23,33,25,35 are N
It is an OT circuit.

【0011】CPU1、2、3のいずれからもバス要求
が出力されず、バス要求信号br1、br2、br3が
“0”であれば、OR回路36の出力は“0”であり、
OR回路12、22、32の出力は“1”となる。CP
U1からバス要求が出力され、バス要求信号br1が
“1”になるとAND回路11の出力が“1”になりバ
ス使用許可信号bg1が“1”となると共に、OR回路
26、36の出力が“1”となり、NOT回路13、2
3、33の出力は“0”となる。AND回路11の出力
が“1”なのでOR回路12の出力は“1”のままであ
るが、OR回路22、32の出力は“0”となり、CP
U2、3からのバス要求は、CPU1からのバス要求信
号br1が“0”となりOR回路36の出力が“0”に
なるまで受け付けなくなる。
If no bus request is output from any of the CPUs 1, 2, 3 and the bus request signals br1, br2, br3 are "0", the output of the OR circuit 36 is "0".
The outputs of the OR circuits 12, 22, 32 are "1". CP
When a bus request is output from U1 and the bus request signal br1 becomes "1", the output of the AND circuit 11 becomes "1", the bus use permission signal bg1 becomes "1", and the outputs of the OR circuits 26 and 36 become It becomes "1" and the NOT circuits 13 and 2
The outputs of 3 and 33 are "0". Since the output of the AND circuit 11 is "1", the output of the OR circuit 12 remains "1", but the outputs of the OR circuits 22 and 32 become "0", and CP
The bus requests from U2 and 3 are not accepted until the bus request signal br1 from the CPU1 becomes "0" and the output of the OR circuit 36 becomes "0".

【0012】また、同時にCPU1、2の両方からバス
要求が出力され、バス要求信号br1、br2が“1”
になった場合においては、AND回路11、21の出力
が“1”となり、CPU1へのバス使用許可信号bg1
はただちに“1”となるが、AND回路21からの出力
は遅延回路d1により信号が遅れてAND回路24に入
力され、先にNOT回路25からの出力が“0”とな
り、CPU1からのバス要求信号br1が“0”になる
まで、CPU2へのバス使用許可信号bg2が“0”に
はならない。よってバス調停回路8は、複数のCPUか
らのバス要求信号を入力されてもそのうちの1つのCP
Uへのみバス使用許可信号を出力する。
At the same time, a bus request is output from both the CPUs 1 and 2, and the bus request signals br1 and br2 are "1".
In this case, the outputs of the AND circuits 11 and 21 become "1", and the bus use permission signal bg1 to the CPU 1 is output.
However, the output from the AND circuit 21 is input to the AND circuit 24 with a signal delayed by the delay circuit d1, and the output from the NOT circuit 25 first becomes "0", so that the bus request from the CPU 1 is made. The bus use permission signal bg2 to the CPU2 does not become "0" until the signal br1 becomes "0". Therefore, even if the bus arbitration circuit 8 receives bus request signals from a plurality of CPUs, one of the CPs
The bus use permission signal is output only to U.

【0013】次にセレクト回路9の実施例を図3に示
す。セレクト回路9はCPU1、2、3のアドレス信号
線と接続されており、特定のアドレスつまりデ−タ受け
側CPUのコ−ドがCPU1、2、3のいずれかからア
ドレス信号線を介してセレクト回路9に入力されると、
デ−タ受け側CPUに接続されたデュアルポ−トメモリ
4、5、6へセレクト信号を出力する。実施例におい
て、A0、A1、A2、A3、A4はアドレス信号で、
41、42、43、44はNOT回路、45、46、4
7、48はAND回路である。またcs1、cs2、c
s3は、デュアルポ−トメモリ4、5、6それぞれに接
続されたセレクト信号である。アドレス信号A0、A
1、A2、A3、A4が“1”、“0”、“0”、
“0”、“1”とするとセレクト信号cs1が“1”に
なる。同様にアドレス信号A0、A1、A2A3、A4
が“0”、“1”、“0”、“0”、“1”とするとセ
レクト信号cs2が“1”になり、“1”、“1”、
“0”、“0”、“1”とするとセレクト信号cs3が
“1”となる。
Next, an embodiment of the select circuit 9 is shown in FIG. The select circuit 9 is connected to the address signal lines of the CPUs 1, 2, and 3, and the code of the specific address, that is, the data receiving CPU is selected from any of the CPUs 1, 2, and 3 via the address signal line. When input to the circuit 9,
The select signal is output to the dual port memories 4, 5 and 6 connected to the data receiving side CPU. In the embodiment, A0, A1, A2, A3 and A4 are address signals,
41, 42, 43, 44 are NOT circuits, 45, 46, 4
Reference numerals 7 and 48 are AND circuits. Also, cs1, cs2, c
s3 is a select signal connected to each of the dual port memories 4, 5, and 6. Address signals A0, A
1, A2, A3, A4 are "1", "0", "0",
When it is set to "0" or "1", the select signal cs1 becomes "1". Similarly, address signals A0, A1, A2A3, A4
Is "0", "1", "0", "0", "1", the select signal cs2 becomes "1", and "1", "1",
When it is "0", "0", or "1", the select signal cs3 becomes "1".

【0014】CPU1、2、3がデ−タを送る時の手順
を図4に示す。まず、図4(A)に示すようにバス要求
信号をONにしバス使用許可信号の割り込みが起るまで
待つ。割り込みが起きると図4(B)に示すように割り
当てられたアドレスに、自己のCPUのコ−ドをデ−タ
送り側CPUのコ−ドとして出力し、次に転送デ−タ数
ならびに転送デ−タを出力する。デ−タの出力が終了し
たらバス要求信号をOFFにする。
FIG. 4 shows a procedure when the CPUs 1, 2 and 3 send data. First, as shown in FIG. 4 (A), the bus request signal is turned on and waits until an interrupt of the bus use permission signal occurs. When an interrupt occurs, the code of its own CPU is output to the address assigned as shown in FIG. 4B as the code of the data sending CPU, and then the number of transfer data and the transfer are performed. Output data. When the output of data is completed, the bus request signal is turned off.

【0015】デュアルポ−トメモリには図5に示すよう
に、デ−タ送り側CPUのコ−ドと転送デ−タ数および
転送デ−タが、1ブロックとして送られてきた順に格納
される。
As shown in FIG. 5, the dual port memory stores the code of the data sending side CPU, the number of transfer data, and the transfer data in the order sent as one block.

【0016】CPU1、2、3がデュアルポ−トメモリ
より転送デ−タを受け取る手順を図6に示す。まず、デ
−タ送り側CPUのコ−ドを読み出し、希望するデ−タ
か判断し、そうでなければ転送デ−タ数を読み出し次の
デ−タのブロックの位置を求め再びデ−タ送り側CPU
のコ−ド読み出しを行う。この手順を希望するデ−タが
見つかるまで繰り返す。希望するデ−タが見つかるとそ
のデ−タを読み出す。
FIG. 6 shows a procedure in which the CPUs 1, 2 and 3 receive the transfer data from the dual port memory. First, the code of the CPU on the data sending side is read and it is judged whether it is the desired data. If not, the number of transfer data is read and the position of the block of the next data is obtained and the data is read again. Sending CPU
Code reading is performed. This procedure is repeated until the desired data is found. When the desired data is found, that data is read.

【0017】このようにして複数CPU間のデ−タ転送
を、複雑な制御やデ−タ転送の制御を行うCPUを必要
とせず、しかも高速で行う。
In this way, data transfer between a plurality of CPUs is performed at high speed without the need for complicated control or a CPU that controls data transfer.

【0018】なお、1つのCPUから複数のデュアルポ
−トメモリへ一度にデ−タを転送してもよい。また、デ
−タ送り側CPUコ−ド以外に、デ−タの内容に関する
情報をコ−ド化してデ−タ転送時に送り、デ−タ受け側
CPUでの希望デ−タかどうかの判断にも用いるように
してもよい。
Data may be transferred from one CPU to a plurality of dual port memories at once. In addition to the data sending side CPU code, information relating to the contents of the data is coded and sent at the time of data transfer, and the data receiving side CPU judges whether or not the desired data. May also be used for.

【0019】[0019]

【発明の効果】この発明によれば、前述したようにバス
とCPU間にデュアルポ−トメモリを設けてデ−タ転送
を行うことにより、デ−タ転送の制御を行うホストCP
Uを必要とせず、高速でデ−タ転送を行える。
According to the present invention, as described above, the host CP which controls the data transfer by providing the dual port memory between the bus and the CPU to transfer the data.
High-speed data transfer is possible without requiring U.

【図面の簡単な説明】[Brief description of drawings]

【図1】この発明のデ−タ転送方式の一例を示すブロッ
ク図である。
FIG. 1 is a block diagram showing an example of a data transfer system of the present invention.

【図2】バス調停回路の一例を示す回路図である。FIG. 2 is a circuit diagram showing an example of a bus arbitration circuit.

【図3】セレクト回路の一例を示す回路図である。FIG. 3 is a circuit diagram showing an example of a select circuit.

【図4】デ−タ送り手順を示す図である。FIG. 4 is a diagram showing a data feeding procedure.

【図5】デュアルポ−トメモリに格納されるデ−タの内
容を示す図である。
FIG. 5 is a diagram showing the contents of data stored in a dual port memory.

【図6】デ−タ受け取り手順を示す図である。FIG. 6 is a diagram showing a procedure for receiving data.

【符号の説明】[Explanation of symbols]

1、2、3 CPU 4、5、6 デュアルポ−トメモリ 7 バス 8 バス調停回路 9 セレクト回路 1, 2, 3 CPUs 4, 5, 6 Dual port memory 7 bus 8 bus arbitration circuit 9 select circuit

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】 単一バスにより複数CPU間でデ−タ転
送を行う場合において、 前記複数CPUのそれぞれに対して、前記バス側からは
シリアルアクセス可能で、前記CPU側からはランダム
アクセス可能なデュアルポ−トメモリを設けるととも
に、 デ−タ転送時に前記複数CPUのうちのデ−タ送り側C
PUから出力されたバス要求信号を受け取り、前記バス
が未使用状態になるまで待って前記デ−タ送り側CPU
にバス使用許可信号を返すバス調停回路と、前記デ−タ
送り側CPUから出力されたデ−タ受け側CPUの前記
各CPU毎に決められたコ−ドを受け取り、そのデ−タ
受け側CPUに接続された前記デュアルポ−トメモリへ
セレクト信号を出力するセレクト回路とを設け、 前記デ−タ送り側CPUからそのデ−タ送り側CPUの
コ−ドとしての自己の前記コ−ドと転送デ−タ数および
転送デ−タを、前記デ−タ受け側CPUに接続されたデ
ュアルポ−トメモリに転送し、前記複数CPUはそれぞ
れに接続された前記各デュアルポ−トメモリに書き込ま
れた前記デ−タ送り側CPUのコ−ドにより必要なデ−
タを選択して読み出すデ−タ転送方式。
1. When data is transferred between a plurality of CPUs by a single bus, serial access is possible from the bus side and random access is possible from the CPU side to each of the plurality of CPUs. A dual port memory is provided, and the data sending side C of the plurality of CPUs is used at the time of data transfer.
The bus request signal output from the PU is received, and the data sending side CPU waits until the bus becomes unused.
A bus arbitration circuit which returns a bus use permission signal to the CPU, and a code which is output from the data sending side CPU and which is determined for each CPU of the data receiving side CPU, and which receives the code. A select circuit for outputting a select signal to the dual port memory connected to the CPU is provided, and the data sending side CPU transfers its own code as the code of the data sending side CPU. The number of data and the transfer data are transferred to the dual port memory connected to the data receiving side CPU, and the plurality of CPUs are written to the respective dual port memories connected to the respective CPUs. Required data depending on the code of the data sending CPU
A data transfer method that selects and reads data.
JP30562491A 1991-10-25 1991-10-25 Data transfer system Pending JPH05120207A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP30562491A JPH05120207A (en) 1991-10-25 1991-10-25 Data transfer system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP30562491A JPH05120207A (en) 1991-10-25 1991-10-25 Data transfer system

Publications (1)

Publication Number Publication Date
JPH05120207A true JPH05120207A (en) 1993-05-18

Family

ID=17947378

Family Applications (1)

Application Number Title Priority Date Filing Date
JP30562491A Pending JPH05120207A (en) 1991-10-25 1991-10-25 Data transfer system

Country Status (1)

Country Link
JP (1) JPH05120207A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
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WO1988007937A1 (en) * 1987-04-06 1988-10-20 Daiken Kagaku Kogyo Kabushiki Kaisha Pattern forming sheet and formed pattern fixing process
KR100298234B1 (en) * 1998-12-30 2001-10-26 이계철 Communication method between multiple subsystems and apparatus
KR100709540B1 (en) * 2005-03-04 2007-04-20 후지쯔 가부시끼가이샤 Computer system using serial connect bus, and method for interconnecting a plurality of cpu using serial connect bus

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1988007937A1 (en) * 1987-04-06 1988-10-20 Daiken Kagaku Kogyo Kabushiki Kaisha Pattern forming sheet and formed pattern fixing process
KR100298234B1 (en) * 1998-12-30 2001-10-26 이계철 Communication method between multiple subsystems and apparatus
KR100709540B1 (en) * 2005-03-04 2007-04-20 후지쯔 가부시끼가이샤 Computer system using serial connect bus, and method for interconnecting a plurality of cpu using serial connect bus

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