JP4322451B2 - Data transfer method between DSP memories or between DSP memory and CPU memory (DPRAM) - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a DSP (Digital Signal Processor) inter-memory data transfer method, and in particular, in a device including a plurality of DSPs, data transfer between memories in a plurality of DSPs is realized by a circuit having a simple configuration. The present invention relates to a DSP memory-to-memory data transfer system.
[0002]
[Prior art]
The DSP is a processor specifically designed for digital signal processing operations such as signal processing and communication processing, and usually refers to a programmable processor. In general, a DSP incorporates an arithmetic device such as an ALU (Arithmetic Logic Unit), a memory, an input / output circuit, a peripheral interface, and the like, and can be applied to various devices by rewriting a program. It has the advantage that system functions can be easily changed and added. For this reason, DSPs are now being adopted in many devices such as mobile phone base stations, mobile phone terminals, and moving image processing devices.
[0003]
And, in apparatuses employing these DSPs, parallel processing is performed using a plurality of DSPs in order to cope with an increase in the amount of digital signal processing, an increase in real-time processing, or a demand for high-speed processing. It is coming.
[0004]
In a device that performs parallel processing using a plurality of DSPs, when sharing data among a plurality of DSPs of different types or the same function, or when transferring data for the next processing, It is necessary to transfer data between built-in memories at high speed.
[0005]
In order to perform high-speed data transfer between a plurality of DSP memories, a DPRAM (Dual Port Random Access Memory: dual port RAM) is provided between the DSPs to which data is to be transferred, and DMA (Direct Memory Access: Direct) is provided via the DPRAM. If (memory access) transfer is performed, it is possible to transfer data at the fastest speed.
[0006]
Further, data transfer between a plurality of DSP memories is usually realized by using a bus connecting the DSPs. In this case, a circuit for performing arbitration for sharing the bus among the plurality of DSPs. Is required. For example, when there are two DSPs, one DSP serves as a bus master and the other serves as a slave, so that data can be transferred between the two DSPs. When there are three or more DSPs, the DSP serving as the bus master accepts a data transfer request output from each DSP, and arbitrates the bus.
[0007]
[Problems to be solved by the invention]
In the above-described conventional method of transferring data between a plurality of DSP memories, it is necessary to provide a DPRAM in each of the data transfer paths between the DSPs to which data is to be transferred, and a circuit for arbitrating the shared bus is provided. As the number of DSPs to be used is increased in any case, the entire circuit becomes complicated and the circuit scale becomes large.
[0008]
The present invention has been made to improve the above-described circumstances, and an object of the present invention is to provide a circuit having a simple configuration for transferring data between memories in a plurality of DSPs in an apparatus including a plurality of DSPs. It is an object of the present invention to provide a data transfer system between DSP memories that can be realized by the above.
[0009]
[Means for Solving the Problems]
The data transfer method between the DSP memories or between the DSP memory and the CPU memory (DPRAM) according to the present invention includes a CPU that controls the entire apparatus, a plurality of DSPs that perform digital signal processing, and data from the CPU or the DSP. A transfer request selection circuit for receiving a transfer request signal for transfer, and an instruction signal for receiving and holding the transfer request signal received by the transfer request selection circuit and executing data transfer according to the priority of the transfer request signal A transfer request holding circuit to be sent, and each of the DSPs connected via an expansion bus, receiving the instruction signal sent by the transfer request holding circuit, reading transfer information of the CPU or DSP, and transferring the transfer information. And an expansion bus control circuit for executing data transfer with the CPU or DSP as a transfer destination according to Holds transfer data use, is connected via the CPU and the CPU bus, and the expansion bus control circuit and a DPRAM for reading or writing of the transfer data,
The extension bus control circuit is further connected with a transfer end notification circuit for notifying the end of data transfer,
The expansion bus control circuit holds a transfer information address table in which addresses corresponding to the CPU or the DSP number are written in the transfer information address column.
The address holding the transfer information is the address of the DPRAM in the case of the transfer information of the CPU, and the address of the memory built in the DSP in the case of the transfer information of the DSP.
The transfer information includes at least a transfer data length, a transfer data start address of a transfer source, a transfer destination data receive start address, and whether or not a response is required after data transfer is completed. And

[0014]
The transfer information address table further includes a field for information on a transfer source storage area where data can be transferred and a field for information on a storage area where data can be stored as a transfer destination.
[0015]
Furthermore, when the expansion bus control circuit executes data transfer, if the reading source of the data to be transferred or the output destination of the data to be transferred is the DSP, the data transfer is executed via the expansion bus. Features.
[0016]
DETAILED DESCRIPTION OF THE INVENTION
Next, embodiments of the present invention will be described with reference to the drawings.
[0017]
FIG. 1 is a block diagram showing an embodiment of a data transfer system between DSP memories of the present invention.
[0018]
The embodiment shown in FIG. 1 shows a schematic configuration of a main part of a device 10 such as a mobile phone base station device, and the device 10 is a CPU (Central Processing Unit) that controls the entire device 10. : Central processing unit) 200, a plurality of DSPs (Digital Signal Processors) 100-1, DSP 100-2, DSP 100-n for performing digital signal processing, and transfer request signals for data transfer from the CPU 200 or DSP 100 Transfer request selection circuit 110 that receives 400, and transfer that receives and holds the transfer request signal 400 received by the transfer request selection circuit 110, and sends an instruction signal for executing data transfer according to the priority of the transfer request signal 400 Request holding circuit 120 and DSP The expansion bus control circuit 130 is connected to each of the devices 100 via the expansion bus 300, receives an instruction signal sent from the transfer request holding circuit 120, reads transfer information of the CPU 200 or DSP 100, and executes data transfer according to the transfer information. A transfer end notification circuit 140 connected to the expansion bus control circuit 130 for notifying the end of data transfer, holding transfer data for the CPU 200, connected to the CPU 200 via the CPU bus 310, and an expansion bus control circuit Reference numeral 130 denotes a DPRAM (Dual Port Random Access Memory) 150 that reads or writes transfer data.
[0019]
Here, the features of the present embodiment will be outlined.
[0020]
In this embodiment, regarding the data to be transferred, the transfer data length, the transfer data start address in the transfer source memory holding the transfer data, and the transfer destination DSP 100 (or the CPU 200 as the transfer destination) Information such as the head address for data reception in the memory of the DPRAM 150 (the transfer destination) (this information will be referred to as “transfer information”) is written in advance at a specific address in the predetermined memory. When the transfer request signal 400 with the transfer destination (the number of the DSP 100 or the CPU 200) is output as a data transfer request signal, the expansion bus control circuit 130 reads the previous transfer information and performs data transfer according to the transfer information. Is adopted.
[0021]
Specifically, when data is transferred from the DSP 100, the transfer data length and the data to be transferred are held as transfer information at a predetermined address in a memory in the transfer source DSP 100 (for example, the DSP 100-1). Transfer data start address in the transfer source memory, start address for data reception in the memory of the transfer destination DSP 100 (or DPRAM 150 if the CPU 200 is the transfer destination), and the necessity of a response after the data transfer is completed Etc. are written in advance.
[0022]
When performing data transfer from the CPU 200, the DPRAM 150 is used as a transfer source memory, and a transfer source length and data to be transferred are stored as transfer information at a predetermined address in the transfer source DPRAM 150. The transfer data start address in the DPRAM 150, the start address for data reception in the memory of the transfer destination DSP 100, the necessity of a response after the end of the data transfer, and the like are written in advance.
[0023]
When the DSP 100 or CPU 200 outputs the transfer request signal 400 with the transfer destination as a data transfer request signal, the expansion bus control circuit 130 reads the transfer information of the original DSP 100 or CPU 200 that output the transfer request signal 400, and Data transfer is performed according to the transfer information. The contents of the transfer information are illustrated in FIG.
[0024]
Note that the address described in the transfer data start address (J11 in FIG. 2) or the transfer destination data receive start address (J12 in FIG. 2) shown in FIG. 2 is a transmission buffer or data for data transmission. An address of a transfer area that is specially prepared such as a reception buffer for reception may be indicated, or an arbitrary address that is not a transfer area may be indicated. When referring to the address of the transfer area, it is usually necessary to perform a write operation before transferring the transfer data to the transfer area. However, when referring to an arbitrary address that is not the transfer area, the contents of the address are any contents. Even if it is (variable contents such as data or unchanging contents such as a program), the data transfer from the address is unconditionally performed, and the writing operation before the transfer of the transfer data to the address becomes unnecessary. .
[0025]
Next, the relationship between the extended bus control circuit 130 that executes data transfer according to the transfer information, and each DSP 100 and DPRAM 150 that holds the transfer information will be described with reference to FIG.
[0026]
FIG. 3 is a detailed block diagram for explaining the relationship between the expansion bus control circuit and each DSP and DPRAM. In FIG. 3, components corresponding to those shown in FIG. 1 are denoted by the same reference numerals or symbols, and description thereof is omitted.
[0027]
In FIG. 3, each DSP 100 holds transfer information in a memory 101 built in the DSP 100. The DPRAM 150 also holds transfer information when transferring data from the CPU 200.
[0028]
As described above, the content of the transfer information is information indicating the transfer source and the transfer destination when a data transfer request is generated, and is stored in the transfer source memory 101 (or DPRAM 150) holding the data to be transferred. In addition to the transfer data start address and transfer data length, and the data reception start address in the transfer destination memory 101 (or DPRAM 150), the contents indicate the necessity of a response after the data transfer is completed. .
[0029]
Specifically, as shown in FIG. 3, transfer information when data is transferred from the CPU 200 is described in the address “dddd” of the DPRAM 150, and the address “ "ddvv" is indicated. Further, the transfer information of the DSP 100-1 is described in the address “aaaa” of the memory 101-1 of the DSP 100-1, and the address “aaax” is designated as the transfer data start address of the transfer source in the transfer information. Similarly, for the DSP 100-2 and the DSP 100-n, the transfer information and the transfer data start address of the transfer source are described.
[0030]
On the other hand, the expansion bus control circuit 130 holds a transfer information address table 131. The transfer information address table 131 is a table showing where the transfer information of the CPU 200 or each DSP 100 exists, and the transfer information is held in the column of the transfer information address 133 corresponding to the column of the CPU or DSP number 132. The address is listed. For example, the address of the transfer information of the CPU 200 indicates the address “dddd” of the DPRAM 150, and the address of the transfer information of the DSP-1 whose DSP number is “1” (that is, the DSP 100-1) is that of the memory 101-1. Similarly, the address of the transfer information of DSP-2 (ie, DSP 100-2) is the address “bbbb” of the memory 101-2, and DSP-n (ie, DSP100-) n) indicates that the address of the transfer information is the address “cccc” of the memory 101-n.
[0031]
The contents of the transfer information address table 131 are set at the time of initialization such as when the apparatus 10 is turned on.
[0032]
Next, the operation of the present embodiment shown in FIGS. 1, 2 and 3 will be described in detail with reference to FIG.
[0033]
FIG. 4 is a flowchart for explaining the operation of this embodiment.
[0034]
In FIG. 4, first, the transfer information address table 131 held by the expansion bus control circuit 130 is initialized, and the transfer information is held in the transfer information address 133 column corresponding to the CPU or DSP number 132 column. Is entered (step S1).
[0035]
The transfer information address table 131 may be stored on the RAM in the expansion bus control circuit 130 or may be stored on a ROM (Read Only Memory). In the case of the RAM, the initialization in step S1 may be performed when the apparatus 10 is turned on, or may be set from input means separately provided in the apparatus 10 when necessary. In the case of the ROM, the contents of the transfer information address table 131 are set in advance in the ROM.
[0036]
Next, each of the CPU 200 or the DSP 100 sets transfer information (step S2). The CPU 200 sets transfer information at a predetermined address (address set in the transfer information address table 131) on the DPRAM 150, and the DSP 100 determines a predetermined address (transfer information address table 131 in the memory 101 in the own DSP 100). Set the forwarding information to the address set to. The contents of the transfer information are as shown in FIG.
[0037]
When data transfer becomes necessary, the CPU 200 or the DSP 100 sets the data to be transferred after the address indicated by the transfer data start address (J11 in FIG. 2) in the transfer information (step S3). Specifically referring to FIG. 3 again, since the transfer data start address of the transfer information of the CPU 200 (existing in the DPRAM 150) is “ddvv”, the data to be transferred is the address “ddvv” of the DPRAM 150. Set after. At this time, the length of the data to be transferred is already set to the transfer data length (J10 in FIG. 2) in the transfer information. Since the transfer data head address of the transfer source of the transfer information (existing in the memory 101-1) of the DSP 100-1 is “aaxx”, the data to be transferred is set after the address “aaxx” of the memory 101-1. At this time, the length of the data to be transferred is already set to the transfer data length (J10 in FIG. 2) in the transfer information. The transfer data setting operation in step S3 may be performed only when necessary. For example, when data transfer is performed after the transfer data is written in the transmission buffer, the setting operation in step S3 is required. However, when the transmission buffer is not used, the transfer data start address of the transfer source (FIG. 2) is used. J11) may be changed, i.e., it is not necessary to write transfer data, so the setting operation in step S3 is unnecessary.
[0038]
After setting the transfer data in step S3, the CPU 200 or the DSP 100 sends a transfer request signal 400 with the transfer destination (the number of the DSP 100 or the CPU 200) (step S4).
[0039]
The transfer request signal 400 sent in step S4 is accepted by the transfer request selection circuit 110, and then sent to the transfer request holding circuit 120 for holding. The transfer request holding circuit 120 sends an instruction signal for executing data transfer to the expansion bus control circuit 130 together with information indicating the transfer destination attached to the transfer request signal 400. Further, information for identifying the original DSP 100 or CPU 200 that has output the transfer request signal 400 is added to the instruction signal. The transfer request holding circuit 120 can simultaneously hold a plurality of transfer request signals 400 when a plurality of transfer request signals 400 are sent simultaneously, but holds a plurality of transfer request signals 400. In response to the priority of the transfer request signal 400, the instruction signal for executing the data transfer is sent one by one in the descending order every time the expansion bus control circuit 130 completes one data transfer. . The priority order of the transfer request signal 400 may be determined in advance so that the lower the number from the DSP 100 number, the higher the order, or it may be determined each time by a round robin method or the like.
[0040]
The expansion bus control circuit 130 that has received the instruction signal for executing the data transfer from the transfer request holding circuit 120 identifies the original DSP 100 or CPU 200 that has output the transfer request signal 400 from the instruction signal, and sends the transfer request signal 400 to it. The output transfer information of the original DSP 100 or CPU 200 is read (step S5). If the source of the transfer request signal 400 is, for example, the CPU 200, the transfer information address of the CPU 200 can be found to be “dddd” of the DPRAM 150 by referring to the transfer information address table 131. Transfer information is read from the address “dddd”. Further, if the source of outputting the transfer request signal 400 is, for example, the DSP 100-1, the address of the transfer information of the DSP 100-1 can be found in the DSP 100-1 (ie, DSP-1) by referring to the transfer information address table 131. Since it is understood that the address is “aaaa” in the memory 101-1, the DSP 100-1 is accessed via the expansion bus 300 and the transfer information is read from the address “aaaa”.
[0041]
The expansion bus control circuit 130 that has read the transfer information accesses the transfer data start address (J11 in FIG. 2) described in the transfer information, reads the transfer data, and receives the transfer destination data reception start. The transfer data is transferred by outputting the transfer data read after the address (J12 in FIG. 2) (step S6). When the transfer data start address (J11 in FIG. 2) of the transfer source points to the DPRAM 150, the DPRAM 150 is accessed to read the transfer data. When the transfer data points to the DSP 100, the DSP 100 is connected to the DSP 100 via the expansion bus 300. The transfer data is read by accessing the memory 101. The length of the transfer data to be read is the length described in the transfer data length (J10 in FIG. 2) in the transfer information. When the transfer destination data reception start address (J12 in FIG. 2) indicates the DSP 100, the transfer data is output to the memory 101 of the DSP 100 via the expansion bus 300, and indicates the DPRAM 150. In this case, the transfer data is directly output to the DPRAM 150.
[0042]
When the transfer of the transfer data in step S6 is completed, the expansion bus control circuit 130 refers to the necessity of the response after the completion of the data transfer described in the transfer information (J13 in FIG. 2) and a response is required. In step S7, the transfer end notification circuit 140 is notified of the end of data transfer. The transfer end notification circuit 140 that has received the notification of the end of data transfer outputs an interrupt signal to the CPU 200 to notify whether the data transfer ends normally or abnormally, and to the DSP 100 the expansion bus control circuit 130. An interrupt signal is output via the expansion bus 300 to notify the normal end / abnormal end of the data transfer.
[0043]
After step S7, the process returns to step S3, and the above-described data transfer step is repeatedly executed.
[0044]
Next, a second embodiment of the present invention will be described.
[0045]
In the second embodiment, information is added to the transfer information address table 131 used in the first embodiment to form a transfer information address table 131-1. FIG. 5 shows a second example of the transfer information address table to which information has been added. That is, the transfer information address table 131 shown in FIG. 3 includes two fields: a transfer source storage data storage area column (134 in FIG. 5) and a transfer destination reception data storage area column (135 in FIG. 5). The transfer information address table 131-1 to which two pieces of information are added is used.
[0046]
The transfer data storage area column (134 in FIG. 5) of the transfer source describes information indicating the address of the memory area in the transfer source memory where the transfer data can be stored. The column (135 in FIG. 5) describes information indicating the address of a memory area where received data can be stored on the transfer destination memory.
[0047]
By adding these two pieces of information, when the expansion bus control circuit 130 performs data transfer, when the transfer data is read by accessing the transfer data start address (J11 in FIG. 2) of the transfer source, the transfer data is transferred. It is possible to check in advance whether the data address indicates an abnormal address (such as a nonexistent address), and the data is read after the first address (J12 in FIG. 2) for receiving data at the transfer destination. When outputting the transfer data, it is possible to check in advance whether the address for receiving the data indicates an abnormal address (such as a nonexistent address or a write-protected area).
[0048]
Next, a third embodiment of the present invention will be described.
[0049]
In the third embodiment, the group identification number of the DSP 100 is added to the transfer request signal 400 used in the first embodiment as information indicating the transfer destination. In this system, when a plurality of DSPs 100 are divided into groups in advance and the same data is to be transferred to the entire group, a group identification number of the group is added to the transfer request signal 400, whereby a plurality of DSPs 100 are added. It is possible to transfer the same data simultaneously.
[0050]
【The invention's effect】
As described above, the DSP memory-to-memory data transfer method of the present invention uses the DSP expansion bus and reads the transfer information every time the expansion bus control circuit receives a transfer request signal for data transfer. Since the data transfer is executed, there is an effect that data can be transferred between the DSP memories or between the DSP memory and the CPU memory without imposing a load on the DSP or the CPU. It has an effect that it can be realized by a circuit having the configuration.
[0051]
In addition, since the start address of the transfer data can be arbitrarily specified, there is an effect that data transfer can be performed without performing internal transfer to a transmission buffer or the like as a transfer area.
[0052]
In addition, because it uses a DSP expansion bus, it has the effect of being easily adaptable to DSP expansion.
FIG. 1 is a block diagram showing an embodiment of a data transfer system between DSP memories of the present invention.
FIG. 2 is a diagram illustrating the contents of transfer information.
FIG. 3 is a detailed block diagram illustrating the relationship between an expansion bus control circuit and each DSP and DPRAM.
FIG. 4 is a flowchart for explaining the operation of the embodiment.
FIG. 5 is a diagram illustrating a second example of a transfer information address table.
[Explanation of symbols]
10 Device 100 DSP
101 Memory 110 Transfer Request Selection Circuit 120 Transfer Request Holding Circuit 130 Expansion Bus Control Circuit 131 Transfer Information Address Table 131-1 Transfer Information Address Table 140 Transfer End Notification Circuit 150 DPRAM
200 CPU
300 Expansion bus 310 CPU bus 400 Transfer request signal

Claims (3)

A CPU that controls the entire apparatus, a plurality of DSPs that perform digital signal processing, a transfer request selection circuit that receives a transfer request signal for data transfer from the CPU or the DSP, and the transfer request selection circuit that receives the transfer request signal A transfer request holding circuit for receiving and holding a transfer request signal and sending an instruction signal for executing data transfer according to the priority of the transfer request signal; and connected to each of the DSPs via an expansion bus; An expansion bus control circuit that receives the instruction signal sent from the transfer request holding circuit, reads transfer information of the CPU or the DSP, and executes data transfer with the CPU or the DSP as a transfer destination according to the transfer information; Holds transfer data for the CPU, is connected to the CPU via a CPU bus, and the expansion bus control circuit It includes a DPRAM for reading or writing the send data, and
The extension bus control circuit is further connected with a transfer end notification circuit for notifying the end of data transfer,
The expansion bus control circuit holds a transfer information address table in which addresses corresponding to the CPU or the DSP number are written in the transfer information address column.
The address holding the transfer information is the address of the DPRAM in the case of the transfer information of the CPU, and the address of the memory built in the DSP in the case of the transfer information of the DSP.
The transfer information is composed of at least a transfer data length, a transfer data start address of a transfer source, a start address for receiving data at a transfer destination, and whether or not a response is required after data transfer is completed.
A data transfer system between DSP memories or between a DSP memory and a CPU memory (DPRAM) . 2. The DSP memory according to claim 1, wherein the transfer information address table further includes a field for information on a transfer data storage area that is a transfer source and a field for information on a reception data storage area that is a transfer destination. A data transfer method between a DSP memory and a CPU memory (DPRAM) . When the expansion bus control circuit executes data transfer, if the source of the data to be transferred or the output destination of the data to be transferred is the DSP, the data transfer is executed via the expansion bus. 3. A data transfer method between DSP memories or between a DSP memory and a CPU memory (DPRAM) according to claim 1.

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